iew_impl.hh revision 13652:45d94ac03a27 
1/*
2 * Copyright (c) 2010-2013, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
45#define __CPU_O3_IEW_IMPL_IMPL_HH__
46
47// @todo: Fix the instantaneous communication among all the stages within
48// iew.  There's a clear delay between issue and execute, yet backwards
49// communication happens simultaneously.
50
51#include <queue>
52
53#include "arch/utility.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/fu_pool.hh"
57#include "cpu/o3/iew.hh"
58#include "cpu/timebuf.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/IEW.hh"
62#include "debug/O3PipeView.hh"
63#include "params/DerivO3CPU.hh"
64
65using namespace std;
66
67template<class Impl>
68DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
69    : issueToExecQueue(params->backComSize, params->forwardComSize),
70      cpu(_cpu),
71      instQueue(_cpu, this, params),
72      ldstQueue(_cpu, this, params),
73      fuPool(params->fuPool),
74      commitToIEWDelay(params->commitToIEWDelay),
75      renameToIEWDelay(params->renameToIEWDelay),
76      issueToExecuteDelay(params->issueToExecuteDelay),
77      dispatchWidth(params->dispatchWidth),
78      issueWidth(params->issueWidth),
79      wbNumInst(0),
80      wbCycle(0),
81      wbWidth(params->wbWidth),
82      numThreads(params->numThreads)
83{
84    if (dispatchWidth > Impl::MaxWidth)
85        fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n"
86             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
87             dispatchWidth, static_cast<int>(Impl::MaxWidth));
88    if (issueWidth > Impl::MaxWidth)
89        fatal("issueWidth (%d) is larger than compiled limit (%d),\n"
90             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
91             issueWidth, static_cast<int>(Impl::MaxWidth));
92    if (wbWidth > Impl::MaxWidth)
93        fatal("wbWidth (%d) is larger than compiled limit (%d),\n"
94             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
95             wbWidth, static_cast<int>(Impl::MaxWidth));
96
97    _status = Active;
98    exeStatus = Running;
99    wbStatus = Idle;
100
101    // Setup wire to read instructions coming from issue.
102    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
103
104    // Instruction queue needs the queue between issue and execute.
105    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
106
107    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
108        dispatchStatus[tid] = Running;
109        fetchRedirect[tid] = false;
110    }
111
112    updateLSQNextCycle = false;
113
114    skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
115}
116
117template <class Impl>
118std::string
119DefaultIEW<Impl>::name() const
120{
121    return cpu->name() + ".iew";
122}
123
124template <class Impl>
125void
126DefaultIEW<Impl>::regProbePoints()
127{
128    ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
129    ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
130    /**
131     * Probe point with dynamic instruction as the argument used to probe when
132     * an instruction starts to execute.
133     */
134    ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
135                                              "Execute");
136    /**
137     * Probe point with dynamic instruction as the argument used to probe when
138     * an instruction execution completes and it is marked ready to commit.
139     */
140    ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(),
141                                               "ToCommit");
142}
143
144template <class Impl>
145void
146DefaultIEW<Impl>::regStats()
147{
148    using namespace Stats;
149
150    instQueue.regStats();
151    ldstQueue.regStats();
152
153    iewIdleCycles
154        .name(name() + ".iewIdleCycles")
155        .desc("Number of cycles IEW is idle");
156
157    iewSquashCycles
158        .name(name() + ".iewSquashCycles")
159        .desc("Number of cycles IEW is squashing");
160
161    iewBlockCycles
162        .name(name() + ".iewBlockCycles")
163        .desc("Number of cycles IEW is blocking");
164
165    iewUnblockCycles
166        .name(name() + ".iewUnblockCycles")
167        .desc("Number of cycles IEW is unblocking");
168
169    iewDispatchedInsts
170        .name(name() + ".iewDispatchedInsts")
171        .desc("Number of instructions dispatched to IQ");
172
173    iewDispSquashedInsts
174        .name(name() + ".iewDispSquashedInsts")
175        .desc("Number of squashed instructions skipped by dispatch");
176
177    iewDispLoadInsts
178        .name(name() + ".iewDispLoadInsts")
179        .desc("Number of dispatched load instructions");
180
181    iewDispStoreInsts
182        .name(name() + ".iewDispStoreInsts")
183        .desc("Number of dispatched store instructions");
184
185    iewDispNonSpecInsts
186        .name(name() + ".iewDispNonSpecInsts")
187        .desc("Number of dispatched non-speculative instructions");
188
189    iewIQFullEvents
190        .name(name() + ".iewIQFullEvents")
191        .desc("Number of times the IQ has become full, causing a stall");
192
193    iewLSQFullEvents
194        .name(name() + ".iewLSQFullEvents")
195        .desc("Number of times the LSQ has become full, causing a stall");
196
197    memOrderViolationEvents
198        .name(name() + ".memOrderViolationEvents")
199        .desc("Number of memory order violations");
200
201    predictedTakenIncorrect
202        .name(name() + ".predictedTakenIncorrect")
203        .desc("Number of branches that were predicted taken incorrectly");
204
205    predictedNotTakenIncorrect
206        .name(name() + ".predictedNotTakenIncorrect")
207        .desc("Number of branches that were predicted not taken incorrectly");
208
209    branchMispredicts
210        .name(name() + ".branchMispredicts")
211        .desc("Number of branch mispredicts detected at execute");
212
213    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
214
215    iewExecutedInsts
216        .name(name() + ".iewExecutedInsts")
217        .desc("Number of executed instructions");
218
219    iewExecLoadInsts
220        .init(cpu->numThreads)
221        .name(name() + ".iewExecLoadInsts")
222        .desc("Number of load instructions executed")
223        .flags(total);
224
225    iewExecSquashedInsts
226        .name(name() + ".iewExecSquashedInsts")
227        .desc("Number of squashed instructions skipped in execute");
228
229    iewExecutedSwp
230        .init(cpu->numThreads)
231        .name(name() + ".exec_swp")
232        .desc("number of swp insts executed")
233        .flags(total);
234
235    iewExecutedNop
236        .init(cpu->numThreads)
237        .name(name() + ".exec_nop")
238        .desc("number of nop insts executed")
239        .flags(total);
240
241    iewExecutedRefs
242        .init(cpu->numThreads)
243        .name(name() + ".exec_refs")
244        .desc("number of memory reference insts executed")
245        .flags(total);
246
247    iewExecutedBranches
248        .init(cpu->numThreads)
249        .name(name() + ".exec_branches")
250        .desc("Number of branches executed")
251        .flags(total);
252
253    iewExecStoreInsts
254        .name(name() + ".exec_stores")
255        .desc("Number of stores executed")
256        .flags(total);
257    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
258
259    iewExecRate
260        .name(name() + ".exec_rate")
261        .desc("Inst execution rate")
262        .flags(total);
263
264    iewExecRate = iewExecutedInsts / cpu->numCycles;
265
266    iewInstsToCommit
267        .init(cpu->numThreads)
268        .name(name() + ".wb_sent")
269        .desc("cumulative count of insts sent to commit")
270        .flags(total);
271
272    writebackCount
273        .init(cpu->numThreads)
274        .name(name() + ".wb_count")
275        .desc("cumulative count of insts written-back")
276        .flags(total);
277
278    producerInst
279        .init(cpu->numThreads)
280        .name(name() + ".wb_producers")
281        .desc("num instructions producing a value")
282        .flags(total);
283
284    consumerInst
285        .init(cpu->numThreads)
286        .name(name() + ".wb_consumers")
287        .desc("num instructions consuming a value")
288        .flags(total);
289
290    wbFanout
291        .name(name() + ".wb_fanout")
292        .desc("average fanout of values written-back")
293        .flags(total);
294
295    wbFanout = producerInst / consumerInst;
296
297    wbRate
298        .name(name() + ".wb_rate")
299        .desc("insts written-back per cycle")
300        .flags(total);
301    wbRate = writebackCount / cpu->numCycles;
302}
303
304template<class Impl>
305void
306DefaultIEW<Impl>::startupStage()
307{
308    for (ThreadID tid = 0; tid < numThreads; tid++) {
309        toRename->iewInfo[tid].usedIQ = true;
310        toRename->iewInfo[tid].freeIQEntries =
311            instQueue.numFreeEntries(tid);
312
313        toRename->iewInfo[tid].usedLSQ = true;
314        toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
315        toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
316    }
317
318    // Initialize the checker's dcache port here
319    if (cpu->checker) {
320        cpu->checker->setDcachePort(&cpu->getDataPort());
321    }
322
323    cpu->activateStage(O3CPU::IEWIdx);
324}
325
326template<class Impl>
327void
328DefaultIEW<Impl>::clearStates(ThreadID tid)
329{
330    toRename->iewInfo[tid].usedIQ = true;
331    toRename->iewInfo[tid].freeIQEntries =
332        instQueue.numFreeEntries(tid);
333
334    toRename->iewInfo[tid].usedLSQ = true;
335    toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
336    toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
337}
338
339template<class Impl>
340void
341DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
342{
343    timeBuffer = tb_ptr;
344
345    // Setup wire to read information from time buffer, from commit.
346    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
347
348    // Setup wire to write information back to previous stages.
349    toRename = timeBuffer->getWire(0);
350
351    toFetch = timeBuffer->getWire(0);
352
353    // Instruction queue also needs main time buffer.
354    instQueue.setTimeBuffer(tb_ptr);
355}
356
357template<class Impl>
358void
359DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
360{
361    renameQueue = rq_ptr;
362
363    // Setup wire to read information from rename queue.
364    fromRename = renameQueue->getWire(-renameToIEWDelay);
365}
366
367template<class Impl>
368void
369DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
370{
371    iewQueue = iq_ptr;
372
373    // Setup wire to write instructions to commit.
374    toCommit = iewQueue->getWire(0);
375}
376
377template<class Impl>
378void
379DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
380{
381    activeThreads = at_ptr;
382
383    ldstQueue.setActiveThreads(at_ptr);
384    instQueue.setActiveThreads(at_ptr);
385}
386
387template<class Impl>
388void
389DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
390{
391    scoreboard = sb_ptr;
392}
393
394template <class Impl>
395bool
396DefaultIEW<Impl>::isDrained() const
397{
398    bool drained = ldstQueue.isDrained() && instQueue.isDrained();
399
400    for (ThreadID tid = 0; tid < numThreads; tid++) {
401        if (!insts[tid].empty()) {
402            DPRINTF(Drain, "%i: Insts not empty.\n", tid);
403            drained = false;
404        }
405        if (!skidBuffer[tid].empty()) {
406            DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
407            drained = false;
408        }
409        drained = drained && dispatchStatus[tid] == Running;
410    }
411
412    // Also check the FU pool as instructions are "stored" in FU
413    // completion events until they are done and not accounted for
414    // above
415    if (drained && !fuPool->isDrained()) {
416        DPRINTF(Drain, "FU pool still busy.\n");
417        drained = false;
418    }
419
420    return drained;
421}
422
423template <class Impl>
424void
425DefaultIEW<Impl>::drainSanityCheck() const
426{
427    assert(isDrained());
428
429    instQueue.drainSanityCheck();
430    ldstQueue.drainSanityCheck();
431}
432
433template <class Impl>
434void
435DefaultIEW<Impl>::takeOverFrom()
436{
437    // Reset all state.
438    _status = Active;
439    exeStatus = Running;
440    wbStatus = Idle;
441
442    instQueue.takeOverFrom();
443    ldstQueue.takeOverFrom();
444    fuPool->takeOverFrom();
445
446    startupStage();
447    cpu->activityThisCycle();
448
449    for (ThreadID tid = 0; tid < numThreads; tid++) {
450        dispatchStatus[tid] = Running;
451        fetchRedirect[tid] = false;
452    }
453
454    updateLSQNextCycle = false;
455
456    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
457        issueToExecQueue.advance();
458    }
459}
460
461template<class Impl>
462void
463DefaultIEW<Impl>::squash(ThreadID tid)
464{
465    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
466
467    // Tell the IQ to start squashing.
468    instQueue.squash(tid);
469
470    // Tell the LDSTQ to start squashing.
471    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
472    updatedQueues = true;
473
474    // Clear the skid buffer in case it has any data in it.
475    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
476            tid, fromCommit->commitInfo[tid].doneSeqNum);
477
478    while (!skidBuffer[tid].empty()) {
479        if (skidBuffer[tid].front()->isLoad()) {
480            toRename->iewInfo[tid].dispatchedToLQ++;
481        }
482        if (skidBuffer[tid].front()->isStore() ||
483            skidBuffer[tid].front()->isAtomic()) {
484            toRename->iewInfo[tid].dispatchedToSQ++;
485        }
486
487        toRename->iewInfo[tid].dispatched++;
488
489        skidBuffer[tid].pop();
490    }
491
492    emptyRenameInsts(tid);
493}
494
495template<class Impl>
496void
497DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
498{
499    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
500            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
501
502    if (!toCommit->squash[tid] ||
503            inst->seqNum < toCommit->squashedSeqNum[tid]) {
504        toCommit->squash[tid] = true;
505        toCommit->squashedSeqNum[tid] = inst->seqNum;
506        toCommit->branchTaken[tid] = inst->pcState().branching();
507
508        TheISA::PCState pc = inst->pcState();
509        TheISA::advancePC(pc, inst->staticInst);
510
511        toCommit->pc[tid] = pc;
512        toCommit->mispredictInst[tid] = inst;
513        toCommit->includeSquashInst[tid] = false;
514
515        wroteToTimeBuffer = true;
516    }
517
518}
519
520template<class Impl>
521void
522DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
523{
524    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
525            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
526    // Need to include inst->seqNum in the following comparison to cover the
527    // corner case when a branch misprediction and a memory violation for the
528    // same instruction (e.g. load PC) are detected in the same cycle.  In this
529    // case the memory violator should take precedence over the branch
530    // misprediction because it requires the violator itself to be included in
531    // the squash.
532    if (!toCommit->squash[tid] ||
533            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
534        toCommit->squash[tid] = true;
535
536        toCommit->squashedSeqNum[tid] = inst->seqNum;
537        toCommit->pc[tid] = inst->pcState();
538        toCommit->mispredictInst[tid] = NULL;
539
540        // Must include the memory violator in the squash.
541        toCommit->includeSquashInst[tid] = true;
542
543        wroteToTimeBuffer = true;
544    }
545}
546
547template<class Impl>
548void
549DefaultIEW<Impl>::block(ThreadID tid)
550{
551    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
552
553    if (dispatchStatus[tid] != Blocked &&
554        dispatchStatus[tid] != Unblocking) {
555        toRename->iewBlock[tid] = true;
556        wroteToTimeBuffer = true;
557    }
558
559    // Add the current inputs to the skid buffer so they can be
560    // reprocessed when this stage unblocks.
561    skidInsert(tid);
562
563    dispatchStatus[tid] = Blocked;
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::unblock(ThreadID tid)
569{
570    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
571            "buffer %u.\n",tid, tid);
572
573    // If the skid bufffer is empty, signal back to previous stages to unblock.
574    // Also switch status to running.
575    if (skidBuffer[tid].empty()) {
576        toRename->iewUnblock[tid] = true;
577        wroteToTimeBuffer = true;
578        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
579        dispatchStatus[tid] = Running;
580    }
581}
582
583template<class Impl>
584void
585DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
586{
587    instQueue.wakeDependents(inst);
588}
589
590template<class Impl>
591void
592DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
593{
594    instQueue.rescheduleMemInst(inst);
595}
596
597template<class Impl>
598void
599DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
600{
601    instQueue.replayMemInst(inst);
602}
603
604template<class Impl>
605void
606DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
607{
608    instQueue.blockMemInst(inst);
609}
610
611template<class Impl>
612void
613DefaultIEW<Impl>::cacheUnblocked()
614{
615    instQueue.cacheUnblocked();
616}
617
618template<class Impl>
619void
620DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
621{
622    // This function should not be called after writebackInsts in a
623    // single cycle.  That will cause problems with an instruction
624    // being added to the queue to commit without being processed by
625    // writebackInsts prior to being sent to commit.
626
627    // First check the time slot that this instruction will write
628    // to.  If there are free write ports at the time, then go ahead
629    // and write the instruction to that time.  If there are not,
630    // keep looking back to see where's the first time there's a
631    // free slot.
632    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
633        ++wbNumInst;
634        if (wbNumInst == wbWidth) {
635            ++wbCycle;
636            wbNumInst = 0;
637        }
638    }
639
640    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
641            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
642    // Add finished instruction to queue to commit.
643    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
644    (*iewQueue)[wbCycle].size++;
645}
646
647template <class Impl>
648unsigned
649DefaultIEW<Impl>::validInstsFromRename()
650{
651    unsigned inst_count = 0;
652
653    for (int i=0; i<fromRename->size; i++) {
654        if (!fromRename->insts[i]->isSquashed())
655            inst_count++;
656    }
657
658    return inst_count;
659}
660
661template<class Impl>
662void
663DefaultIEW<Impl>::skidInsert(ThreadID tid)
664{
665    DynInstPtr inst = NULL;
666
667    while (!insts[tid].empty()) {
668        inst = insts[tid].front();
669
670        insts[tid].pop();
671
672        DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
673                "dispatch skidBuffer %i\n",tid, inst->seqNum,
674                inst->pcState(),tid);
675
676        skidBuffer[tid].push(inst);
677    }
678
679    assert(skidBuffer[tid].size() <= skidBufferMax &&
680           "Skidbuffer Exceeded Max Size");
681}
682
683template<class Impl>
684int
685DefaultIEW<Impl>::skidCount()
686{
687    int max=0;
688
689    list<ThreadID>::iterator threads = activeThreads->begin();
690    list<ThreadID>::iterator end = activeThreads->end();
691
692    while (threads != end) {
693        ThreadID tid = *threads++;
694        unsigned thread_count = skidBuffer[tid].size();
695        if (max < thread_count)
696            max = thread_count;
697    }
698
699    return max;
700}
701
702template<class Impl>
703bool
704DefaultIEW<Impl>::skidsEmpty()
705{
706    list<ThreadID>::iterator threads = activeThreads->begin();
707    list<ThreadID>::iterator end = activeThreads->end();
708
709    while (threads != end) {
710        ThreadID tid = *threads++;
711
712        if (!skidBuffer[tid].empty())
713            return false;
714    }
715
716    return true;
717}
718
719template <class Impl>
720void
721DefaultIEW<Impl>::updateStatus()
722{
723    bool any_unblocking = false;
724
725    list<ThreadID>::iterator threads = activeThreads->begin();
726    list<ThreadID>::iterator end = activeThreads->end();
727
728    while (threads != end) {
729        ThreadID tid = *threads++;
730
731        if (dispatchStatus[tid] == Unblocking) {
732            any_unblocking = true;
733            break;
734        }
735    }
736
737    // If there are no ready instructions waiting to be scheduled by the IQ,
738    // and there's no stores waiting to write back, and dispatch is not
739    // unblocking, then there is no internal activity for the IEW stage.
740    instQueue.intInstQueueReads++;
741    if (_status == Active && !instQueue.hasReadyInsts() &&
742        !ldstQueue.willWB() && !any_unblocking) {
743        DPRINTF(IEW, "IEW switching to idle\n");
744
745        deactivateStage();
746
747        _status = Inactive;
748    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
749                                       ldstQueue.willWB() ||
750                                       any_unblocking)) {
751        // Otherwise there is internal activity.  Set to active.
752        DPRINTF(IEW, "IEW switching to active\n");
753
754        activateStage();
755
756        _status = Active;
757    }
758}
759
760template <class Impl>
761bool
762DefaultIEW<Impl>::checkStall(ThreadID tid)
763{
764    bool ret_val(false);
765
766    if (fromCommit->commitInfo[tid].robSquashing) {
767        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
768        ret_val = true;
769    } else if (instQueue.isFull(tid)) {
770        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
771        ret_val = true;
772    }
773
774    return ret_val;
775}
776
777template <class Impl>
778void
779DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
780{
781    // Check if there's a squash signal, squash if there is
782    // Check stall signals, block if there is.
783    // If status was Blocked
784    //     if so then go to unblocking
785    // If status was Squashing
786    //     check if squashing is not high.  Switch to running this cycle.
787
788    if (fromCommit->commitInfo[tid].squash) {
789        squash(tid);
790
791        if (dispatchStatus[tid] == Blocked ||
792            dispatchStatus[tid] == Unblocking) {
793            toRename->iewUnblock[tid] = true;
794            wroteToTimeBuffer = true;
795        }
796
797        dispatchStatus[tid] = Squashing;
798        fetchRedirect[tid] = false;
799        return;
800    }
801
802    if (fromCommit->commitInfo[tid].robSquashing) {
803        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
804
805        dispatchStatus[tid] = Squashing;
806        emptyRenameInsts(tid);
807        wroteToTimeBuffer = true;
808    }
809
810    if (checkStall(tid)) {
811        block(tid);
812        dispatchStatus[tid] = Blocked;
813        return;
814    }
815
816    if (dispatchStatus[tid] == Blocked) {
817        // Status from previous cycle was blocked, but there are no more stall
818        // conditions.  Switch over to unblocking.
819        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
820                tid);
821
822        dispatchStatus[tid] = Unblocking;
823
824        unblock(tid);
825
826        return;
827    }
828
829    if (dispatchStatus[tid] == Squashing) {
830        // Switch status to running if rename isn't being told to block or
831        // squash this cycle.
832        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
833                tid);
834
835        dispatchStatus[tid] = Running;
836
837        return;
838    }
839}
840
841template <class Impl>
842void
843DefaultIEW<Impl>::sortInsts()
844{
845    int insts_from_rename = fromRename->size;
846#ifdef DEBUG
847    for (ThreadID tid = 0; tid < numThreads; tid++)
848        assert(insts[tid].empty());
849#endif
850    for (int i = 0; i < insts_from_rename; ++i) {
851        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
852    }
853}
854
855template <class Impl>
856void
857DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
858{
859    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
860
861    while (!insts[tid].empty()) {
862
863        if (insts[tid].front()->isLoad()) {
864            toRename->iewInfo[tid].dispatchedToLQ++;
865        }
866        if (insts[tid].front()->isStore() ||
867            insts[tid].front()->isAtomic()) {
868            toRename->iewInfo[tid].dispatchedToSQ++;
869        }
870
871        toRename->iewInfo[tid].dispatched++;
872
873        insts[tid].pop();
874    }
875}
876
877template <class Impl>
878void
879DefaultIEW<Impl>::wakeCPU()
880{
881    cpu->wakeCPU();
882}
883
884template <class Impl>
885void
886DefaultIEW<Impl>::activityThisCycle()
887{
888    DPRINTF(Activity, "Activity this cycle.\n");
889    cpu->activityThisCycle();
890}
891
892template <class Impl>
893inline void
894DefaultIEW<Impl>::activateStage()
895{
896    DPRINTF(Activity, "Activating stage.\n");
897    cpu->activateStage(O3CPU::IEWIdx);
898}
899
900template <class Impl>
901inline void
902DefaultIEW<Impl>::deactivateStage()
903{
904    DPRINTF(Activity, "Deactivating stage.\n");
905    cpu->deactivateStage(O3CPU::IEWIdx);
906}
907
908template<class Impl>
909void
910DefaultIEW<Impl>::dispatch(ThreadID tid)
911{
912    // If status is Running or idle,
913    //     call dispatchInsts()
914    // If status is Unblocking,
915    //     buffer any instructions coming from rename
916    //     continue trying to empty skid buffer
917    //     check if stall conditions have passed
918
919    if (dispatchStatus[tid] == Blocked) {
920        ++iewBlockCycles;
921
922    } else if (dispatchStatus[tid] == Squashing) {
923        ++iewSquashCycles;
924    }
925
926    // Dispatch should try to dispatch as many instructions as its bandwidth
927    // will allow, as long as it is not currently blocked.
928    if (dispatchStatus[tid] == Running ||
929        dispatchStatus[tid] == Idle) {
930        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
931                "dispatch.\n", tid);
932
933        dispatchInsts(tid);
934    } else if (dispatchStatus[tid] == Unblocking) {
935        // Make sure that the skid buffer has something in it if the
936        // status is unblocking.
937        assert(!skidsEmpty());
938
939        // If the status was unblocking, then instructions from the skid
940        // buffer were used.  Remove those instructions and handle
941        // the rest of unblocking.
942        dispatchInsts(tid);
943
944        ++iewUnblockCycles;
945
946        if (validInstsFromRename()) {
947            // Add the current inputs to the skid buffer so they can be
948            // reprocessed when this stage unblocks.
949            skidInsert(tid);
950        }
951
952        unblock(tid);
953    }
954}
955
956template <class Impl>
957void
958DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
959{
960    // Obtain instructions from skid buffer if unblocking, or queue from rename
961    // otherwise.
962    std::queue<DynInstPtr> &insts_to_dispatch =
963        dispatchStatus[tid] == Unblocking ?
964        skidBuffer[tid] : insts[tid];
965
966    int insts_to_add = insts_to_dispatch.size();
967
968    DynInstPtr inst;
969    bool add_to_iq = false;
970    int dis_num_inst = 0;
971
972    // Loop through the instructions, putting them in the instruction
973    // queue.
974    for ( ; dis_num_inst < insts_to_add &&
975              dis_num_inst < dispatchWidth;
976          ++dis_num_inst)
977    {
978        inst = insts_to_dispatch.front();
979
980        if (dispatchStatus[tid] == Unblocking) {
981            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
982                    "buffer\n", tid);
983        }
984
985        // Make sure there's a valid instruction there.
986        assert(inst);
987
988        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
989                "IQ.\n",
990                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
991
992        // Be sure to mark these instructions as ready so that the
993        // commit stage can go ahead and execute them, and mark
994        // them as issued so the IQ doesn't reprocess them.
995
996        // Check for squashed instructions.
997        if (inst->isSquashed()) {
998            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
999                    "not adding to IQ.\n", tid);
1000
1001            ++iewDispSquashedInsts;
1002
1003            insts_to_dispatch.pop();
1004
1005            //Tell Rename That An Instruction has been processed
1006            if (inst->isLoad()) {
1007                toRename->iewInfo[tid].dispatchedToLQ++;
1008            }
1009            if (inst->isStore() || inst->isAtomic()) {
1010                toRename->iewInfo[tid].dispatchedToSQ++;
1011            }
1012
1013            toRename->iewInfo[tid].dispatched++;
1014
1015            continue;
1016        }
1017
1018        // Check for full conditions.
1019        if (instQueue.isFull(tid)) {
1020            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1021
1022            // Call function to start blocking.
1023            block(tid);
1024
1025            // Set unblock to false. Special case where we are using
1026            // skidbuffer (unblocking) instructions but then we still
1027            // get full in the IQ.
1028            toRename->iewUnblock[tid] = false;
1029
1030            ++iewIQFullEvents;
1031            break;
1032        }
1033
1034        // Check LSQ if inst is LD/ST
1035        if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
1036            (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1037            (inst->isStore() && ldstQueue.sqFull(tid))) {
1038            DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
1039                    inst->isLoad() ? "LQ" : "SQ");
1040
1041            // Call function to start blocking.
1042            block(tid);
1043
1044            // Set unblock to false. Special case where we are using
1045            // skidbuffer (unblocking) instructions but then we still
1046            // get full in the IQ.
1047            toRename->iewUnblock[tid] = false;
1048
1049            ++iewLSQFullEvents;
1050            break;
1051        }
1052
1053        // Otherwise issue the instruction just fine.
1054        if (inst->isAtomic()) {
1055            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1056                    "encountered, adding to LSQ.\n", tid);
1057
1058            ldstQueue.insertStore(inst);
1059
1060            ++iewDispStoreInsts;
1061
1062            // AMOs need to be set as "canCommit()"
1063            // so that commit can process them when they reach the
1064            // head of commit.
1065            inst->setCanCommit();
1066            instQueue.insertNonSpec(inst);
1067            add_to_iq = false;
1068
1069            ++iewDispNonSpecInsts;
1070
1071            toRename->iewInfo[tid].dispatchedToSQ++;
1072        } else if (inst->isLoad()) {
1073            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1074                    "encountered, adding to LSQ.\n", tid);
1075
1076            // Reserve a spot in the load store queue for this
1077            // memory access.
1078            ldstQueue.insertLoad(inst);
1079
1080            ++iewDispLoadInsts;
1081
1082            add_to_iq = true;
1083
1084            toRename->iewInfo[tid].dispatchedToLQ++;
1085        } else if (inst->isStore()) {
1086            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1087                    "encountered, adding to LSQ.\n", tid);
1088
1089            ldstQueue.insertStore(inst);
1090
1091            ++iewDispStoreInsts;
1092
1093            if (inst->isStoreConditional()) {
1094                // Store conditionals need to be set as "canCommit()"
1095                // so that commit can process them when they reach the
1096                // head of commit.
1097                // @todo: This is somewhat specific to Alpha.
1098                inst->setCanCommit();
1099                instQueue.insertNonSpec(inst);
1100                add_to_iq = false;
1101
1102                ++iewDispNonSpecInsts;
1103            } else {
1104                add_to_iq = true;
1105            }
1106
1107            toRename->iewInfo[tid].dispatchedToSQ++;
1108        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1109            // Same as non-speculative stores.
1110            inst->setCanCommit();
1111            instQueue.insertBarrier(inst);
1112            add_to_iq = false;
1113        } else if (inst->isNop()) {
1114            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1115                    "skipping.\n", tid);
1116
1117            inst->setIssued();
1118            inst->setExecuted();
1119            inst->setCanCommit();
1120
1121            instQueue.recordProducer(inst);
1122
1123            iewExecutedNop[tid]++;
1124
1125            add_to_iq = false;
1126        } else {
1127            assert(!inst->isExecuted());
1128            add_to_iq = true;
1129        }
1130
1131        if (add_to_iq && inst->isNonSpeculative()) {
1132            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1133                    "encountered, skipping.\n", tid);
1134
1135            // Same as non-speculative stores.
1136            inst->setCanCommit();
1137
1138            // Specifically insert it as nonspeculative.
1139            instQueue.insertNonSpec(inst);
1140
1141            ++iewDispNonSpecInsts;
1142
1143            add_to_iq = false;
1144        }
1145
1146        // If the instruction queue is not full, then add the
1147        // instruction.
1148        if (add_to_iq) {
1149            instQueue.insert(inst);
1150        }
1151
1152        insts_to_dispatch.pop();
1153
1154        toRename->iewInfo[tid].dispatched++;
1155
1156        ++iewDispatchedInsts;
1157
1158#if TRACING_ON
1159        inst->dispatchTick = curTick() - inst->fetchTick;
1160#endif
1161        ppDispatch->notify(inst);
1162    }
1163
1164    if (!insts_to_dispatch.empty()) {
1165        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1166        block(tid);
1167        toRename->iewUnblock[tid] = false;
1168    }
1169
1170    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1171        dispatchStatus[tid] = Running;
1172
1173        updatedQueues = true;
1174    }
1175
1176    dis_num_inst = 0;
1177}
1178
1179template <class Impl>
1180void
1181DefaultIEW<Impl>::printAvailableInsts()
1182{
1183    int inst = 0;
1184
1185    std::cout << "Available Instructions: ";
1186
1187    while (fromIssue->insts[inst]) {
1188
1189        if (inst%3==0) std::cout << "\n\t";
1190
1191        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1192             << " TN: " << fromIssue->insts[inst]->threadNumber
1193             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1194
1195        inst++;
1196
1197    }
1198
1199    std::cout << "\n";
1200}
1201
1202template <class Impl>
1203void
1204DefaultIEW<Impl>::executeInsts()
1205{
1206    wbNumInst = 0;
1207    wbCycle = 0;
1208
1209    list<ThreadID>::iterator threads = activeThreads->begin();
1210    list<ThreadID>::iterator end = activeThreads->end();
1211
1212    while (threads != end) {
1213        ThreadID tid = *threads++;
1214        fetchRedirect[tid] = false;
1215    }
1216
1217    // Uncomment this if you want to see all available instructions.
1218    // @todo This doesn't actually work anymore, we should fix it.
1219//    printAvailableInsts();
1220
1221    // Execute/writeback any instructions that are available.
1222    int insts_to_execute = fromIssue->size;
1223    int inst_num = 0;
1224    for (; inst_num < insts_to_execute;
1225          ++inst_num) {
1226
1227        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1228
1229        DynInstPtr inst = instQueue.getInstToExecute();
1230
1231        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1232                inst->pcState(), inst->threadNumber,inst->seqNum);
1233
1234        // Notify potential listeners that this instruction has started
1235        // executing
1236        ppExecute->notify(inst);
1237
1238        // Check if the instruction is squashed; if so then skip it
1239        if (inst->isSquashed()) {
1240            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1241                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1242                         inst->seqNum);
1243
1244            // Consider this instruction executed so that commit can go
1245            // ahead and retire the instruction.
1246            inst->setExecuted();
1247
1248            // Not sure if I should set this here or just let commit try to
1249            // commit any squashed instructions.  I like the latter a bit more.
1250            inst->setCanCommit();
1251
1252            ++iewExecSquashedInsts;
1253
1254            continue;
1255        }
1256
1257        Fault fault = NoFault;
1258
1259        // Execute instruction.
1260        // Note that if the instruction faults, it will be handled
1261        // at the commit stage.
1262        if (inst->isMemRef()) {
1263            DPRINTF(IEW, "Execute: Calculating address for memory "
1264                    "reference.\n");
1265
1266            // Tell the LDSTQ to execute this instruction (if it is a load).
1267            if (inst->isAtomic()) {
1268                // AMOs are treated like store requests
1269                fault = ldstQueue.executeStore(inst);
1270
1271                if (inst->isTranslationDelayed() &&
1272                    fault == NoFault) {
1273                    // A hw page table walk is currently going on; the
1274                    // instruction must be deferred.
1275                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1276                            "store.\n");
1277                    instQueue.deferMemInst(inst);
1278                    continue;
1279                }
1280            } else if (inst->isLoad()) {
1281                // Loads will mark themselves as executed, and their writeback
1282                // event adds the instruction to the queue to commit
1283                fault = ldstQueue.executeLoad(inst);
1284
1285                if (inst->isTranslationDelayed() &&
1286                    fault == NoFault) {
1287                    // A hw page table walk is currently going on; the
1288                    // instruction must be deferred.
1289                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1290                            "load.\n");
1291                    instQueue.deferMemInst(inst);
1292                    continue;
1293                }
1294
1295                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1296                    inst->fault = NoFault;
1297                }
1298            } else if (inst->isStore()) {
1299                fault = ldstQueue.executeStore(inst);
1300
1301                if (inst->isTranslationDelayed() &&
1302                    fault == NoFault) {
1303                    // A hw page table walk is currently going on; the
1304                    // instruction must be deferred.
1305                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1306                            "store.\n");
1307                    instQueue.deferMemInst(inst);
1308                    continue;
1309                }
1310
1311                // If the store had a fault then it may not have a mem req
1312                if (fault != NoFault || !inst->readPredicate() ||
1313                        !inst->isStoreConditional()) {
1314                    // If the instruction faulted, then we need to send it along
1315                    // to commit without the instruction completing.
1316                    // Send this instruction to commit, also make sure iew stage
1317                    // realizes there is activity.
1318                    inst->setExecuted();
1319                    instToCommit(inst);
1320                    activityThisCycle();
1321                }
1322
1323                // Store conditionals will mark themselves as
1324                // executed, and their writeback event will add the
1325                // instruction to the queue to commit.
1326            } else {
1327                panic("Unexpected memory type!\n");
1328            }
1329
1330        } else {
1331            // If the instruction has already faulted, then skip executing it.
1332            // Such case can happen when it faulted during ITLB translation.
1333            // If we execute the instruction (even if it's a nop) the fault
1334            // will be replaced and we will lose it.
1335            if (inst->getFault() == NoFault) {
1336                inst->execute();
1337                if (!inst->readPredicate())
1338                    inst->forwardOldRegs();
1339            }
1340
1341            inst->setExecuted();
1342
1343            instToCommit(inst);
1344        }
1345
1346        updateExeInstStats(inst);
1347
1348        // Check if branch prediction was correct, if not then we need
1349        // to tell commit to squash in flight instructions.  Only
1350        // handle this if there hasn't already been something that
1351        // redirects fetch in this group of instructions.
1352
1353        // This probably needs to prioritize the redirects if a different
1354        // scheduler is used.  Currently the scheduler schedules the oldest
1355        // instruction first, so the branch resolution order will be correct.
1356        ThreadID tid = inst->threadNumber;
1357
1358        if (!fetchRedirect[tid] ||
1359            !toCommit->squash[tid] ||
1360            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1361
1362            // Prevent testing for misprediction on load instructions,
1363            // that have not been executed.
1364            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1365
1366            if (inst->mispredicted() && !loadNotExecuted) {
1367                fetchRedirect[tid] = true;
1368
1369                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1370                DPRINTF(IEW, "Predicted target was PC: %s.\n",
1371                        inst->readPredTarg());
1372                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1373                        inst->pcState());
1374                // If incorrect, then signal the ROB that it must be squashed.
1375                squashDueToBranch(inst, tid);
1376
1377                ppMispredict->notify(inst);
1378
1379                if (inst->readPredTaken()) {
1380                    predictedTakenIncorrect++;
1381                } else {
1382                    predictedNotTakenIncorrect++;
1383                }
1384            } else if (ldstQueue.violation(tid)) {
1385                assert(inst->isMemRef());
1386                // If there was an ordering violation, then get the
1387                // DynInst that caused the violation.  Note that this
1388                // clears the violation signal.
1389                DynInstPtr violator;
1390                violator = ldstQueue.getMemDepViolator(tid);
1391
1392                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1393                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1394                        violator->pcState(), violator->seqNum,
1395                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1396
1397                fetchRedirect[tid] = true;
1398
1399                // Tell the instruction queue that a violation has occured.
1400                instQueue.violation(inst, violator);
1401
1402                // Squash.
1403                squashDueToMemOrder(violator, tid);
1404
1405                ++memOrderViolationEvents;
1406            }
1407        } else {
1408            // Reset any state associated with redirects that will not
1409            // be used.
1410            if (ldstQueue.violation(tid)) {
1411                assert(inst->isMemRef());
1412
1413                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1414
1415                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1416                        "%s, inst PC: %s.  Addr is: %#x.\n",
1417                        violator->pcState(), inst->pcState(),
1418                        inst->physEffAddr);
1419                DPRINTF(IEW, "Violation will not be handled because "
1420                        "already squashing\n");
1421
1422                ++memOrderViolationEvents;
1423            }
1424        }
1425    }
1426
1427    // Update and record activity if we processed any instructions.
1428    if (inst_num) {
1429        if (exeStatus == Idle) {
1430            exeStatus = Running;
1431        }
1432
1433        updatedQueues = true;
1434
1435        cpu->activityThisCycle();
1436    }
1437
1438    // Need to reset this in case a writeback event needs to write into the
1439    // iew queue.  That way the writeback event will write into the correct
1440    // spot in the queue.
1441    wbNumInst = 0;
1442
1443}
1444
1445template <class Impl>
1446void
1447DefaultIEW<Impl>::writebackInsts()
1448{
1449    // Loop through the head of the time buffer and wake any
1450    // dependents.  These instructions are about to write back.  Also
1451    // mark scoreboard that this instruction is finally complete.
1452    // Either have IEW have direct access to scoreboard, or have this
1453    // as part of backwards communication.
1454    for (int inst_num = 0; inst_num < wbWidth &&
1455             toCommit->insts[inst_num]; inst_num++) {
1456        DynInstPtr inst = toCommit->insts[inst_num];
1457        ThreadID tid = inst->threadNumber;
1458
1459        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1460                inst->seqNum, inst->pcState());
1461
1462        iewInstsToCommit[tid]++;
1463        // Notify potential listeners that execution is complete for this
1464        // instruction.
1465        ppToCommit->notify(inst);
1466
1467        // Some instructions will be sent to commit without having
1468        // executed because they need commit to handle them.
1469        // E.g. Strictly ordered loads have not actually executed when they
1470        // are first sent to commit.  Instead commit must tell the LSQ
1471        // when it's ready to execute the strictly ordered load.
1472        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1473            int dependents = instQueue.wakeDependents(inst);
1474
1475            for (int i = 0; i < inst->numDestRegs(); i++) {
1476                //mark as Ready
1477                DPRINTF(IEW,"Setting Destination Register %i (%s)\n",
1478                        inst->renamedDestRegIdx(i)->index(),
1479                        inst->renamedDestRegIdx(i)->className());
1480                scoreboard->setReg(inst->renamedDestRegIdx(i));
1481            }
1482
1483            if (dependents) {
1484                producerInst[tid]++;
1485                consumerInst[tid]+= dependents;
1486            }
1487            writebackCount[tid]++;
1488        }
1489    }
1490}
1491
1492template<class Impl>
1493void
1494DefaultIEW<Impl>::tick()
1495{
1496    wbNumInst = 0;
1497    wbCycle = 0;
1498
1499    wroteToTimeBuffer = false;
1500    updatedQueues = false;
1501
1502    ldstQueue.tick();
1503
1504    sortInsts();
1505
1506    // Free function units marked as being freed this cycle.
1507    fuPool->processFreeUnits();
1508
1509    list<ThreadID>::iterator threads = activeThreads->begin();
1510    list<ThreadID>::iterator end = activeThreads->end();
1511
1512    // Check stall and squash signals, dispatch any instructions.
1513    while (threads != end) {
1514        ThreadID tid = *threads++;
1515
1516        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1517
1518        checkSignalsAndUpdate(tid);
1519        dispatch(tid);
1520    }
1521
1522    if (exeStatus != Squashing) {
1523        executeInsts();
1524
1525        writebackInsts();
1526
1527        // Have the instruction queue try to schedule any ready instructions.
1528        // (In actuality, this scheduling is for instructions that will
1529        // be executed next cycle.)
1530        instQueue.scheduleReadyInsts();
1531
1532        // Also should advance its own time buffers if the stage ran.
1533        // Not the best place for it, but this works (hopefully).
1534        issueToExecQueue.advance();
1535    }
1536
1537    bool broadcast_free_entries = false;
1538
1539    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1540        exeStatus = Idle;
1541        updateLSQNextCycle = false;
1542
1543        broadcast_free_entries = true;
1544    }
1545
1546    // Writeback any stores using any leftover bandwidth.
1547    ldstQueue.writebackStores();
1548
1549    // Check the committed load/store signals to see if there's a load
1550    // or store to commit.  Also check if it's being told to execute a
1551    // nonspeculative instruction.
1552    // This is pretty inefficient...
1553
1554    threads = activeThreads->begin();
1555    while (threads != end) {
1556        ThreadID tid = (*threads++);
1557
1558        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1559
1560        // Update structures based on instructions committed.
1561        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1562            !fromCommit->commitInfo[tid].squash &&
1563            !fromCommit->commitInfo[tid].robSquashing) {
1564
1565            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1566
1567            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1568
1569            updateLSQNextCycle = true;
1570            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1571        }
1572
1573        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1574
1575            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1576            if (fromCommit->commitInfo[tid].strictlyOrdered) {
1577                instQueue.replayMemInst(
1578                    fromCommit->commitInfo[tid].strictlyOrderedLoad);
1579                fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1580            } else {
1581                instQueue.scheduleNonSpec(
1582                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1583            }
1584        }
1585
1586        if (broadcast_free_entries) {
1587            toFetch->iewInfo[tid].iqCount =
1588                instQueue.getCount(tid);
1589            toFetch->iewInfo[tid].ldstqCount =
1590                ldstQueue.getCount(tid);
1591
1592            toRename->iewInfo[tid].usedIQ = true;
1593            toRename->iewInfo[tid].freeIQEntries =
1594                instQueue.numFreeEntries(tid);
1595            toRename->iewInfo[tid].usedLSQ = true;
1596
1597            toRename->iewInfo[tid].freeLQEntries =
1598                ldstQueue.numFreeLoadEntries(tid);
1599            toRename->iewInfo[tid].freeSQEntries =
1600                ldstQueue.numFreeStoreEntries(tid);
1601
1602            wroteToTimeBuffer = true;
1603        }
1604
1605        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1606                tid, toRename->iewInfo[tid].dispatched);
1607    }
1608
1609    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1610            "LQ has %i free entries. SQ has %i free entries.\n",
1611            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1612            ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries());
1613
1614    updateStatus();
1615
1616    if (wroteToTimeBuffer) {
1617        DPRINTF(Activity, "Activity this cycle.\n");
1618        cpu->activityThisCycle();
1619    }
1620}
1621
1622template <class Impl>
1623void
1624DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1625{
1626    ThreadID tid = inst->threadNumber;
1627
1628    iewExecutedInsts++;
1629
1630#if TRACING_ON
1631    if (DTRACE(O3PipeView)) {
1632        inst->completeTick = curTick() - inst->fetchTick;
1633    }
1634#endif
1635
1636    //
1637    //  Control operations
1638    //
1639    if (inst->isControl())
1640        iewExecutedBranches[tid]++;
1641
1642    //
1643    //  Memory operations
1644    //
1645    if (inst->isMemRef()) {
1646        iewExecutedRefs[tid]++;
1647
1648        if (inst->isLoad()) {
1649            iewExecLoadInsts[tid]++;
1650        }
1651    }
1652}
1653
1654template <class Impl>
1655void
1656DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1657{
1658    ThreadID tid = inst->threadNumber;
1659
1660    if (!fetchRedirect[tid] ||
1661        !toCommit->squash[tid] ||
1662        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1663
1664        if (inst->mispredicted()) {
1665            fetchRedirect[tid] = true;
1666
1667            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1668            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1669                    inst->predInstAddr(), inst->predNextInstAddr());
1670            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1671                    " NPC: %#x.\n", inst->nextInstAddr(),
1672                    inst->nextInstAddr());
1673            // If incorrect, then signal the ROB that it must be squashed.
1674            squashDueToBranch(inst, tid);
1675
1676            if (inst->readPredTaken()) {
1677                predictedTakenIncorrect++;
1678            } else {
1679                predictedNotTakenIncorrect++;
1680            }
1681        }
1682    }
1683}
1684
1685#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
1686