iew_impl.hh revision 13453:4a7a060ea26e
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37733SAli.Saidi@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47733SAli.Saidi@ARM.com * All rights reserved. 57733SAli.Saidi@ARM.com * 67733SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77733SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87733SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97733SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107733SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117733SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127733SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137733SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 142391SN/A * 152391SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162391SN/A * All rights reserved. 172391SN/A * 182391SN/A * Redistribution and use in source and binary forms, with or without 192391SN/A * modification, are permitted provided that the following conditions are 202391SN/A * met: redistributions of source code must retain the above copyright 212391SN/A * notice, this list of conditions and the following disclaimer; 222391SN/A * redistributions in binary form must reproduce the above copyright 232391SN/A * notice, this list of conditions and the following disclaimer in the 242391SN/A * documentation and/or other materials provided with the distribution; 252391SN/A * neither the name of the copyright holders nor the names of its 262391SN/A * contributors may be used to endorse or promote products derived from 272391SN/A * this software without specific prior written permission. 282391SN/A * 292391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362665Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378931Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409293Sandreas.hansson@arm.com * 419293Sandreas.hansson@arm.com * Authors: Kevin Lim 429293Sandreas.hansson@arm.com */ 439293Sandreas.hansson@arm.com 449293Sandreas.hansson@arm.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459293Sandreas.hansson@arm.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469293Sandreas.hansson@arm.com 479293Sandreas.hansson@arm.com// @todo: Fix the instantaneous communication among all the stages within 489293Sandreas.hansson@arm.com// iew. There's a clear delay between issue and execute, yet backwards 499293Sandreas.hansson@arm.com// communication happens simultaneously. 509293Sandreas.hansson@arm.com 519293Sandreas.hansson@arm.com#include <queue> 529293Sandreas.hansson@arm.com 539356Snilay@cs.wisc.edu#include "arch/utility.hh" 548931Sandreas.hansson@arm.com#include "config/the_isa.hh" 559293Sandreas.hansson@arm.com#include "cpu/checker/cpu.hh" 569293Sandreas.hansson@arm.com#include "cpu/o3/fu_pool.hh" 572394SN/A#include "cpu/o3/iew.hh" 582394SN/A#include "cpu/timebuf.hh" 592391SN/A#include "debug/Activity.hh" 602391SN/A#include "debug/Drain.hh" 619293Sandreas.hansson@arm.com#include "debug/IEW.hh" 629293Sandreas.hansson@arm.com#include "debug/O3PipeView.hh" 639293Sandreas.hansson@arm.com#include "params/DerivO3CPU.hh" 642391SN/A 659293Sandreas.hansson@arm.comusing namespace std; 669293Sandreas.hansson@arm.com 678931Sandreas.hansson@arm.comtemplate<class Impl> 688931Sandreas.hansson@arm.comDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 698931Sandreas.hansson@arm.com : issueToExecQueue(params->backComSize, params->forwardComSize), 708931Sandreas.hansson@arm.com cpu(_cpu), 718931Sandreas.hansson@arm.com instQueue(_cpu, this, params), 722391SN/A ldstQueue(_cpu, this, params), 738931Sandreas.hansson@arm.com fuPool(params->fuPool), 748931Sandreas.hansson@arm.com commitToIEWDelay(params->commitToIEWDelay), 758931Sandreas.hansson@arm.com renameToIEWDelay(params->renameToIEWDelay), 768931Sandreas.hansson@arm.com issueToExecuteDelay(params->issueToExecuteDelay), 778931Sandreas.hansson@arm.com dispatchWidth(params->dispatchWidth), 788931Sandreas.hansson@arm.com issueWidth(params->issueWidth), 798931Sandreas.hansson@arm.com wbNumInst(0), 808931Sandreas.hansson@arm.com wbCycle(0), 819293Sandreas.hansson@arm.com wbWidth(params->wbWidth), 829293Sandreas.hansson@arm.com numThreads(params->numThreads) 839293Sandreas.hansson@arm.com{ 849293Sandreas.hansson@arm.com if (dispatchWidth > Impl::MaxWidth) 859293Sandreas.hansson@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 869293Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 879293Sandreas.hansson@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 889293Sandreas.hansson@arm.com if (issueWidth > Impl::MaxWidth) 899293Sandreas.hansson@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 909293Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 919293Sandreas.hansson@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 929293Sandreas.hansson@arm.com if (wbWidth > Impl::MaxWidth) 939293Sandreas.hansson@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 949293Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 958931Sandreas.hansson@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 969293Sandreas.hansson@arm.com 979293Sandreas.hansson@arm.com _status = Active; 9810070Sandreas.hansson@arm.com exeStatus = Running; 9910070Sandreas.hansson@arm.com wbStatus = Idle; 10010070Sandreas.hansson@arm.com 1019565Sandreas.hansson@arm.com // Setup wire to read instructions coming from issue. 1029293Sandreas.hansson@arm.com fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1039293Sandreas.hansson@arm.com 1049293Sandreas.hansson@arm.com // Instruction queue needs the queue between issue and execute. 1059293Sandreas.hansson@arm.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1069293Sandreas.hansson@arm.com 1079293Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1089565Sandreas.hansson@arm.com dispatchStatus[tid] = Running; 1099565Sandreas.hansson@arm.com fetchRedirect[tid] = false; 1109565Sandreas.hansson@arm.com } 1119565Sandreas.hansson@arm.com 1129565Sandreas.hansson@arm.com updateLSQNextCycle = false; 1139565Sandreas.hansson@arm.com 1149565Sandreas.hansson@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1159565Sandreas.hansson@arm.com} 1169565Sandreas.hansson@arm.com 1179565Sandreas.hansson@arm.comtemplate <class Impl> 1189565Sandreas.hansson@arm.comstd::string 1199565Sandreas.hansson@arm.comDefaultIEW<Impl>::name() const 1209565Sandreas.hansson@arm.com{ 1219565Sandreas.hansson@arm.com return cpu->name() + ".iew"; 1229565Sandreas.hansson@arm.com} 1239565Sandreas.hansson@arm.com 1249565Sandreas.hansson@arm.comtemplate <class Impl> 1259565Sandreas.hansson@arm.comvoid 1269565Sandreas.hansson@arm.comDefaultIEW<Impl>::regProbePoints() 1279293Sandreas.hansson@arm.com{ 1289293Sandreas.hansson@arm.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1299565Sandreas.hansson@arm.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1309565Sandreas.hansson@arm.com /** 1319565Sandreas.hansson@arm.com * Probe point with dynamic instruction as the argument used to probe when 1329565Sandreas.hansson@arm.com * an instruction starts to execute. 1339565Sandreas.hansson@arm.com */ 1349565Sandreas.hansson@arm.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1359565Sandreas.hansson@arm.com "Execute"); 1369293Sandreas.hansson@arm.com /** 1379293Sandreas.hansson@arm.com * Probe point with dynamic instruction as the argument used to probe when 1389293Sandreas.hansson@arm.com * an instruction execution completes and it is marked ready to commit. 1399293Sandreas.hansson@arm.com */ 1409293Sandreas.hansson@arm.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1419293Sandreas.hansson@arm.com "ToCommit"); 1429411Sandreas.hansson@arm.com} 1439411Sandreas.hansson@arm.com 1449411Sandreas.hansson@arm.comtemplate <class Impl> 1459411Sandreas.hansson@arm.comvoid 1469293Sandreas.hansson@arm.comDefaultIEW<Impl>::regStats() 1479411Sandreas.hansson@arm.com{ 1489411Sandreas.hansson@arm.com using namespace Stats; 1499293Sandreas.hansson@arm.com 1509293Sandreas.hansson@arm.com instQueue.regStats(); 1519293Sandreas.hansson@arm.com ldstQueue.regStats(); 1529293Sandreas.hansson@arm.com 1539293Sandreas.hansson@arm.com iewIdleCycles 1549293Sandreas.hansson@arm.com .name(name() + ".iewIdleCycles") 1559293Sandreas.hansson@arm.com .desc("Number of cycles IEW is idle"); 1569405Sandreas.hansson@arm.com 1579405Sandreas.hansson@arm.com iewSquashCycles 1589293Sandreas.hansson@arm.com .name(name() + ".iewSquashCycles") 1599293Sandreas.hansson@arm.com .desc("Number of cycles IEW is squashing"); 1609293Sandreas.hansson@arm.com 1619293Sandreas.hansson@arm.com iewBlockCycles 1629293Sandreas.hansson@arm.com .name(name() + ".iewBlockCycles") 1639293Sandreas.hansson@arm.com .desc("Number of cycles IEW is blocking"); 16410070Sandreas.hansson@arm.com 1659293Sandreas.hansson@arm.com iewUnblockCycles 1669293Sandreas.hansson@arm.com .name(name() + ".iewUnblockCycles") 1679293Sandreas.hansson@arm.com .desc("Number of cycles IEW is unblocking"); 1688931Sandreas.hansson@arm.com 1699293Sandreas.hansson@arm.com iewDispatchedInsts 1708931Sandreas.hansson@arm.com .name(name() + ".iewDispatchedInsts") 1718931Sandreas.hansson@arm.com .desc("Number of instructions dispatched to IQ"); 1728931Sandreas.hansson@arm.com 1739293Sandreas.hansson@arm.com iewDispSquashedInsts 1749293Sandreas.hansson@arm.com .name(name() + ".iewDispSquashedInsts") 1759293Sandreas.hansson@arm.com .desc("Number of squashed instructions skipped by dispatch"); 1769293Sandreas.hansson@arm.com 1779293Sandreas.hansson@arm.com iewDispLoadInsts 1789293Sandreas.hansson@arm.com .name(name() + ".iewDispLoadInsts") 1799293Sandreas.hansson@arm.com .desc("Number of dispatched load instructions"); 1809293Sandreas.hansson@arm.com 1818931Sandreas.hansson@arm.com iewDispStoreInsts 1828931Sandreas.hansson@arm.com .name(name() + ".iewDispStoreInsts") 1838931Sandreas.hansson@arm.com .desc("Number of dispatched store instructions"); 1848931Sandreas.hansson@arm.com 1859405Sandreas.hansson@arm.com iewDispNonSpecInsts 1868931Sandreas.hansson@arm.com .name(name() + ".iewDispNonSpecInsts") 1879235Sandreas.hansson@arm.com .desc("Number of dispatched non-speculative instructions"); 1888931Sandreas.hansson@arm.com 1898931Sandreas.hansson@arm.com iewIQFullEvents 1908931Sandreas.hansson@arm.com .name(name() + ".iewIQFullEvents") 1918931Sandreas.hansson@arm.com .desc("Number of times the IQ has become full, causing a stall"); 1928931Sandreas.hansson@arm.com 1938931Sandreas.hansson@arm.com iewLSQFullEvents 1948851Sandreas.hansson@arm.com .name(name() + ".iewLSQFullEvents") 1958851Sandreas.hansson@arm.com .desc("Number of times the LSQ has become full, causing a stall"); 1968931Sandreas.hansson@arm.com 1975477Snate@binkert.org memOrderViolationEvents 1988931Sandreas.hansson@arm.com .name(name() + ".memOrderViolationEvents") 1998931Sandreas.hansson@arm.com .desc("Number of memory order violations"); 2008931Sandreas.hansson@arm.com 2017730SAli.Saidi@ARM.com predictedTakenIncorrect 2028931Sandreas.hansson@arm.com .name(name() + ".predictedTakenIncorrect") 2038931Sandreas.hansson@arm.com .desc("Number of branches that were predicted taken incorrectly"); 2048931Sandreas.hansson@arm.com 2058931Sandreas.hansson@arm.com predictedNotTakenIncorrect 2068931Sandreas.hansson@arm.com .name(name() + ".predictedNotTakenIncorrect") 2078931Sandreas.hansson@arm.com .desc("Number of branches that were predicted not taken incorrectly"); 2089413Sandreas.hansson@arm.com 2099413Sandreas.hansson@arm.com branchMispredicts 2109413Sandreas.hansson@arm.com .name(name() + ".branchMispredicts") 2119413Sandreas.hansson@arm.com .desc("Number of branch mispredicts detected at execute"); 2129413Sandreas.hansson@arm.com 2139413Sandreas.hansson@arm.com branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2149413Sandreas.hansson@arm.com 2159413Sandreas.hansson@arm.com iewExecutedInsts 2169413Sandreas.hansson@arm.com .name(name() + ".iewExecutedInsts") 2179413Sandreas.hansson@arm.com .desc("Number of executed instructions"); 2189413Sandreas.hansson@arm.com 2199413Sandreas.hansson@arm.com iewExecLoadInsts 2209413Sandreas.hansson@arm.com .init(cpu->numThreads) 2219413Sandreas.hansson@arm.com .name(name() + ".iewExecLoadInsts") 2229413Sandreas.hansson@arm.com .desc("Number of load instructions executed") 2239413Sandreas.hansson@arm.com .flags(total); 2249413Sandreas.hansson@arm.com 2259413Sandreas.hansson@arm.com iewExecSquashedInsts 2269413Sandreas.hansson@arm.com .name(name() + ".iewExecSquashedInsts") 2278931Sandreas.hansson@arm.com .desc("Number of squashed instructions skipped in execute"); 2287730SAli.Saidi@ARM.com 2292391SN/A iewExecutedSwp 2309413Sandreas.hansson@arm.com .init(cpu->numThreads) 2319413Sandreas.hansson@arm.com .name(name() + ".exec_swp") 2329413Sandreas.hansson@arm.com .desc("number of swp insts executed") 2339413Sandreas.hansson@arm.com .flags(total); 2349413Sandreas.hansson@arm.com 2359413Sandreas.hansson@arm.com iewExecutedNop 2368931Sandreas.hansson@arm.com .init(cpu->numThreads) 2372391SN/A .name(name() + ".exec_nop") 2382391SN/A .desc("number of nop insts executed") 2392541SN/A .flags(total); 2408931Sandreas.hansson@arm.com 2412541SN/A iewExecutedRefs 2428931Sandreas.hansson@arm.com .init(cpu->numThreads) 2438931Sandreas.hansson@arm.com .name(name() + ".exec_refs") 2449235Sandreas.hansson@arm.com .desc("number of memory reference insts executed") 2458931Sandreas.hansson@arm.com .flags(total); 2468931Sandreas.hansson@arm.com 2472391SN/A iewExecutedBranches 2482391SN/A .init(cpu->numThreads) 2498719SAli.Saidi@ARM.com .name(name() + ".exec_branches") 2508931Sandreas.hansson@arm.com .desc("Number of branches executed") 2518719SAli.Saidi@ARM.com .flags(total); 2528931Sandreas.hansson@arm.com 2538931Sandreas.hansson@arm.com iewExecStoreInsts 2549235Sandreas.hansson@arm.com .name(name() + ".exec_stores") 2558931Sandreas.hansson@arm.com .desc("Number of stores executed") 2568931Sandreas.hansson@arm.com .flags(total); 2578719SAli.Saidi@ARM.com iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2589293Sandreas.hansson@arm.com 2599293Sandreas.hansson@arm.com iewExecRate 2609293Sandreas.hansson@arm.com .name(name() + ".exec_rate") 2619293Sandreas.hansson@arm.com .desc("Inst execution rate") 2629293Sandreas.hansson@arm.com .flags(total); 2639293Sandreas.hansson@arm.com 2649293Sandreas.hansson@arm.com iewExecRate = iewExecutedInsts / cpu->numCycles; 2659293Sandreas.hansson@arm.com 2669293Sandreas.hansson@arm.com iewInstsToCommit 2679293Sandreas.hansson@arm.com .init(cpu->numThreads) 2689293Sandreas.hansson@arm.com .name(name() + ".wb_sent") 2699293Sandreas.hansson@arm.com .desc("cumulative count of insts sent to commit") 2709293Sandreas.hansson@arm.com .flags(total); 2719293Sandreas.hansson@arm.com 2729293Sandreas.hansson@arm.com writebackCount 2739293Sandreas.hansson@arm.com .init(cpu->numThreads) 2749293Sandreas.hansson@arm.com .name(name() + ".wb_count") 2759293Sandreas.hansson@arm.com .desc("cumulative count of insts written-back") 2769293Sandreas.hansson@arm.com .flags(total); 2779293Sandreas.hansson@arm.com 2789293Sandreas.hansson@arm.com producerInst 2799293Sandreas.hansson@arm.com .init(cpu->numThreads) 2809293Sandreas.hansson@arm.com .name(name() + ".wb_producers") 2819293Sandreas.hansson@arm.com .desc("num instructions producing a value") 2829293Sandreas.hansson@arm.com .flags(total); 2839293Sandreas.hansson@arm.com 2849293Sandreas.hansson@arm.com consumerInst 2859293Sandreas.hansson@arm.com .init(cpu->numThreads) 2869293Sandreas.hansson@arm.com .name(name() + ".wb_consumers") 2879293Sandreas.hansson@arm.com .desc("num instructions consuming a value") 2889293Sandreas.hansson@arm.com .flags(total); 2899293Sandreas.hansson@arm.com 2909293Sandreas.hansson@arm.com wbFanout 2919293Sandreas.hansson@arm.com .name(name() + ".wb_fanout") 2929293Sandreas.hansson@arm.com .desc("average fanout of values written-back") 2939293Sandreas.hansson@arm.com .flags(total); 2949293Sandreas.hansson@arm.com 2959293Sandreas.hansson@arm.com wbFanout = producerInst / consumerInst; 2969293Sandreas.hansson@arm.com 2979293Sandreas.hansson@arm.com wbRate 2989386Sandreas.hansson@arm.com .name(name() + ".wb_rate") 2999293Sandreas.hansson@arm.com .desc("insts written-back per cycle") 3009293Sandreas.hansson@arm.com .flags(total); 3019293Sandreas.hansson@arm.com wbRate = writebackCount / cpu->numCycles; 3029293Sandreas.hansson@arm.com} 3039293Sandreas.hansson@arm.com 3049293Sandreas.hansson@arm.comtemplate<class Impl> 3059293Sandreas.hansson@arm.comvoid 3069293Sandreas.hansson@arm.comDefaultIEW<Impl>::startupStage() 3079293Sandreas.hansson@arm.com{ 3089293Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3099293Sandreas.hansson@arm.com toRename->iewInfo[tid].usedIQ = true; 3109293Sandreas.hansson@arm.com toRename->iewInfo[tid].freeIQEntries = 3119293Sandreas.hansson@arm.com instQueue.numFreeEntries(tid); 3129293Sandreas.hansson@arm.com 3139293Sandreas.hansson@arm.com toRename->iewInfo[tid].usedLSQ = true; 3149293Sandreas.hansson@arm.com toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3159293Sandreas.hansson@arm.com toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3169293Sandreas.hansson@arm.com } 3179293Sandreas.hansson@arm.com 3189293Sandreas.hansson@arm.com // Initialize the checker's dcache port here 3199293Sandreas.hansson@arm.com if (cpu->checker) { 3209293Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3219293Sandreas.hansson@arm.com } 3229293Sandreas.hansson@arm.com 3239293Sandreas.hansson@arm.com cpu->activateStage(O3CPU::IEWIdx); 3249293Sandreas.hansson@arm.com} 3259293Sandreas.hansson@arm.com 3269293Sandreas.hansson@arm.comtemplate<class Impl> 3279293Sandreas.hansson@arm.comvoid 3289293Sandreas.hansson@arm.comDefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3299293Sandreas.hansson@arm.com{ 3309293Sandreas.hansson@arm.com timeBuffer = tb_ptr; 3319293Sandreas.hansson@arm.com 3329293Sandreas.hansson@arm.com // Setup wire to read information from time buffer, from commit. 3339293Sandreas.hansson@arm.com fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3349293Sandreas.hansson@arm.com 3359293Sandreas.hansson@arm.com // Setup wire to write information back to previous stages. 3369293Sandreas.hansson@arm.com toRename = timeBuffer->getWire(0); 3379293Sandreas.hansson@arm.com 3389293Sandreas.hansson@arm.com toFetch = timeBuffer->getWire(0); 3399293Sandreas.hansson@arm.com 3409293Sandreas.hansson@arm.com // Instruction queue also needs main time buffer. 3419293Sandreas.hansson@arm.com instQueue.setTimeBuffer(tb_ptr); 3429293Sandreas.hansson@arm.com} 3439293Sandreas.hansson@arm.com 3449293Sandreas.hansson@arm.comtemplate<class Impl> 3459293Sandreas.hansson@arm.comvoid 3469293Sandreas.hansson@arm.comDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3479293Sandreas.hansson@arm.com{ 3489293Sandreas.hansson@arm.com renameQueue = rq_ptr; 3499293Sandreas.hansson@arm.com 3509293Sandreas.hansson@arm.com // Setup wire to read information from rename queue. 3519293Sandreas.hansson@arm.com fromRename = renameQueue->getWire(-renameToIEWDelay); 3529293Sandreas.hansson@arm.com} 3539293Sandreas.hansson@arm.com 3549293Sandreas.hansson@arm.comtemplate<class Impl> 3559409Sandreas.hansson@arm.comvoid 3569409Sandreas.hansson@arm.comDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3579293Sandreas.hansson@arm.com{ 3589293Sandreas.hansson@arm.com iewQueue = iq_ptr; 3599293Sandreas.hansson@arm.com 3609293Sandreas.hansson@arm.com // Setup wire to write instructions to commit. 3619293Sandreas.hansson@arm.com toCommit = iewQueue->getWire(0); 3629293Sandreas.hansson@arm.com} 3639293Sandreas.hansson@arm.com 3649293Sandreas.hansson@arm.comtemplate<class Impl> 3659293Sandreas.hansson@arm.comvoid 3669293Sandreas.hansson@arm.comDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3679293Sandreas.hansson@arm.com{ 3689293Sandreas.hansson@arm.com activeThreads = at_ptr; 3699293Sandreas.hansson@arm.com 3709293Sandreas.hansson@arm.com ldstQueue.setActiveThreads(at_ptr); 3719293Sandreas.hansson@arm.com instQueue.setActiveThreads(at_ptr); 3729293Sandreas.hansson@arm.com} 3739293Sandreas.hansson@arm.com 3749293Sandreas.hansson@arm.comtemplate<class Impl> 3759293Sandreas.hansson@arm.comvoid 3769293Sandreas.hansson@arm.comDefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3779293Sandreas.hansson@arm.com{ 3789293Sandreas.hansson@arm.com scoreboard = sb_ptr; 3799293Sandreas.hansson@arm.com} 3809293Sandreas.hansson@arm.com 3819293Sandreas.hansson@arm.comtemplate <class Impl> 3829293Sandreas.hansson@arm.combool 3839293Sandreas.hansson@arm.comDefaultIEW<Impl>::isDrained() const 3849293Sandreas.hansson@arm.com{ 3859293Sandreas.hansson@arm.com bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3869293Sandreas.hansson@arm.com 3879293Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3889293Sandreas.hansson@arm.com if (!insts[tid].empty()) { 3899293Sandreas.hansson@arm.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3909293Sandreas.hansson@arm.com drained = false; 3919293Sandreas.hansson@arm.com } 3929293Sandreas.hansson@arm.com if (!skidBuffer[tid].empty()) { 3939293Sandreas.hansson@arm.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 39410070Sandreas.hansson@arm.com drained = false; 3959293Sandreas.hansson@arm.com } 3969293Sandreas.hansson@arm.com drained = drained && dispatchStatus[tid] == Running; 3979293Sandreas.hansson@arm.com } 3989293Sandreas.hansson@arm.com 3999293Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4009293Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4019293Sandreas.hansson@arm.com // above 4029293Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4039293Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4049293Sandreas.hansson@arm.com drained = false; 4059293Sandreas.hansson@arm.com } 4069293Sandreas.hansson@arm.com 4079293Sandreas.hansson@arm.com return drained; 4089293Sandreas.hansson@arm.com} 4099293Sandreas.hansson@arm.com 4109293Sandreas.hansson@arm.comtemplate <class Impl> 4119293Sandreas.hansson@arm.comvoid 4129293Sandreas.hansson@arm.comDefaultIEW<Impl>::drainSanityCheck() const 4139293Sandreas.hansson@arm.com{ 4149293Sandreas.hansson@arm.com assert(isDrained()); 4159293Sandreas.hansson@arm.com 4169293Sandreas.hansson@arm.com instQueue.drainSanityCheck(); 4179293Sandreas.hansson@arm.com ldstQueue.drainSanityCheck(); 4189293Sandreas.hansson@arm.com} 4199293Sandreas.hansson@arm.com 4209293Sandreas.hansson@arm.comtemplate <class Impl> 4219293Sandreas.hansson@arm.comvoid 4229293Sandreas.hansson@arm.comDefaultIEW<Impl>::takeOverFrom() 4239293Sandreas.hansson@arm.com{ 4249293Sandreas.hansson@arm.com // Reset all state. 4259293Sandreas.hansson@arm.com _status = Active; 4269293Sandreas.hansson@arm.com exeStatus = Running; 4279293Sandreas.hansson@arm.com wbStatus = Idle; 4289293Sandreas.hansson@arm.com 4299293Sandreas.hansson@arm.com instQueue.takeOverFrom(); 4309293Sandreas.hansson@arm.com ldstQueue.takeOverFrom(); 4319293Sandreas.hansson@arm.com fuPool->takeOverFrom(); 4329293Sandreas.hansson@arm.com 4339293Sandreas.hansson@arm.com startupStage(); 4349293Sandreas.hansson@arm.com cpu->activityThisCycle(); 4359293Sandreas.hansson@arm.com 436 for (ThreadID tid = 0; tid < numThreads; tid++) { 437 dispatchStatus[tid] = Running; 438 fetchRedirect[tid] = false; 439 } 440 441 updateLSQNextCycle = false; 442 443 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 444 issueToExecQueue.advance(); 445 } 446} 447 448template<class Impl> 449void 450DefaultIEW<Impl>::squash(ThreadID tid) 451{ 452 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 453 454 // Tell the IQ to start squashing. 455 instQueue.squash(tid); 456 457 // Tell the LDSTQ to start squashing. 458 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 459 updatedQueues = true; 460 461 // Clear the skid buffer in case it has any data in it. 462 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 463 tid, fromCommit->commitInfo[tid].doneSeqNum); 464 465 while (!skidBuffer[tid].empty()) { 466 if (skidBuffer[tid].front()->isLoad()) { 467 toRename->iewInfo[tid].dispatchedToLQ++; 468 } 469 if (skidBuffer[tid].front()->isStore()) { 470 toRename->iewInfo[tid].dispatchedToSQ++; 471 } 472 473 toRename->iewInfo[tid].dispatched++; 474 475 skidBuffer[tid].pop(); 476 } 477 478 emptyRenameInsts(tid); 479} 480 481template<class Impl> 482void 483DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 484{ 485 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 486 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 487 488 if (!toCommit->squash[tid] || 489 inst->seqNum < toCommit->squashedSeqNum[tid]) { 490 toCommit->squash[tid] = true; 491 toCommit->squashedSeqNum[tid] = inst->seqNum; 492 toCommit->branchTaken[tid] = inst->pcState().branching(); 493 494 TheISA::PCState pc = inst->pcState(); 495 TheISA::advancePC(pc, inst->staticInst); 496 497 toCommit->pc[tid] = pc; 498 toCommit->mispredictInst[tid] = inst; 499 toCommit->includeSquashInst[tid] = false; 500 501 wroteToTimeBuffer = true; 502 } 503 504} 505 506template<class Impl> 507void 508DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 509{ 510 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 511 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 512 // Need to include inst->seqNum in the following comparison to cover the 513 // corner case when a branch misprediction and a memory violation for the 514 // same instruction (e.g. load PC) are detected in the same cycle. In this 515 // case the memory violator should take precedence over the branch 516 // misprediction because it requires the violator itself to be included in 517 // the squash. 518 if (!toCommit->squash[tid] || 519 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 520 toCommit->squash[tid] = true; 521 522 toCommit->squashedSeqNum[tid] = inst->seqNum; 523 toCommit->pc[tid] = inst->pcState(); 524 toCommit->mispredictInst[tid] = NULL; 525 526 // Must include the memory violator in the squash. 527 toCommit->includeSquashInst[tid] = true; 528 529 wroteToTimeBuffer = true; 530 } 531} 532 533template<class Impl> 534void 535DefaultIEW<Impl>::block(ThreadID tid) 536{ 537 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 538 539 if (dispatchStatus[tid] != Blocked && 540 dispatchStatus[tid] != Unblocking) { 541 toRename->iewBlock[tid] = true; 542 wroteToTimeBuffer = true; 543 } 544 545 // Add the current inputs to the skid buffer so they can be 546 // reprocessed when this stage unblocks. 547 skidInsert(tid); 548 549 dispatchStatus[tid] = Blocked; 550} 551 552template<class Impl> 553void 554DefaultIEW<Impl>::unblock(ThreadID tid) 555{ 556 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 557 "buffer %u.\n",tid, tid); 558 559 // If the skid bufffer is empty, signal back to previous stages to unblock. 560 // Also switch status to running. 561 if (skidBuffer[tid].empty()) { 562 toRename->iewUnblock[tid] = true; 563 wroteToTimeBuffer = true; 564 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 565 dispatchStatus[tid] = Running; 566 } 567} 568 569template<class Impl> 570void 571DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 572{ 573 instQueue.wakeDependents(inst); 574} 575 576template<class Impl> 577void 578DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 579{ 580 instQueue.rescheduleMemInst(inst); 581} 582 583template<class Impl> 584void 585DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 586{ 587 instQueue.replayMemInst(inst); 588} 589 590template<class Impl> 591void 592DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 593{ 594 instQueue.blockMemInst(inst); 595} 596 597template<class Impl> 598void 599DefaultIEW<Impl>::cacheUnblocked() 600{ 601 instQueue.cacheUnblocked(); 602} 603 604template<class Impl> 605void 606DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 607{ 608 // This function should not be called after writebackInsts in a 609 // single cycle. That will cause problems with an instruction 610 // being added to the queue to commit without being processed by 611 // writebackInsts prior to being sent to commit. 612 613 // First check the time slot that this instruction will write 614 // to. If there are free write ports at the time, then go ahead 615 // and write the instruction to that time. If there are not, 616 // keep looking back to see where's the first time there's a 617 // free slot. 618 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 619 ++wbNumInst; 620 if (wbNumInst == wbWidth) { 621 ++wbCycle; 622 wbNumInst = 0; 623 } 624 } 625 626 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 627 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 628 // Add finished instruction to queue to commit. 629 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 630 (*iewQueue)[wbCycle].size++; 631} 632 633template <class Impl> 634unsigned 635DefaultIEW<Impl>::validInstsFromRename() 636{ 637 unsigned inst_count = 0; 638 639 for (int i=0; i<fromRename->size; i++) { 640 if (!fromRename->insts[i]->isSquashed()) 641 inst_count++; 642 } 643 644 return inst_count; 645} 646 647template<class Impl> 648void 649DefaultIEW<Impl>::skidInsert(ThreadID tid) 650{ 651 DynInstPtr inst = NULL; 652 653 while (!insts[tid].empty()) { 654 inst = insts[tid].front(); 655 656 insts[tid].pop(); 657 658 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 659 "dispatch skidBuffer %i\n",tid, inst->seqNum, 660 inst->pcState(),tid); 661 662 skidBuffer[tid].push(inst); 663 } 664 665 assert(skidBuffer[tid].size() <= skidBufferMax && 666 "Skidbuffer Exceeded Max Size"); 667} 668 669template<class Impl> 670int 671DefaultIEW<Impl>::skidCount() 672{ 673 int max=0; 674 675 list<ThreadID>::iterator threads = activeThreads->begin(); 676 list<ThreadID>::iterator end = activeThreads->end(); 677 678 while (threads != end) { 679 ThreadID tid = *threads++; 680 unsigned thread_count = skidBuffer[tid].size(); 681 if (max < thread_count) 682 max = thread_count; 683 } 684 685 return max; 686} 687 688template<class Impl> 689bool 690DefaultIEW<Impl>::skidsEmpty() 691{ 692 list<ThreadID>::iterator threads = activeThreads->begin(); 693 list<ThreadID>::iterator end = activeThreads->end(); 694 695 while (threads != end) { 696 ThreadID tid = *threads++; 697 698 if (!skidBuffer[tid].empty()) 699 return false; 700 } 701 702 return true; 703} 704 705template <class Impl> 706void 707DefaultIEW<Impl>::updateStatus() 708{ 709 bool any_unblocking = false; 710 711 list<ThreadID>::iterator threads = activeThreads->begin(); 712 list<ThreadID>::iterator end = activeThreads->end(); 713 714 while (threads != end) { 715 ThreadID tid = *threads++; 716 717 if (dispatchStatus[tid] == Unblocking) { 718 any_unblocking = true; 719 break; 720 } 721 } 722 723 // If there are no ready instructions waiting to be scheduled by the IQ, 724 // and there's no stores waiting to write back, and dispatch is not 725 // unblocking, then there is no internal activity for the IEW stage. 726 instQueue.intInstQueueReads++; 727 if (_status == Active && !instQueue.hasReadyInsts() && 728 !ldstQueue.willWB() && !any_unblocking) { 729 DPRINTF(IEW, "IEW switching to idle\n"); 730 731 deactivateStage(); 732 733 _status = Inactive; 734 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 735 ldstQueue.willWB() || 736 any_unblocking)) { 737 // Otherwise there is internal activity. Set to active. 738 DPRINTF(IEW, "IEW switching to active\n"); 739 740 activateStage(); 741 742 _status = Active; 743 } 744} 745 746template <class Impl> 747void 748DefaultIEW<Impl>::resetEntries() 749{ 750 instQueue.resetEntries(); 751 ldstQueue.resetEntries(); 752} 753 754template <class Impl> 755bool 756DefaultIEW<Impl>::checkStall(ThreadID tid) 757{ 758 bool ret_val(false); 759 760 if (fromCommit->commitInfo[tid].robSquashing) { 761 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 762 ret_val = true; 763 } else if (instQueue.isFull(tid)) { 764 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 765 ret_val = true; 766 } 767 768 return ret_val; 769} 770 771template <class Impl> 772void 773DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 774{ 775 // Check if there's a squash signal, squash if there is 776 // Check stall signals, block if there is. 777 // If status was Blocked 778 // if so then go to unblocking 779 // If status was Squashing 780 // check if squashing is not high. Switch to running this cycle. 781 782 if (fromCommit->commitInfo[tid].squash) { 783 squash(tid); 784 785 if (dispatchStatus[tid] == Blocked || 786 dispatchStatus[tid] == Unblocking) { 787 toRename->iewUnblock[tid] = true; 788 wroteToTimeBuffer = true; 789 } 790 791 dispatchStatus[tid] = Squashing; 792 fetchRedirect[tid] = false; 793 return; 794 } 795 796 if (fromCommit->commitInfo[tid].robSquashing) { 797 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 798 799 dispatchStatus[tid] = Squashing; 800 emptyRenameInsts(tid); 801 wroteToTimeBuffer = true; 802 } 803 804 if (checkStall(tid)) { 805 block(tid); 806 dispatchStatus[tid] = Blocked; 807 return; 808 } 809 810 if (dispatchStatus[tid] == Blocked) { 811 // Status from previous cycle was blocked, but there are no more stall 812 // conditions. Switch over to unblocking. 813 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 814 tid); 815 816 dispatchStatus[tid] = Unblocking; 817 818 unblock(tid); 819 820 return; 821 } 822 823 if (dispatchStatus[tid] == Squashing) { 824 // Switch status to running if rename isn't being told to block or 825 // squash this cycle. 826 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 827 tid); 828 829 dispatchStatus[tid] = Running; 830 831 return; 832 } 833} 834 835template <class Impl> 836void 837DefaultIEW<Impl>::sortInsts() 838{ 839 int insts_from_rename = fromRename->size; 840#ifdef DEBUG 841 for (ThreadID tid = 0; tid < numThreads; tid++) 842 assert(insts[tid].empty()); 843#endif 844 for (int i = 0; i < insts_from_rename; ++i) { 845 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 846 } 847} 848 849template <class Impl> 850void 851DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 852{ 853 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 854 855 while (!insts[tid].empty()) { 856 857 if (insts[tid].front()->isLoad()) { 858 toRename->iewInfo[tid].dispatchedToLQ++; 859 } 860 if (insts[tid].front()->isStore()) { 861 toRename->iewInfo[tid].dispatchedToSQ++; 862 } 863 864 toRename->iewInfo[tid].dispatched++; 865 866 insts[tid].pop(); 867 } 868} 869 870template <class Impl> 871void 872DefaultIEW<Impl>::wakeCPU() 873{ 874 cpu->wakeCPU(); 875} 876 877template <class Impl> 878void 879DefaultIEW<Impl>::activityThisCycle() 880{ 881 DPRINTF(Activity, "Activity this cycle.\n"); 882 cpu->activityThisCycle(); 883} 884 885template <class Impl> 886inline void 887DefaultIEW<Impl>::activateStage() 888{ 889 DPRINTF(Activity, "Activating stage.\n"); 890 cpu->activateStage(O3CPU::IEWIdx); 891} 892 893template <class Impl> 894inline void 895DefaultIEW<Impl>::deactivateStage() 896{ 897 DPRINTF(Activity, "Deactivating stage.\n"); 898 cpu->deactivateStage(O3CPU::IEWIdx); 899} 900 901template<class Impl> 902void 903DefaultIEW<Impl>::dispatch(ThreadID tid) 904{ 905 // If status is Running or idle, 906 // call dispatchInsts() 907 // If status is Unblocking, 908 // buffer any instructions coming from rename 909 // continue trying to empty skid buffer 910 // check if stall conditions have passed 911 912 if (dispatchStatus[tid] == Blocked) { 913 ++iewBlockCycles; 914 915 } else if (dispatchStatus[tid] == Squashing) { 916 ++iewSquashCycles; 917 } 918 919 // Dispatch should try to dispatch as many instructions as its bandwidth 920 // will allow, as long as it is not currently blocked. 921 if (dispatchStatus[tid] == Running || 922 dispatchStatus[tid] == Idle) { 923 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 924 "dispatch.\n", tid); 925 926 dispatchInsts(tid); 927 } else if (dispatchStatus[tid] == Unblocking) { 928 // Make sure that the skid buffer has something in it if the 929 // status is unblocking. 930 assert(!skidsEmpty()); 931 932 // If the status was unblocking, then instructions from the skid 933 // buffer were used. Remove those instructions and handle 934 // the rest of unblocking. 935 dispatchInsts(tid); 936 937 ++iewUnblockCycles; 938 939 if (validInstsFromRename()) { 940 // Add the current inputs to the skid buffer so they can be 941 // reprocessed when this stage unblocks. 942 skidInsert(tid); 943 } 944 945 unblock(tid); 946 } 947} 948 949template <class Impl> 950void 951DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 952{ 953 // Obtain instructions from skid buffer if unblocking, or queue from rename 954 // otherwise. 955 std::queue<DynInstPtr> &insts_to_dispatch = 956 dispatchStatus[tid] == Unblocking ? 957 skidBuffer[tid] : insts[tid]; 958 959 int insts_to_add = insts_to_dispatch.size(); 960 961 DynInstPtr inst; 962 bool add_to_iq = false; 963 int dis_num_inst = 0; 964 965 // Loop through the instructions, putting them in the instruction 966 // queue. 967 for ( ; dis_num_inst < insts_to_add && 968 dis_num_inst < dispatchWidth; 969 ++dis_num_inst) 970 { 971 inst = insts_to_dispatch.front(); 972 973 if (dispatchStatus[tid] == Unblocking) { 974 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 975 "buffer\n", tid); 976 } 977 978 // Make sure there's a valid instruction there. 979 assert(inst); 980 981 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 982 "IQ.\n", 983 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 984 985 // Be sure to mark these instructions as ready so that the 986 // commit stage can go ahead and execute them, and mark 987 // them as issued so the IQ doesn't reprocess them. 988 989 // Check for squashed instructions. 990 if (inst->isSquashed()) { 991 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 992 "not adding to IQ.\n", tid); 993 994 ++iewDispSquashedInsts; 995 996 insts_to_dispatch.pop(); 997 998 //Tell Rename That An Instruction has been processed 999 if (inst->isLoad()) { 1000 toRename->iewInfo[tid].dispatchedToLQ++; 1001 } 1002 if (inst->isStore()) { 1003 toRename->iewInfo[tid].dispatchedToSQ++; 1004 } 1005 1006 toRename->iewInfo[tid].dispatched++; 1007 1008 continue; 1009 } 1010 1011 // Check for full conditions. 1012 if (instQueue.isFull(tid)) { 1013 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1014 1015 // Call function to start blocking. 1016 block(tid); 1017 1018 // Set unblock to false. Special case where we are using 1019 // skidbuffer (unblocking) instructions but then we still 1020 // get full in the IQ. 1021 toRename->iewUnblock[tid] = false; 1022 1023 ++iewIQFullEvents; 1024 break; 1025 } 1026 1027 // Check LSQ if inst is LD/ST 1028 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1029 (inst->isStore() && ldstQueue.sqFull(tid))) { 1030 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1031 inst->isLoad() ? "LQ" : "SQ"); 1032 1033 // Call function to start blocking. 1034 block(tid); 1035 1036 // Set unblock to false. Special case where we are using 1037 // skidbuffer (unblocking) instructions but then we still 1038 // get full in the IQ. 1039 toRename->iewUnblock[tid] = false; 1040 1041 ++iewLSQFullEvents; 1042 break; 1043 } 1044 1045 // Otherwise issue the instruction just fine. 1046 if (inst->isLoad()) { 1047 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1048 "encountered, adding to LSQ.\n", tid); 1049 1050 // Reserve a spot in the load store queue for this 1051 // memory access. 1052 ldstQueue.insertLoad(inst); 1053 1054 ++iewDispLoadInsts; 1055 1056 add_to_iq = true; 1057 1058 toRename->iewInfo[tid].dispatchedToLQ++; 1059 } else if (inst->isStore()) { 1060 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1061 "encountered, adding to LSQ.\n", tid); 1062 1063 ldstQueue.insertStore(inst); 1064 1065 ++iewDispStoreInsts; 1066 1067 if (inst->isStoreConditional()) { 1068 // Store conditionals need to be set as "canCommit()" 1069 // so that commit can process them when they reach the 1070 // head of commit. 1071 // @todo: This is somewhat specific to Alpha. 1072 inst->setCanCommit(); 1073 instQueue.insertNonSpec(inst); 1074 add_to_iq = false; 1075 1076 ++iewDispNonSpecInsts; 1077 } else { 1078 add_to_iq = true; 1079 } 1080 1081 toRename->iewInfo[tid].dispatchedToSQ++; 1082 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1083 // Same as non-speculative stores. 1084 inst->setCanCommit(); 1085 instQueue.insertBarrier(inst); 1086 add_to_iq = false; 1087 } else if (inst->isNop()) { 1088 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1089 "skipping.\n", tid); 1090 1091 inst->setIssued(); 1092 inst->setExecuted(); 1093 inst->setCanCommit(); 1094 1095 instQueue.recordProducer(inst); 1096 1097 iewExecutedNop[tid]++; 1098 1099 add_to_iq = false; 1100 } else { 1101 assert(!inst->isExecuted()); 1102 add_to_iq = true; 1103 } 1104 1105 if (add_to_iq && inst->isNonSpeculative()) { 1106 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1107 "encountered, skipping.\n", tid); 1108 1109 // Same as non-speculative stores. 1110 inst->setCanCommit(); 1111 1112 // Specifically insert it as nonspeculative. 1113 instQueue.insertNonSpec(inst); 1114 1115 ++iewDispNonSpecInsts; 1116 1117 add_to_iq = false; 1118 } 1119 1120 // If the instruction queue is not full, then add the 1121 // instruction. 1122 if (add_to_iq) { 1123 instQueue.insert(inst); 1124 } 1125 1126 insts_to_dispatch.pop(); 1127 1128 toRename->iewInfo[tid].dispatched++; 1129 1130 ++iewDispatchedInsts; 1131 1132#if TRACING_ON 1133 inst->dispatchTick = curTick() - inst->fetchTick; 1134#endif 1135 ppDispatch->notify(inst); 1136 } 1137 1138 if (!insts_to_dispatch.empty()) { 1139 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1140 block(tid); 1141 toRename->iewUnblock[tid] = false; 1142 } 1143 1144 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1145 dispatchStatus[tid] = Running; 1146 1147 updatedQueues = true; 1148 } 1149 1150 dis_num_inst = 0; 1151} 1152 1153template <class Impl> 1154void 1155DefaultIEW<Impl>::printAvailableInsts() 1156{ 1157 int inst = 0; 1158 1159 std::cout << "Available Instructions: "; 1160 1161 while (fromIssue->insts[inst]) { 1162 1163 if (inst%3==0) std::cout << "\n\t"; 1164 1165 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1166 << " TN: " << fromIssue->insts[inst]->threadNumber 1167 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1168 1169 inst++; 1170 1171 } 1172 1173 std::cout << "\n"; 1174} 1175 1176template <class Impl> 1177void 1178DefaultIEW<Impl>::executeInsts() 1179{ 1180 wbNumInst = 0; 1181 wbCycle = 0; 1182 1183 list<ThreadID>::iterator threads = activeThreads->begin(); 1184 list<ThreadID>::iterator end = activeThreads->end(); 1185 1186 while (threads != end) { 1187 ThreadID tid = *threads++; 1188 fetchRedirect[tid] = false; 1189 } 1190 1191 // Uncomment this if you want to see all available instructions. 1192 // @todo This doesn't actually work anymore, we should fix it. 1193// printAvailableInsts(); 1194 1195 // Execute/writeback any instructions that are available. 1196 int insts_to_execute = fromIssue->size; 1197 int inst_num = 0; 1198 for (; inst_num < insts_to_execute; 1199 ++inst_num) { 1200 1201 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1202 1203 DynInstPtr inst = instQueue.getInstToExecute(); 1204 1205 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1206 inst->pcState(), inst->threadNumber,inst->seqNum); 1207 1208 // Notify potential listeners that this instruction has started 1209 // executing 1210 ppExecute->notify(inst); 1211 1212 // Check if the instruction is squashed; if so then skip it 1213 if (inst->isSquashed()) { 1214 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1215 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1216 inst->seqNum); 1217 1218 // Consider this instruction executed so that commit can go 1219 // ahead and retire the instruction. 1220 inst->setExecuted(); 1221 1222 // Not sure if I should set this here or just let commit try to 1223 // commit any squashed instructions. I like the latter a bit more. 1224 inst->setCanCommit(); 1225 1226 ++iewExecSquashedInsts; 1227 1228 continue; 1229 } 1230 1231 Fault fault = NoFault; 1232 1233 // Execute instruction. 1234 // Note that if the instruction faults, it will be handled 1235 // at the commit stage. 1236 if (inst->isMemRef()) { 1237 DPRINTF(IEW, "Execute: Calculating address for memory " 1238 "reference.\n"); 1239 1240 // Tell the LDSTQ to execute this instruction (if it is a load). 1241 if (inst->isLoad()) { 1242 // Loads will mark themselves as executed, and their writeback 1243 // event adds the instruction to the queue to commit 1244 fault = ldstQueue.executeLoad(inst); 1245 1246 if (inst->isTranslationDelayed() && 1247 fault == NoFault) { 1248 // A hw page table walk is currently going on; the 1249 // instruction must be deferred. 1250 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1251 "load.\n"); 1252 instQueue.deferMemInst(inst); 1253 continue; 1254 } 1255 1256 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1257 inst->fault = NoFault; 1258 } 1259 } else if (inst->isStore()) { 1260 fault = ldstQueue.executeStore(inst); 1261 1262 if (inst->isTranslationDelayed() && 1263 fault == NoFault) { 1264 // A hw page table walk is currently going on; the 1265 // instruction must be deferred. 1266 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1267 "store.\n"); 1268 instQueue.deferMemInst(inst); 1269 continue; 1270 } 1271 1272 // If the store had a fault then it may not have a mem req 1273 if (fault != NoFault || !inst->readPredicate() || 1274 !inst->isStoreConditional()) { 1275 // If the instruction faulted, then we need to send it along 1276 // to commit without the instruction completing. 1277 // Send this instruction to commit, also make sure iew stage 1278 // realizes there is activity. 1279 inst->setExecuted(); 1280 instToCommit(inst); 1281 activityThisCycle(); 1282 } 1283 1284 // Store conditionals will mark themselves as 1285 // executed, and their writeback event will add the 1286 // instruction to the queue to commit. 1287 } else { 1288 panic("Unexpected memory type!\n"); 1289 } 1290 1291 } else { 1292 // If the instruction has already faulted, then skip executing it. 1293 // Such case can happen when it faulted during ITLB translation. 1294 // If we execute the instruction (even if it's a nop) the fault 1295 // will be replaced and we will lose it. 1296 if (inst->getFault() == NoFault) { 1297 inst->execute(); 1298 if (!inst->readPredicate()) 1299 inst->forwardOldRegs(); 1300 } 1301 1302 inst->setExecuted(); 1303 1304 instToCommit(inst); 1305 } 1306 1307 updateExeInstStats(inst); 1308 1309 // Check if branch prediction was correct, if not then we need 1310 // to tell commit to squash in flight instructions. Only 1311 // handle this if there hasn't already been something that 1312 // redirects fetch in this group of instructions. 1313 1314 // This probably needs to prioritize the redirects if a different 1315 // scheduler is used. Currently the scheduler schedules the oldest 1316 // instruction first, so the branch resolution order will be correct. 1317 ThreadID tid = inst->threadNumber; 1318 1319 if (!fetchRedirect[tid] || 1320 !toCommit->squash[tid] || 1321 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1322 1323 // Prevent testing for misprediction on load instructions, 1324 // that have not been executed. 1325 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1326 1327 if (inst->mispredicted() && !loadNotExecuted) { 1328 fetchRedirect[tid] = true; 1329 1330 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1331 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1332 inst->readPredTarg()); 1333 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1334 inst->pcState()); 1335 // If incorrect, then signal the ROB that it must be squashed. 1336 squashDueToBranch(inst, tid); 1337 1338 ppMispredict->notify(inst); 1339 1340 if (inst->readPredTaken()) { 1341 predictedTakenIncorrect++; 1342 } else { 1343 predictedNotTakenIncorrect++; 1344 } 1345 } else if (ldstQueue.violation(tid)) { 1346 assert(inst->isMemRef()); 1347 // If there was an ordering violation, then get the 1348 // DynInst that caused the violation. Note that this 1349 // clears the violation signal. 1350 DynInstPtr violator; 1351 violator = ldstQueue.getMemDepViolator(tid); 1352 1353 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1354 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1355 violator->pcState(), violator->seqNum, 1356 inst->pcState(), inst->seqNum, inst->physEffAddrLow); 1357 1358 fetchRedirect[tid] = true; 1359 1360 // Tell the instruction queue that a violation has occured. 1361 instQueue.violation(inst, violator); 1362 1363 // Squash. 1364 squashDueToMemOrder(violator, tid); 1365 1366 ++memOrderViolationEvents; 1367 } 1368 } else { 1369 // Reset any state associated with redirects that will not 1370 // be used. 1371 if (ldstQueue.violation(tid)) { 1372 assert(inst->isMemRef()); 1373 1374 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1375 1376 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1377 "%s, inst PC: %s. Addr is: %#x.\n", 1378 violator->pcState(), inst->pcState(), 1379 inst->physEffAddrLow); 1380 DPRINTF(IEW, "Violation will not be handled because " 1381 "already squashing\n"); 1382 1383 ++memOrderViolationEvents; 1384 } 1385 } 1386 } 1387 1388 // Update and record activity if we processed any instructions. 1389 if (inst_num) { 1390 if (exeStatus == Idle) { 1391 exeStatus = Running; 1392 } 1393 1394 updatedQueues = true; 1395 1396 cpu->activityThisCycle(); 1397 } 1398 1399 // Need to reset this in case a writeback event needs to write into the 1400 // iew queue. That way the writeback event will write into the correct 1401 // spot in the queue. 1402 wbNumInst = 0; 1403 1404} 1405 1406template <class Impl> 1407void 1408DefaultIEW<Impl>::writebackInsts() 1409{ 1410 // Loop through the head of the time buffer and wake any 1411 // dependents. These instructions are about to write back. Also 1412 // mark scoreboard that this instruction is finally complete. 1413 // Either have IEW have direct access to scoreboard, or have this 1414 // as part of backwards communication. 1415 for (int inst_num = 0; inst_num < wbWidth && 1416 toCommit->insts[inst_num]; inst_num++) { 1417 DynInstPtr inst = toCommit->insts[inst_num]; 1418 ThreadID tid = inst->threadNumber; 1419 1420 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1421 inst->seqNum, inst->pcState()); 1422 1423 iewInstsToCommit[tid]++; 1424 // Notify potential listeners that execution is complete for this 1425 // instruction. 1426 ppToCommit->notify(inst); 1427 1428 // Some instructions will be sent to commit without having 1429 // executed because they need commit to handle them. 1430 // E.g. Strictly ordered loads have not actually executed when they 1431 // are first sent to commit. Instead commit must tell the LSQ 1432 // when it's ready to execute the strictly ordered load. 1433 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1434 int dependents = instQueue.wakeDependents(inst); 1435 1436 for (int i = 0; i < inst->numDestRegs(); i++) { 1437 //mark as Ready 1438 DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 1439 inst->renamedDestRegIdx(i)->index(), 1440 inst->renamedDestRegIdx(i)->className()); 1441 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1442 } 1443 1444 if (dependents) { 1445 producerInst[tid]++; 1446 consumerInst[tid]+= dependents; 1447 } 1448 writebackCount[tid]++; 1449 } 1450 } 1451} 1452 1453template<class Impl> 1454void 1455DefaultIEW<Impl>::tick() 1456{ 1457 wbNumInst = 0; 1458 wbCycle = 0; 1459 1460 wroteToTimeBuffer = false; 1461 updatedQueues = false; 1462 1463 sortInsts(); 1464 1465 // Free function units marked as being freed this cycle. 1466 fuPool->processFreeUnits(); 1467 1468 list<ThreadID>::iterator threads = activeThreads->begin(); 1469 list<ThreadID>::iterator end = activeThreads->end(); 1470 1471 // Check stall and squash signals, dispatch any instructions. 1472 while (threads != end) { 1473 ThreadID tid = *threads++; 1474 1475 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1476 1477 checkSignalsAndUpdate(tid); 1478 dispatch(tid); 1479 } 1480 1481 if (exeStatus != Squashing) { 1482 executeInsts(); 1483 1484 writebackInsts(); 1485 1486 // Have the instruction queue try to schedule any ready instructions. 1487 // (In actuality, this scheduling is for instructions that will 1488 // be executed next cycle.) 1489 instQueue.scheduleReadyInsts(); 1490 1491 // Also should advance its own time buffers if the stage ran. 1492 // Not the best place for it, but this works (hopefully). 1493 issueToExecQueue.advance(); 1494 } 1495 1496 bool broadcast_free_entries = false; 1497 1498 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1499 exeStatus = Idle; 1500 updateLSQNextCycle = false; 1501 1502 broadcast_free_entries = true; 1503 } 1504 1505 // Writeback any stores using any leftover bandwidth. 1506 ldstQueue.writebackStores(); 1507 1508 // Check the committed load/store signals to see if there's a load 1509 // or store to commit. Also check if it's being told to execute a 1510 // nonspeculative instruction. 1511 // This is pretty inefficient... 1512 1513 threads = activeThreads->begin(); 1514 while (threads != end) { 1515 ThreadID tid = (*threads++); 1516 1517 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1518 1519 // Update structures based on instructions committed. 1520 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1521 !fromCommit->commitInfo[tid].squash && 1522 !fromCommit->commitInfo[tid].robSquashing) { 1523 1524 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1525 1526 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1527 1528 updateLSQNextCycle = true; 1529 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1530 } 1531 1532 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1533 1534 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1535 if (fromCommit->commitInfo[tid].strictlyOrdered) { 1536 instQueue.replayMemInst( 1537 fromCommit->commitInfo[tid].strictlyOrderedLoad); 1538 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 1539 } else { 1540 instQueue.scheduleNonSpec( 1541 fromCommit->commitInfo[tid].nonSpecSeqNum); 1542 } 1543 } 1544 1545 if (broadcast_free_entries) { 1546 toFetch->iewInfo[tid].iqCount = 1547 instQueue.getCount(tid); 1548 toFetch->iewInfo[tid].ldstqCount = 1549 ldstQueue.getCount(tid); 1550 1551 toRename->iewInfo[tid].usedIQ = true; 1552 toRename->iewInfo[tid].freeIQEntries = 1553 instQueue.numFreeEntries(tid); 1554 toRename->iewInfo[tid].usedLSQ = true; 1555 1556 toRename->iewInfo[tid].freeLQEntries = 1557 ldstQueue.numFreeLoadEntries(tid); 1558 toRename->iewInfo[tid].freeSQEntries = 1559 ldstQueue.numFreeStoreEntries(tid); 1560 1561 wroteToTimeBuffer = true; 1562 } 1563 1564 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1565 tid, toRename->iewInfo[tid].dispatched); 1566 } 1567 1568 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1569 "LQ has %i free entries. SQ has %i free entries.\n", 1570 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1571 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1572 1573 updateStatus(); 1574 1575 if (wroteToTimeBuffer) { 1576 DPRINTF(Activity, "Activity this cycle.\n"); 1577 cpu->activityThisCycle(); 1578 } 1579} 1580 1581template <class Impl> 1582void 1583DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 1584{ 1585 ThreadID tid = inst->threadNumber; 1586 1587 iewExecutedInsts++; 1588 1589#if TRACING_ON 1590 if (DTRACE(O3PipeView)) { 1591 inst->completeTick = curTick() - inst->fetchTick; 1592 } 1593#endif 1594 1595 // 1596 // Control operations 1597 // 1598 if (inst->isControl()) 1599 iewExecutedBranches[tid]++; 1600 1601 // 1602 // Memory operations 1603 // 1604 if (inst->isMemRef()) { 1605 iewExecutedRefs[tid]++; 1606 1607 if (inst->isLoad()) { 1608 iewExecLoadInsts[tid]++; 1609 } 1610 } 1611} 1612 1613template <class Impl> 1614void 1615DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 1616{ 1617 ThreadID tid = inst->threadNumber; 1618 1619 if (!fetchRedirect[tid] || 1620 !toCommit->squash[tid] || 1621 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1622 1623 if (inst->mispredicted()) { 1624 fetchRedirect[tid] = true; 1625 1626 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1627 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1628 inst->predInstAddr(), inst->predNextInstAddr()); 1629 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1630 " NPC: %#x.\n", inst->nextInstAddr(), 1631 inst->nextInstAddr()); 1632 // If incorrect, then signal the ROB that it must be squashed. 1633 squashDueToBranch(inst, tid); 1634 1635 if (inst->readPredTaken()) { 1636 predictedTakenIncorrect++; 1637 } else { 1638 predictedNotTakenIncorrect++; 1639 } 1640 } 1641 } 1642} 1643 1644#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1645