iew_impl.hh revision 10240:15f822e9410a
12391SN/A/* 210482Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37733SAli.Saidi@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47733SAli.Saidi@ARM.com * All rights reserved. 57733SAli.Saidi@ARM.com * 67733SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77733SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87733SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97733SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107733SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117733SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127733SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137733SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 142391SN/A * 152391SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162391SN/A * All rights reserved. 172391SN/A * 182391SN/A * Redistribution and use in source and binary forms, with or without 192391SN/A * modification, are permitted provided that the following conditions are 202391SN/A * met: redistributions of source code must retain the above copyright 212391SN/A * notice, this list of conditions and the following disclaimer; 222391SN/A * redistributions in binary form must reproduce the above copyright 232391SN/A * notice, this list of conditions and the following disclaimer in the 242391SN/A * documentation and/or other materials provided with the distribution; 252391SN/A * neither the name of the copyright holders nor the names of its 262391SN/A * contributors may be used to endorse or promote products derived from 272391SN/A * this software without specific prior written permission. 282391SN/A * 292391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362665Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378931Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409293Sandreas.hansson@arm.com * 419293Sandreas.hansson@arm.com * Authors: Kevin Lim 429293Sandreas.hansson@arm.com */ 439293Sandreas.hansson@arm.com 449293Sandreas.hansson@arm.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459293Sandreas.hansson@arm.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469293Sandreas.hansson@arm.com 479293Sandreas.hansson@arm.com// @todo: Fix the instantaneous communication among all the stages within 489293Sandreas.hansson@arm.com// iew. There's a clear delay between issue and execute, yet backwards 499293Sandreas.hansson@arm.com// communication happens simultaneously. 509293Sandreas.hansson@arm.com 519293Sandreas.hansson@arm.com#include <queue> 529293Sandreas.hansson@arm.com 539356Snilay@cs.wisc.edu#include "arch/utility.hh" 5410405Sandreas.hansson@arm.com#include "config/the_isa.hh" 559293Sandreas.hansson@arm.com#include "cpu/checker/cpu.hh" 569293Sandreas.hansson@arm.com#include "cpu/o3/fu_pool.hh" 572394SN/A#include "cpu/o3/iew.hh" 582394SN/A#include "cpu/timebuf.hh" 5910700Sandreas.hansson@arm.com#include "debug/Activity.hh" 6010700Sandreas.hansson@arm.com#include "debug/Drain.hh" 6110700Sandreas.hansson@arm.com#include "debug/IEW.hh" 6211446Sbaz21@cam.ac.uk#include "debug/O3PipeView.hh" 6311446Sbaz21@cam.ac.uk#include "params/DerivO3CPU.hh" 6410700Sandreas.hansson@arm.com 6511446Sbaz21@cam.ac.ukusing namespace std; 6610700Sandreas.hansson@arm.com 6710700Sandreas.hansson@arm.comtemplate<class Impl> 6810700Sandreas.hansson@arm.comDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 6910700Sandreas.hansson@arm.com : issueToExecQueue(params->backComSize, params->forwardComSize), 7010700Sandreas.hansson@arm.com cpu(_cpu), 712391SN/A instQueue(_cpu, this, params), 722391SN/A ldstQueue(_cpu, this, params), 739293Sandreas.hansson@arm.com fuPool(params->fuPool), 7410700Sandreas.hansson@arm.com commitToIEWDelay(params->commitToIEWDelay), 7510700Sandreas.hansson@arm.com renameToIEWDelay(params->renameToIEWDelay), 7610700Sandreas.hansson@arm.com issueToExecuteDelay(params->issueToExecuteDelay), 7710700Sandreas.hansson@arm.com dispatchWidth(params->dispatchWidth), 782391SN/A issueWidth(params->issueWidth), 7910700Sandreas.hansson@arm.com wbOutstanding(0), 8010700Sandreas.hansson@arm.com wbWidth(params->wbWidth), 8110700Sandreas.hansson@arm.com numThreads(params->numThreads) 829293Sandreas.hansson@arm.com{ 839293Sandreas.hansson@arm.com if (dispatchWidth > Impl::MaxWidth) 8410482Sandreas.hansson@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 858931Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8610482Sandreas.hansson@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8710482Sandreas.hansson@arm.com if (issueWidth > Impl::MaxWidth) 882391SN/A fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 898931Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9010482Sandreas.hansson@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 918931Sandreas.hansson@arm.com if (wbWidth > Impl::MaxWidth) 928931Sandreas.hansson@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 938931Sandreas.hansson@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9410482Sandreas.hansson@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9510482Sandreas.hansson@arm.com 9610482Sandreas.hansson@arm.com _status = Active; 979293Sandreas.hansson@arm.com exeStatus = Running; 989293Sandreas.hansson@arm.com wbStatus = Idle; 999293Sandreas.hansson@arm.com 1009293Sandreas.hansson@arm.com // Setup wire to read instructions coming from issue. 10110482Sandreas.hansson@arm.com fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 10210482Sandreas.hansson@arm.com 10310482Sandreas.hansson@arm.com // Instruction queue needs the queue between issue and execute. 10410482Sandreas.hansson@arm.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 10510482Sandreas.hansson@arm.com 10610482Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 10710482Sandreas.hansson@arm.com dispatchStatus[tid] = Running; 10810482Sandreas.hansson@arm.com stalls[tid].commit = false; 1099293Sandreas.hansson@arm.com fetchRedirect[tid] = false; 1109293Sandreas.hansson@arm.com } 1119293Sandreas.hansson@arm.com 1129293Sandreas.hansson@arm.com wbMax = wbWidth * params->wbDepth; 11310482Sandreas.hansson@arm.com 11411614Sdavid.j.hashe@gmail.com updateLSQNextCycle = false; 11511614Sdavid.j.hashe@gmail.com 11611614Sdavid.j.hashe@gmail.com ableToIssue = true; 1178931Sandreas.hansson@arm.com 1189293Sandreas.hansson@arm.com skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1199293Sandreas.hansson@arm.com} 12010070Sandreas.hansson@arm.com 12110070Sandreas.hansson@arm.comtemplate <class Impl> 12210070Sandreas.hansson@arm.comstd::string 1239565Sandreas.hansson@arm.comDefaultIEW<Impl>::name() const 1249293Sandreas.hansson@arm.com{ 12510482Sandreas.hansson@arm.com return cpu->name() + ".iew"; 1269293Sandreas.hansson@arm.com} 1279293Sandreas.hansson@arm.com 12810482Sandreas.hansson@arm.comtemplate <class Impl> 1299565Sandreas.hansson@arm.comvoid 13010482Sandreas.hansson@arm.comDefaultIEW<Impl>::regProbePoints() 1319565Sandreas.hansson@arm.com{ 1329565Sandreas.hansson@arm.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1339565Sandreas.hansson@arm.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1349565Sandreas.hansson@arm.com} 13510482Sandreas.hansson@arm.com 1369565Sandreas.hansson@arm.comtemplate <class Impl> 13711614Sdavid.j.hashe@gmail.comvoid 13811614Sdavid.j.hashe@gmail.comDefaultIEW<Impl>::regStats() 13911614Sdavid.j.hashe@gmail.com{ 14011614Sdavid.j.hashe@gmail.com using namespace Stats; 14111614Sdavid.j.hashe@gmail.com 14211614Sdavid.j.hashe@gmail.com instQueue.regStats(); 14311614Sdavid.j.hashe@gmail.com ldstQueue.regStats(); 14411614Sdavid.j.hashe@gmail.com 14511614Sdavid.j.hashe@gmail.com iewIdleCycles 14611614Sdavid.j.hashe@gmail.com .name(name() + ".iewIdleCycles") 14711614Sdavid.j.hashe@gmail.com .desc("Number of cycles IEW is idle"); 14811614Sdavid.j.hashe@gmail.com 14911614Sdavid.j.hashe@gmail.com iewSquashCycles 1509565Sandreas.hansson@arm.com .name(name() + ".iewSquashCycles") 1519565Sandreas.hansson@arm.com .desc("Number of cycles IEW is squashing"); 1529565Sandreas.hansson@arm.com 15310482Sandreas.hansson@arm.com iewBlockCycles 15410482Sandreas.hansson@arm.com .name(name() + ".iewBlockCycles") 1559565Sandreas.hansson@arm.com .desc("Number of cycles IEW is blocking"); 15610482Sandreas.hansson@arm.com 15711614Sdavid.j.hashe@gmail.com iewUnblockCycles 15811614Sdavid.j.hashe@gmail.com .name(name() + ".iewUnblockCycles") 15911614Sdavid.j.hashe@gmail.com .desc("Number of cycles IEW is unblocking"); 16011614Sdavid.j.hashe@gmail.com 1619565Sandreas.hansson@arm.com iewDispatchedInsts 1629293Sandreas.hansson@arm.com .name(name() + ".iewDispatchedInsts") 1639293Sandreas.hansson@arm.com .desc("Number of instructions dispatched to IQ"); 1649565Sandreas.hansson@arm.com 1659565Sandreas.hansson@arm.com iewDispSquashedInsts 1669565Sandreas.hansson@arm.com .name(name() + ".iewDispSquashedInsts") 1679565Sandreas.hansson@arm.com .desc("Number of squashed instructions skipped by dispatch"); 1689565Sandreas.hansson@arm.com 16911614Sdavid.j.hashe@gmail.com iewDispLoadInsts 17011614Sdavid.j.hashe@gmail.com .name(name() + ".iewDispLoadInsts") 17111614Sdavid.j.hashe@gmail.com .desc("Number of dispatched load instructions"); 17211614Sdavid.j.hashe@gmail.com 17311614Sdavid.j.hashe@gmail.com iewDispStoreInsts 17411614Sdavid.j.hashe@gmail.com .name(name() + ".iewDispStoreInsts") 17511614Sdavid.j.hashe@gmail.com .desc("Number of dispatched store instructions"); 17611614Sdavid.j.hashe@gmail.com 17711614Sdavid.j.hashe@gmail.com iewDispNonSpecInsts 17811614Sdavid.j.hashe@gmail.com .name(name() + ".iewDispNonSpecInsts") 17911614Sdavid.j.hashe@gmail.com .desc("Number of dispatched non-speculative instructions"); 18011614Sdavid.j.hashe@gmail.com 1819565Sandreas.hansson@arm.com iewIQFullEvents 1829293Sandreas.hansson@arm.com .name(name() + ".iewIQFullEvents") 1839293Sandreas.hansson@arm.com .desc("Number of times the IQ has become full, causing a stall"); 1849293Sandreas.hansson@arm.com 1859293Sandreas.hansson@arm.com iewLSQFullEvents 18611614Sdavid.j.hashe@gmail.com .name(name() + ".iewLSQFullEvents") 18711614Sdavid.j.hashe@gmail.com .desc("Number of times the LSQ has become full, causing a stall"); 18811614Sdavid.j.hashe@gmail.com 1899293Sandreas.hansson@arm.com memOrderViolationEvents 19010482Sandreas.hansson@arm.com .name(name() + ".memOrderViolationEvents") 19110482Sandreas.hansson@arm.com .desc("Number of memory order violations"); 1929411Sandreas.hansson@arm.com 1939411Sandreas.hansson@arm.com predictedTakenIncorrect 1949293Sandreas.hansson@arm.com .name(name() + ".predictedTakenIncorrect") 19510405Sandreas.hansson@arm.com .desc("Number of branches that were predicted taken incorrectly"); 1969411Sandreas.hansson@arm.com 1979293Sandreas.hansson@arm.com predictedNotTakenIncorrect 19810700Sandreas.hansson@arm.com .name(name() + ".predictedNotTakenIncorrect") 19910700Sandreas.hansson@arm.com .desc("Number of branches that were predicted not taken incorrectly"); 20010700Sandreas.hansson@arm.com 20110700Sandreas.hansson@arm.com branchMispredicts 20210700Sandreas.hansson@arm.com .name(name() + ".branchMispredicts") 20310700Sandreas.hansson@arm.com .desc("Number of branch mispredicts detected at execute"); 20410700Sandreas.hansson@arm.com 2059293Sandreas.hansson@arm.com branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2069293Sandreas.hansson@arm.com 2079293Sandreas.hansson@arm.com iewExecutedInsts 2089293Sandreas.hansson@arm.com .name(name() + ".iewExecutedInsts") 2099293Sandreas.hansson@arm.com .desc("Number of executed instructions"); 2109293Sandreas.hansson@arm.com 2119405Sandreas.hansson@arm.com iewExecLoadInsts 2129405Sandreas.hansson@arm.com .init(cpu->numThreads) 2139293Sandreas.hansson@arm.com .name(name() + ".iewExecLoadInsts") 2149293Sandreas.hansson@arm.com .desc("Number of load instructions executed") 2159293Sandreas.hansson@arm.com .flags(total); 2169293Sandreas.hansson@arm.com 21711614Sdavid.j.hashe@gmail.com iewExecSquashedInsts 21811614Sdavid.j.hashe@gmail.com .name(name() + ".iewExecSquashedInsts") 2199293Sandreas.hansson@arm.com .desc("Number of squashed instructions skipped in execute"); 22010070Sandreas.hansson@arm.com 22110482Sandreas.hansson@arm.com iewExecutedSwp 22210405Sandreas.hansson@arm.com .init(cpu->numThreads) 22310482Sandreas.hansson@arm.com .name(name() + ".exec_swp") 22410482Sandreas.hansson@arm.com .desc("number of swp insts executed") 2258931Sandreas.hansson@arm.com .flags(total); 2268931Sandreas.hansson@arm.com 2278931Sandreas.hansson@arm.com iewExecutedNop 2289293Sandreas.hansson@arm.com .init(cpu->numThreads) 2299293Sandreas.hansson@arm.com .name(name() + ".exec_nop") 2309293Sandreas.hansson@arm.com .desc("number of nop insts executed") 23110482Sandreas.hansson@arm.com .flags(total); 23211614Sdavid.j.hashe@gmail.com 2339293Sandreas.hansson@arm.com iewExecutedRefs 2349293Sandreas.hansson@arm.com .init(cpu->numThreads) 2358931Sandreas.hansson@arm.com .name(name() + ".exec_refs") 2368931Sandreas.hansson@arm.com .desc("number of memory reference insts executed") 2378931Sandreas.hansson@arm.com .flags(total); 2388931Sandreas.hansson@arm.com 23910699Sandreas.hansson@arm.com iewExecutedBranches 24010699Sandreas.hansson@arm.com .init(cpu->numThreads) 24110699Sandreas.hansson@arm.com .name(name() + ".exec_branches") 2428931Sandreas.hansson@arm.com .desc("Number of branches executed") 24310482Sandreas.hansson@arm.com .flags(total); 2448931Sandreas.hansson@arm.com 2458931Sandreas.hansson@arm.com iewExecStoreInsts 2468931Sandreas.hansson@arm.com .name(name() + ".exec_stores") 2478931Sandreas.hansson@arm.com .desc("Number of stores executed") 2488931Sandreas.hansson@arm.com .flags(total); 24910699Sandreas.hansson@arm.com iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 25010699Sandreas.hansson@arm.com 2518851Sandreas.hansson@arm.com iewExecRate 2528931Sandreas.hansson@arm.com .name(name() + ".exec_rate") 2537730SAli.Saidi@ARM.com .desc("Inst execution rate") 2548931Sandreas.hansson@arm.com .flags(total); 2558931Sandreas.hansson@arm.com 2568931Sandreas.hansson@arm.com iewExecRate = iewExecutedInsts / cpu->numCycles; 2578931Sandreas.hansson@arm.com 2588931Sandreas.hansson@arm.com iewInstsToCommit 2598931Sandreas.hansson@arm.com .init(cpu->numThreads) 2609413Sandreas.hansson@arm.com .name(name() + ".wb_sent") 26110482Sandreas.hansson@arm.com .desc("cumulative count of insts sent to commit") 26210482Sandreas.hansson@arm.com .flags(total); 2639413Sandreas.hansson@arm.com 26410482Sandreas.hansson@arm.com writebackCount 2659413Sandreas.hansson@arm.com .init(cpu->numThreads) 2669413Sandreas.hansson@arm.com .name(name() + ".wb_count") 2679413Sandreas.hansson@arm.com .desc("cumulative count of insts written-back") 2689413Sandreas.hansson@arm.com .flags(total); 26910482Sandreas.hansson@arm.com 2709413Sandreas.hansson@arm.com producerInst 2719413Sandreas.hansson@arm.com .init(cpu->numThreads) 2729413Sandreas.hansson@arm.com .name(name() + ".wb_producers") 27310482Sandreas.hansson@arm.com .desc("num instructions producing a value") 2749413Sandreas.hansson@arm.com .flags(total); 2759413Sandreas.hansson@arm.com 27610482Sandreas.hansson@arm.com consumerInst 2779413Sandreas.hansson@arm.com .init(cpu->numThreads) 2788931Sandreas.hansson@arm.com .name(name() + ".wb_consumers") 2797730SAli.Saidi@ARM.com .desc("num instructions consuming a value") 2802391SN/A .flags(total); 2819413Sandreas.hansson@arm.com 2829413Sandreas.hansson@arm.com wbPenalized 2839413Sandreas.hansson@arm.com .init(cpu->numThreads) 2849413Sandreas.hansson@arm.com .name(name() + ".wb_penalized") 2859413Sandreas.hansson@arm.com .desc("number of instrctions required to write to 'other' IQ") 2869413Sandreas.hansson@arm.com .flags(total); 2878931Sandreas.hansson@arm.com 2882391SN/A wbPenalizedRate 2892391SN/A .name(name() + ".wb_penalized_rate") 2902541SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2918931Sandreas.hansson@arm.com .flags(total); 2922541SN/A 2938931Sandreas.hansson@arm.com wbPenalizedRate = wbPenalized / writebackCount; 2948931Sandreas.hansson@arm.com 29510699Sandreas.hansson@arm.com wbFanout 29610699Sandreas.hansson@arm.com .name(name() + ".wb_fanout") 29710699Sandreas.hansson@arm.com .desc("average fanout of values written-back") 29810699Sandreas.hansson@arm.com .flags(total); 29910699Sandreas.hansson@arm.com 30010699Sandreas.hansson@arm.com wbFanout = producerInst / consumerInst; 30110699Sandreas.hansson@arm.com 30210699Sandreas.hansson@arm.com wbRate 30310699Sandreas.hansson@arm.com .name(name() + ".wb_rate") 3042391SN/A .desc("insts written-back per cycle") 3052391SN/A .flags(total); 3068719SAli.Saidi@ARM.com wbRate = writebackCount / cpu->numCycles; 3078931Sandreas.hansson@arm.com} 3088719SAli.Saidi@ARM.com 3098931Sandreas.hansson@arm.comtemplate<class Impl> 3108931Sandreas.hansson@arm.comvoid 31110699Sandreas.hansson@arm.comDefaultIEW<Impl>::startupStage() 31210699Sandreas.hansson@arm.com{ 31310699Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 31410699Sandreas.hansson@arm.com toRename->iewInfo[tid].usedIQ = true; 31510699Sandreas.hansson@arm.com toRename->iewInfo[tid].freeIQEntries = 31610699Sandreas.hansson@arm.com instQueue.numFreeEntries(tid); 31710699Sandreas.hansson@arm.com 31810699Sandreas.hansson@arm.com toRename->iewInfo[tid].usedLSQ = true; 31910699Sandreas.hansson@arm.com toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3208719SAli.Saidi@ARM.com toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3219293Sandreas.hansson@arm.com } 3229293Sandreas.hansson@arm.com 32310905Sandreas.sandberg@arm.com // Initialize the checker's dcache port here 3249293Sandreas.hansson@arm.com if (cpu->checker) { 3259293Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3269293Sandreas.hansson@arm.com } 32711005Sandreas.sandberg@arm.com 3289293Sandreas.hansson@arm.com cpu->activateStage(O3CPU::IEWIdx); 32910482Sandreas.hansson@arm.com} 33010482Sandreas.hansson@arm.com 33110482Sandreas.hansson@arm.comtemplate<class Impl> 33210482Sandreas.hansson@arm.comvoid 33310482Sandreas.hansson@arm.comDefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3349293Sandreas.hansson@arm.com{ 3359293Sandreas.hansson@arm.com timeBuffer = tb_ptr; 3369293Sandreas.hansson@arm.com 33710905Sandreas.sandberg@arm.com // Setup wire to read information from time buffer, from commit. 33810905Sandreas.sandberg@arm.com fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3399293Sandreas.hansson@arm.com 3409293Sandreas.hansson@arm.com // Setup wire to write information back to previous stages. 3419293Sandreas.hansson@arm.com toRename = timeBuffer->getWire(0); 3429293Sandreas.hansson@arm.com 3439293Sandreas.hansson@arm.com toFetch = timeBuffer->getWire(0); 3449293Sandreas.hansson@arm.com 3459293Sandreas.hansson@arm.com // Instruction queue also needs main time buffer. 34610482Sandreas.hansson@arm.com instQueue.setTimeBuffer(tb_ptr); 34710905Sandreas.sandberg@arm.com} 34811614Sdavid.j.hashe@gmail.com 3499293Sandreas.hansson@arm.comtemplate<class Impl> 3509293Sandreas.hansson@arm.comvoid 3519293Sandreas.hansson@arm.comDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3529293Sandreas.hansson@arm.com{ 35310905Sandreas.sandberg@arm.com renameQueue = rq_ptr; 35410905Sandreas.sandberg@arm.com 3559293Sandreas.hansson@arm.com // Setup wire to read information from rename queue. 3569293Sandreas.hansson@arm.com fromRename = renameQueue->getWire(-renameToIEWDelay); 3579293Sandreas.hansson@arm.com} 3589386Sandreas.hansson@arm.com 3599293Sandreas.hansson@arm.comtemplate<class Impl> 3609293Sandreas.hansson@arm.comvoid 3619293Sandreas.hansson@arm.comDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3629293Sandreas.hansson@arm.com{ 3639293Sandreas.hansson@arm.com iewQueue = iq_ptr; 3649293Sandreas.hansson@arm.com 3659293Sandreas.hansson@arm.com // Setup wire to write instructions to commit. 3669293Sandreas.hansson@arm.com toCommit = iewQueue->getWire(0); 3679293Sandreas.hansson@arm.com} 3689293Sandreas.hansson@arm.com 36910905Sandreas.sandberg@arm.comtemplate<class Impl> 37010412Sandreas.hansson@arm.comvoid 37110412Sandreas.hansson@arm.comDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3729293Sandreas.hansson@arm.com{ 3739293Sandreas.hansson@arm.com activeThreads = at_ptr; 3749293Sandreas.hansson@arm.com 3759293Sandreas.hansson@arm.com ldstQueue.setActiveThreads(at_ptr); 3769293Sandreas.hansson@arm.com instQueue.setActiveThreads(at_ptr); 3779293Sandreas.hansson@arm.com} 3789293Sandreas.hansson@arm.com 3799293Sandreas.hansson@arm.comtemplate<class Impl> 3809293Sandreas.hansson@arm.comvoid 3819293Sandreas.hansson@arm.comDefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3829293Sandreas.hansson@arm.com{ 3839293Sandreas.hansson@arm.com scoreboard = sb_ptr; 3849293Sandreas.hansson@arm.com} 3859293Sandreas.hansson@arm.com 3869293Sandreas.hansson@arm.comtemplate <class Impl> 3879293Sandreas.hansson@arm.combool 3889293Sandreas.hansson@arm.comDefaultIEW<Impl>::isDrained() const 3899293Sandreas.hansson@arm.com{ 3909293Sandreas.hansson@arm.com bool drained(ldstQueue.isDrained()); 3919293Sandreas.hansson@arm.com 3929293Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3939293Sandreas.hansson@arm.com if (!insts[tid].empty()) { 3949293Sandreas.hansson@arm.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3959293Sandreas.hansson@arm.com drained = false; 3969293Sandreas.hansson@arm.com } 3979293Sandreas.hansson@arm.com if (!skidBuffer[tid].empty()) { 3989293Sandreas.hansson@arm.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 39910905Sandreas.sandberg@arm.com drained = false; 4009293Sandreas.hansson@arm.com } 4019293Sandreas.hansson@arm.com } 4029293Sandreas.hansson@arm.com 4039293Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 40411005Sandreas.sandberg@arm.com // completion events until they are done and not accounted for 40510905Sandreas.sandberg@arm.com // above 40610905Sandreas.sandberg@arm.com if (drained && !fuPool->isDrained()) { 40711321Ssteve.reinhardt@amd.com DPRINTF(Drain, "FU pool still busy.\n"); 40810482Sandreas.hansson@arm.com drained = false; 4099293Sandreas.hansson@arm.com } 4109293Sandreas.hansson@arm.com 4119293Sandreas.hansson@arm.com return drained; 4129293Sandreas.hansson@arm.com} 4139293Sandreas.hansson@arm.com 4149293Sandreas.hansson@arm.comtemplate <class Impl> 4159293Sandreas.hansson@arm.comvoid 4169293Sandreas.hansson@arm.comDefaultIEW<Impl>::drainSanityCheck() const 41710905Sandreas.sandberg@arm.com{ 41810905Sandreas.sandberg@arm.com assert(isDrained()); 4199293Sandreas.hansson@arm.com 4209293Sandreas.hansson@arm.com instQueue.drainSanityCheck(); 4219293Sandreas.hansson@arm.com ldstQueue.drainSanityCheck(); 4229293Sandreas.hansson@arm.com} 4239293Sandreas.hansson@arm.com 42410905Sandreas.sandberg@arm.comtemplate <class Impl> 4259293Sandreas.hansson@arm.comvoid 4269293Sandreas.hansson@arm.comDefaultIEW<Impl>::takeOverFrom() 4279293Sandreas.hansson@arm.com{ 4289293Sandreas.hansson@arm.com // Reset all state. 4299293Sandreas.hansson@arm.com _status = Active; 4309293Sandreas.hansson@arm.com exeStatus = Running; 4319293Sandreas.hansson@arm.com wbStatus = Idle; 4329293Sandreas.hansson@arm.com 43310905Sandreas.sandberg@arm.com instQueue.takeOverFrom(); 4349293Sandreas.hansson@arm.com ldstQueue.takeOverFrom(); 4359293Sandreas.hansson@arm.com fuPool->takeOverFrom(); 43610412Sandreas.hansson@arm.com 43710412Sandreas.hansson@arm.com startupStage(); 4389293Sandreas.hansson@arm.com cpu->activityThisCycle(); 4399293Sandreas.hansson@arm.com 44010070Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 44111614Sdavid.j.hashe@gmail.com dispatchStatus[tid] = Running; 44211614Sdavid.j.hashe@gmail.com stalls[tid].commit = false; 4439293Sandreas.hansson@arm.com fetchRedirect[tid] = false; 4449293Sandreas.hansson@arm.com } 4459293Sandreas.hansson@arm.com 4469293Sandreas.hansson@arm.com updateLSQNextCycle = false; 4479293Sandreas.hansson@arm.com 4489293Sandreas.hansson@arm.com for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4499293Sandreas.hansson@arm.com issueToExecQueue.advance(); 4509293Sandreas.hansson@arm.com } 4519293Sandreas.hansson@arm.com} 4529293Sandreas.hansson@arm.com 4539293Sandreas.hansson@arm.comtemplate<class Impl> 4549293Sandreas.hansson@arm.comvoid 4559293Sandreas.hansson@arm.comDefaultIEW<Impl>::squash(ThreadID tid) 4569293Sandreas.hansson@arm.com{ 4579293Sandreas.hansson@arm.com DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4589293Sandreas.hansson@arm.com 4599293Sandreas.hansson@arm.com // Tell the IQ to start squashing. 4609293Sandreas.hansson@arm.com instQueue.squash(tid); 4619293Sandreas.hansson@arm.com 4629293Sandreas.hansson@arm.com // Tell the LDSTQ to start squashing. 4639293Sandreas.hansson@arm.com ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4649293Sandreas.hansson@arm.com updatedQueues = true; 4659293Sandreas.hansson@arm.com 4669293Sandreas.hansson@arm.com // Clear the skid buffer in case it has any data in it. 4679293Sandreas.hansson@arm.com DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4689293Sandreas.hansson@arm.com tid, fromCommit->commitInfo[tid].doneSeqNum); 4699293Sandreas.hansson@arm.com 4709293Sandreas.hansson@arm.com while (!skidBuffer[tid].empty()) { 4719293Sandreas.hansson@arm.com if (skidBuffer[tid].front()->isLoad()) { 4729293Sandreas.hansson@arm.com toRename->iewInfo[tid].dispatchedToLQ++; 4739293Sandreas.hansson@arm.com } 4749293Sandreas.hansson@arm.com if (skidBuffer[tid].front()->isStore()) { 4759293Sandreas.hansson@arm.com toRename->iewInfo[tid].dispatchedToSQ++; 4769293Sandreas.hansson@arm.com } 4779293Sandreas.hansson@arm.com 4789293Sandreas.hansson@arm.com toRename->iewInfo[tid].dispatched++; 4799293Sandreas.hansson@arm.com 4809293Sandreas.hansson@arm.com skidBuffer[tid].pop(); 4819293Sandreas.hansson@arm.com } 482 483 emptyRenameInsts(tid); 484} 485 486template<class Impl> 487void 488DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 489{ 490 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 491 "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 492 493 if (!toCommit->squash[tid] || 494 inst->seqNum < toCommit->squashedSeqNum[tid]) { 495 toCommit->squash[tid] = true; 496 toCommit->squashedSeqNum[tid] = inst->seqNum; 497 toCommit->branchTaken[tid] = inst->pcState().branching(); 498 499 TheISA::PCState pc = inst->pcState(); 500 TheISA::advancePC(pc, inst->staticInst); 501 502 toCommit->pc[tid] = pc; 503 toCommit->mispredictInst[tid] = inst; 504 toCommit->includeSquashInst[tid] = false; 505 506 wroteToTimeBuffer = true; 507 } 508 509} 510 511template<class Impl> 512void 513DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 514{ 515 DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 516 "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 517 // Need to include inst->seqNum in the following comparison to cover the 518 // corner case when a branch misprediction and a memory violation for the 519 // same instruction (e.g. load PC) are detected in the same cycle. In this 520 // case the memory violator should take precedence over the branch 521 // misprediction because it requires the violator itself to be included in 522 // the squash. 523 if (!toCommit->squash[tid] || 524 inst->seqNum <= toCommit->squashedSeqNum[tid]) { 525 toCommit->squash[tid] = true; 526 527 toCommit->squashedSeqNum[tid] = inst->seqNum; 528 toCommit->pc[tid] = inst->pcState(); 529 toCommit->mispredictInst[tid] = NULL; 530 531 // Must include the memory violator in the squash. 532 toCommit->includeSquashInst[tid] = true; 533 534 wroteToTimeBuffer = true; 535 } 536} 537 538template<class Impl> 539void 540DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 541{ 542 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 543 "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 544 if (!toCommit->squash[tid] || 545 inst->seqNum < toCommit->squashedSeqNum[tid]) { 546 toCommit->squash[tid] = true; 547 548 toCommit->squashedSeqNum[tid] = inst->seqNum; 549 toCommit->pc[tid] = inst->pcState(); 550 toCommit->mispredictInst[tid] = NULL; 551 552 // Must include the broadcasted SN in the squash. 553 toCommit->includeSquashInst[tid] = true; 554 555 ldstQueue.setLoadBlockedHandled(tid); 556 557 wroteToTimeBuffer = true; 558 } 559} 560 561template<class Impl> 562void 563DefaultIEW<Impl>::block(ThreadID tid) 564{ 565 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 566 567 if (dispatchStatus[tid] != Blocked && 568 dispatchStatus[tid] != Unblocking) { 569 toRename->iewBlock[tid] = true; 570 wroteToTimeBuffer = true; 571 } 572 573 // Add the current inputs to the skid buffer so they can be 574 // reprocessed when this stage unblocks. 575 skidInsert(tid); 576 577 dispatchStatus[tid] = Blocked; 578} 579 580template<class Impl> 581void 582DefaultIEW<Impl>::unblock(ThreadID tid) 583{ 584 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 585 "buffer %u.\n",tid, tid); 586 587 // If the skid bufffer is empty, signal back to previous stages to unblock. 588 // Also switch status to running. 589 if (skidBuffer[tid].empty()) { 590 toRename->iewUnblock[tid] = true; 591 wroteToTimeBuffer = true; 592 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 593 dispatchStatus[tid] = Running; 594 } 595} 596 597template<class Impl> 598void 599DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 600{ 601 instQueue.wakeDependents(inst); 602} 603 604template<class Impl> 605void 606DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 607{ 608 instQueue.rescheduleMemInst(inst); 609} 610 611template<class Impl> 612void 613DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 614{ 615 instQueue.replayMemInst(inst); 616} 617 618template<class Impl> 619void 620DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 621{ 622 // This function should not be called after writebackInsts in a 623 // single cycle. That will cause problems with an instruction 624 // being added to the queue to commit without being processed by 625 // writebackInsts prior to being sent to commit. 626 627 // First check the time slot that this instruction will write 628 // to. If there are free write ports at the time, then go ahead 629 // and write the instruction to that time. If there are not, 630 // keep looking back to see where's the first time there's a 631 // free slot. 632 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 633 ++wbNumInst; 634 if (wbNumInst == wbWidth) { 635 ++wbCycle; 636 wbNumInst = 0; 637 } 638 639 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 640 } 641 642 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 643 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 644 // Add finished instruction to queue to commit. 645 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 646 (*iewQueue)[wbCycle].size++; 647} 648 649template <class Impl> 650unsigned 651DefaultIEW<Impl>::validInstsFromRename() 652{ 653 unsigned inst_count = 0; 654 655 for (int i=0; i<fromRename->size; i++) { 656 if (!fromRename->insts[i]->isSquashed()) 657 inst_count++; 658 } 659 660 return inst_count; 661} 662 663template<class Impl> 664void 665DefaultIEW<Impl>::skidInsert(ThreadID tid) 666{ 667 DynInstPtr inst = NULL; 668 669 while (!insts[tid].empty()) { 670 inst = insts[tid].front(); 671 672 insts[tid].pop(); 673 674 DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 675 "dispatch skidBuffer %i\n",tid, inst->seqNum, 676 inst->pcState(),tid); 677 678 skidBuffer[tid].push(inst); 679 } 680 681 assert(skidBuffer[tid].size() <= skidBufferMax && 682 "Skidbuffer Exceeded Max Size"); 683} 684 685template<class Impl> 686int 687DefaultIEW<Impl>::skidCount() 688{ 689 int max=0; 690 691 list<ThreadID>::iterator threads = activeThreads->begin(); 692 list<ThreadID>::iterator end = activeThreads->end(); 693 694 while (threads != end) { 695 ThreadID tid = *threads++; 696 unsigned thread_count = skidBuffer[tid].size(); 697 if (max < thread_count) 698 max = thread_count; 699 } 700 701 return max; 702} 703 704template<class Impl> 705bool 706DefaultIEW<Impl>::skidsEmpty() 707{ 708 list<ThreadID>::iterator threads = activeThreads->begin(); 709 list<ThreadID>::iterator end = activeThreads->end(); 710 711 while (threads != end) { 712 ThreadID tid = *threads++; 713 714 if (!skidBuffer[tid].empty()) 715 return false; 716 } 717 718 return true; 719} 720 721template <class Impl> 722void 723DefaultIEW<Impl>::updateStatus() 724{ 725 bool any_unblocking = false; 726 727 list<ThreadID>::iterator threads = activeThreads->begin(); 728 list<ThreadID>::iterator end = activeThreads->end(); 729 730 while (threads != end) { 731 ThreadID tid = *threads++; 732 733 if (dispatchStatus[tid] == Unblocking) { 734 any_unblocking = true; 735 break; 736 } 737 } 738 739 // If there are no ready instructions waiting to be scheduled by the IQ, 740 // and there's no stores waiting to write back, and dispatch is not 741 // unblocking, then there is no internal activity for the IEW stage. 742 instQueue.intInstQueueReads++; 743 if (_status == Active && !instQueue.hasReadyInsts() && 744 !ldstQueue.willWB() && !any_unblocking) { 745 DPRINTF(IEW, "IEW switching to idle\n"); 746 747 deactivateStage(); 748 749 _status = Inactive; 750 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 751 ldstQueue.willWB() || 752 any_unblocking)) { 753 // Otherwise there is internal activity. Set to active. 754 DPRINTF(IEW, "IEW switching to active\n"); 755 756 activateStage(); 757 758 _status = Active; 759 } 760} 761 762template <class Impl> 763void 764DefaultIEW<Impl>::resetEntries() 765{ 766 instQueue.resetEntries(); 767 ldstQueue.resetEntries(); 768} 769 770template <class Impl> 771void 772DefaultIEW<Impl>::readStallSignals(ThreadID tid) 773{ 774 if (fromCommit->commitBlock[tid]) { 775 stalls[tid].commit = true; 776 } 777 778 if (fromCommit->commitUnblock[tid]) { 779 assert(stalls[tid].commit); 780 stalls[tid].commit = false; 781 } 782} 783 784template <class Impl> 785bool 786DefaultIEW<Impl>::checkStall(ThreadID tid) 787{ 788 bool ret_val(false); 789 790 if (stalls[tid].commit) { 791 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 792 ret_val = true; 793 } else if (instQueue.isFull(tid)) { 794 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 795 ret_val = true; 796 } 797 798 return ret_val; 799} 800 801template <class Impl> 802void 803DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 804{ 805 // Check if there's a squash signal, squash if there is 806 // Check stall signals, block if there is. 807 // If status was Blocked 808 // if so then go to unblocking 809 // If status was Squashing 810 // check if squashing is not high. Switch to running this cycle. 811 812 readStallSignals(tid); 813 814 if (fromCommit->commitInfo[tid].squash) { 815 squash(tid); 816 817 if (dispatchStatus[tid] == Blocked || 818 dispatchStatus[tid] == Unblocking) { 819 toRename->iewUnblock[tid] = true; 820 wroteToTimeBuffer = true; 821 } 822 823 dispatchStatus[tid] = Squashing; 824 fetchRedirect[tid] = false; 825 return; 826 } 827 828 if (fromCommit->commitInfo[tid].robSquashing) { 829 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 830 831 dispatchStatus[tid] = Squashing; 832 emptyRenameInsts(tid); 833 wroteToTimeBuffer = true; 834 return; 835 } 836 837 if (checkStall(tid)) { 838 block(tid); 839 dispatchStatus[tid] = Blocked; 840 return; 841 } 842 843 if (dispatchStatus[tid] == Blocked) { 844 // Status from previous cycle was blocked, but there are no more stall 845 // conditions. Switch over to unblocking. 846 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 847 tid); 848 849 dispatchStatus[tid] = Unblocking; 850 851 unblock(tid); 852 853 return; 854 } 855 856 if (dispatchStatus[tid] == Squashing) { 857 // Switch status to running if rename isn't being told to block or 858 // squash this cycle. 859 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 860 tid); 861 862 dispatchStatus[tid] = Running; 863 864 return; 865 } 866} 867 868template <class Impl> 869void 870DefaultIEW<Impl>::sortInsts() 871{ 872 int insts_from_rename = fromRename->size; 873#ifdef DEBUG 874 for (ThreadID tid = 0; tid < numThreads; tid++) 875 assert(insts[tid].empty()); 876#endif 877 for (int i = 0; i < insts_from_rename; ++i) { 878 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 879 } 880} 881 882template <class Impl> 883void 884DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 885{ 886 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 887 888 while (!insts[tid].empty()) { 889 890 if (insts[tid].front()->isLoad()) { 891 toRename->iewInfo[tid].dispatchedToLQ++; 892 } 893 if (insts[tid].front()->isStore()) { 894 toRename->iewInfo[tid].dispatchedToSQ++; 895 } 896 897 toRename->iewInfo[tid].dispatched++; 898 899 insts[tid].pop(); 900 } 901} 902 903template <class Impl> 904void 905DefaultIEW<Impl>::wakeCPU() 906{ 907 cpu->wakeCPU(); 908} 909 910template <class Impl> 911void 912DefaultIEW<Impl>::activityThisCycle() 913{ 914 DPRINTF(Activity, "Activity this cycle.\n"); 915 cpu->activityThisCycle(); 916} 917 918template <class Impl> 919inline void 920DefaultIEW<Impl>::activateStage() 921{ 922 DPRINTF(Activity, "Activating stage.\n"); 923 cpu->activateStage(O3CPU::IEWIdx); 924} 925 926template <class Impl> 927inline void 928DefaultIEW<Impl>::deactivateStage() 929{ 930 DPRINTF(Activity, "Deactivating stage.\n"); 931 cpu->deactivateStage(O3CPU::IEWIdx); 932} 933 934template<class Impl> 935void 936DefaultIEW<Impl>::dispatch(ThreadID tid) 937{ 938 // If status is Running or idle, 939 // call dispatchInsts() 940 // If status is Unblocking, 941 // buffer any instructions coming from rename 942 // continue trying to empty skid buffer 943 // check if stall conditions have passed 944 945 if (dispatchStatus[tid] == Blocked) { 946 ++iewBlockCycles; 947 948 } else if (dispatchStatus[tid] == Squashing) { 949 ++iewSquashCycles; 950 } 951 952 // Dispatch should try to dispatch as many instructions as its bandwidth 953 // will allow, as long as it is not currently blocked. 954 if (dispatchStatus[tid] == Running || 955 dispatchStatus[tid] == Idle) { 956 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 957 "dispatch.\n", tid); 958 959 dispatchInsts(tid); 960 } else if (dispatchStatus[tid] == Unblocking) { 961 // Make sure that the skid buffer has something in it if the 962 // status is unblocking. 963 assert(!skidsEmpty()); 964 965 // If the status was unblocking, then instructions from the skid 966 // buffer were used. Remove those instructions and handle 967 // the rest of unblocking. 968 dispatchInsts(tid); 969 970 ++iewUnblockCycles; 971 972 if (validInstsFromRename()) { 973 // Add the current inputs to the skid buffer so they can be 974 // reprocessed when this stage unblocks. 975 skidInsert(tid); 976 } 977 978 unblock(tid); 979 } 980} 981 982template <class Impl> 983void 984DefaultIEW<Impl>::dispatchInsts(ThreadID tid) 985{ 986 // Obtain instructions from skid buffer if unblocking, or queue from rename 987 // otherwise. 988 std::queue<DynInstPtr> &insts_to_dispatch = 989 dispatchStatus[tid] == Unblocking ? 990 skidBuffer[tid] : insts[tid]; 991 992 int insts_to_add = insts_to_dispatch.size(); 993 994 DynInstPtr inst; 995 bool add_to_iq = false; 996 int dis_num_inst = 0; 997 998 // Loop through the instructions, putting them in the instruction 999 // queue. 1000 for ( ; dis_num_inst < insts_to_add && 1001 dis_num_inst < dispatchWidth; 1002 ++dis_num_inst) 1003 { 1004 inst = insts_to_dispatch.front(); 1005 1006 if (dispatchStatus[tid] == Unblocking) { 1007 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 1008 "buffer\n", tid); 1009 } 1010 1011 // Make sure there's a valid instruction there. 1012 assert(inst); 1013 1014 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 1015 "IQ.\n", 1016 tid, inst->pcState(), inst->seqNum, inst->threadNumber); 1017 1018 // Be sure to mark these instructions as ready so that the 1019 // commit stage can go ahead and execute them, and mark 1020 // them as issued so the IQ doesn't reprocess them. 1021 1022 // Check for squashed instructions. 1023 if (inst->isSquashed()) { 1024 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1025 "not adding to IQ.\n", tid); 1026 1027 ++iewDispSquashedInsts; 1028 1029 insts_to_dispatch.pop(); 1030 1031 //Tell Rename That An Instruction has been processed 1032 if (inst->isLoad()) { 1033 toRename->iewInfo[tid].dispatchedToLQ++; 1034 } 1035 if (inst->isStore()) { 1036 toRename->iewInfo[tid].dispatchedToSQ++; 1037 } 1038 1039 toRename->iewInfo[tid].dispatched++; 1040 1041 continue; 1042 } 1043 1044 // Check for full conditions. 1045 if (instQueue.isFull(tid)) { 1046 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1047 1048 // Call function to start blocking. 1049 block(tid); 1050 1051 // Set unblock to false. Special case where we are using 1052 // skidbuffer (unblocking) instructions but then we still 1053 // get full in the IQ. 1054 toRename->iewUnblock[tid] = false; 1055 1056 ++iewIQFullEvents; 1057 break; 1058 } 1059 1060 // Check LSQ if inst is LD/ST 1061 if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 1062 (inst->isStore() && ldstQueue.sqFull(tid))) { 1063 DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 1064 inst->isLoad() ? "LQ" : "SQ"); 1065 1066 // Call function to start blocking. 1067 block(tid); 1068 1069 // Set unblock to false. Special case where we are using 1070 // skidbuffer (unblocking) instructions but then we still 1071 // get full in the IQ. 1072 toRename->iewUnblock[tid] = false; 1073 1074 ++iewLSQFullEvents; 1075 break; 1076 } 1077 1078 // Otherwise issue the instruction just fine. 1079 if (inst->isLoad()) { 1080 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1081 "encountered, adding to LSQ.\n", tid); 1082 1083 // Reserve a spot in the load store queue for this 1084 // memory access. 1085 ldstQueue.insertLoad(inst); 1086 1087 ++iewDispLoadInsts; 1088 1089 add_to_iq = true; 1090 1091 toRename->iewInfo[tid].dispatchedToLQ++; 1092 } else if (inst->isStore()) { 1093 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1094 "encountered, adding to LSQ.\n", tid); 1095 1096 ldstQueue.insertStore(inst); 1097 1098 ++iewDispStoreInsts; 1099 1100 if (inst->isStoreConditional()) { 1101 // Store conditionals need to be set as "canCommit()" 1102 // so that commit can process them when they reach the 1103 // head of commit. 1104 // @todo: This is somewhat specific to Alpha. 1105 inst->setCanCommit(); 1106 instQueue.insertNonSpec(inst); 1107 add_to_iq = false; 1108 1109 ++iewDispNonSpecInsts; 1110 } else { 1111 add_to_iq = true; 1112 } 1113 1114 toRename->iewInfo[tid].dispatchedToSQ++; 1115 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1116 // Same as non-speculative stores. 1117 inst->setCanCommit(); 1118 instQueue.insertBarrier(inst); 1119 add_to_iq = false; 1120 } else if (inst->isNop()) { 1121 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1122 "skipping.\n", tid); 1123 1124 inst->setIssued(); 1125 inst->setExecuted(); 1126 inst->setCanCommit(); 1127 1128 instQueue.recordProducer(inst); 1129 1130 iewExecutedNop[tid]++; 1131 1132 add_to_iq = false; 1133 } else if (inst->isExecuted()) { 1134 assert(0 && "Instruction shouldn't be executed.\n"); 1135 DPRINTF(IEW, "Issue: Executed branch encountered, " 1136 "skipping.\n"); 1137 1138 inst->setIssued(); 1139 inst->setCanCommit(); 1140 1141 instQueue.recordProducer(inst); 1142 1143 add_to_iq = false; 1144 } else { 1145 add_to_iq = true; 1146 } 1147 if (inst->isNonSpeculative()) { 1148 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1149 "encountered, skipping.\n", tid); 1150 1151 // Same as non-speculative stores. 1152 inst->setCanCommit(); 1153 1154 // Specifically insert it as nonspeculative. 1155 instQueue.insertNonSpec(inst); 1156 1157 ++iewDispNonSpecInsts; 1158 1159 add_to_iq = false; 1160 } 1161 1162 // If the instruction queue is not full, then add the 1163 // instruction. 1164 if (add_to_iq) { 1165 instQueue.insert(inst); 1166 } 1167 1168 insts_to_dispatch.pop(); 1169 1170 toRename->iewInfo[tid].dispatched++; 1171 1172 ++iewDispatchedInsts; 1173 1174#if TRACING_ON 1175 inst->dispatchTick = curTick() - inst->fetchTick; 1176#endif 1177 ppDispatch->notify(inst); 1178 } 1179 1180 if (!insts_to_dispatch.empty()) { 1181 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1182 block(tid); 1183 toRename->iewUnblock[tid] = false; 1184 } 1185 1186 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1187 dispatchStatus[tid] = Running; 1188 1189 updatedQueues = true; 1190 } 1191 1192 dis_num_inst = 0; 1193} 1194 1195template <class Impl> 1196void 1197DefaultIEW<Impl>::printAvailableInsts() 1198{ 1199 int inst = 0; 1200 1201 std::cout << "Available Instructions: "; 1202 1203 while (fromIssue->insts[inst]) { 1204 1205 if (inst%3==0) std::cout << "\n\t"; 1206 1207 std::cout << "PC: " << fromIssue->insts[inst]->pcState() 1208 << " TN: " << fromIssue->insts[inst]->threadNumber 1209 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1210 1211 inst++; 1212 1213 } 1214 1215 std::cout << "\n"; 1216} 1217 1218template <class Impl> 1219void 1220DefaultIEW<Impl>::executeInsts() 1221{ 1222 wbNumInst = 0; 1223 wbCycle = 0; 1224 1225 list<ThreadID>::iterator threads = activeThreads->begin(); 1226 list<ThreadID>::iterator end = activeThreads->end(); 1227 1228 while (threads != end) { 1229 ThreadID tid = *threads++; 1230 fetchRedirect[tid] = false; 1231 } 1232 1233 // Uncomment this if you want to see all available instructions. 1234 // @todo This doesn't actually work anymore, we should fix it. 1235// printAvailableInsts(); 1236 1237 // Execute/writeback any instructions that are available. 1238 int insts_to_execute = fromIssue->size; 1239 int inst_num = 0; 1240 for (; inst_num < insts_to_execute; 1241 ++inst_num) { 1242 1243 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1244 1245 DynInstPtr inst = instQueue.getInstToExecute(); 1246 1247 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 1248 inst->pcState(), inst->threadNumber,inst->seqNum); 1249 1250 // Check if the instruction is squashed; if so then skip it 1251 if (inst->isSquashed()) { 1252 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 1253 " [sn:%i]\n", inst->pcState(), inst->threadNumber, 1254 inst->seqNum); 1255 1256 // Consider this instruction executed so that commit can go 1257 // ahead and retire the instruction. 1258 inst->setExecuted(); 1259 1260 // Not sure if I should set this here or just let commit try to 1261 // commit any squashed instructions. I like the latter a bit more. 1262 inst->setCanCommit(); 1263 1264 ++iewExecSquashedInsts; 1265 1266 decrWb(inst->seqNum); 1267 continue; 1268 } 1269 1270 Fault fault = NoFault; 1271 1272 // Execute instruction. 1273 // Note that if the instruction faults, it will be handled 1274 // at the commit stage. 1275 if (inst->isMemRef()) { 1276 DPRINTF(IEW, "Execute: Calculating address for memory " 1277 "reference.\n"); 1278 1279 // Tell the LDSTQ to execute this instruction (if it is a load). 1280 if (inst->isLoad()) { 1281 // Loads will mark themselves as executed, and their writeback 1282 // event adds the instruction to the queue to commit 1283 fault = ldstQueue.executeLoad(inst); 1284 1285 if (inst->isTranslationDelayed() && 1286 fault == NoFault) { 1287 // A hw page table walk is currently going on; the 1288 // instruction must be deferred. 1289 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1290 "load.\n"); 1291 instQueue.deferMemInst(inst); 1292 continue; 1293 } 1294 1295 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1296 inst->fault = NoFault; 1297 } 1298 } else if (inst->isStore()) { 1299 fault = ldstQueue.executeStore(inst); 1300 1301 if (inst->isTranslationDelayed() && 1302 fault == NoFault) { 1303 // A hw page table walk is currently going on; the 1304 // instruction must be deferred. 1305 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1306 "store.\n"); 1307 instQueue.deferMemInst(inst); 1308 continue; 1309 } 1310 1311 // If the store had a fault then it may not have a mem req 1312 if (fault != NoFault || !inst->readPredicate() || 1313 !inst->isStoreConditional()) { 1314 // If the instruction faulted, then we need to send it along 1315 // to commit without the instruction completing. 1316 // Send this instruction to commit, also make sure iew stage 1317 // realizes there is activity. 1318 inst->setExecuted(); 1319 instToCommit(inst); 1320 activityThisCycle(); 1321 } 1322 1323 // Store conditionals will mark themselves as 1324 // executed, and their writeback event will add the 1325 // instruction to the queue to commit. 1326 } else { 1327 panic("Unexpected memory type!\n"); 1328 } 1329 1330 } else { 1331 // If the instruction has already faulted, then skip executing it. 1332 // Such case can happen when it faulted during ITLB translation. 1333 // If we execute the instruction (even if it's a nop) the fault 1334 // will be replaced and we will lose it. 1335 if (inst->getFault() == NoFault) { 1336 inst->execute(); 1337 if (!inst->readPredicate()) 1338 inst->forwardOldRegs(); 1339 } 1340 1341 inst->setExecuted(); 1342 1343 instToCommit(inst); 1344 } 1345 1346 updateExeInstStats(inst); 1347 1348 // Check if branch prediction was correct, if not then we need 1349 // to tell commit to squash in flight instructions. Only 1350 // handle this if there hasn't already been something that 1351 // redirects fetch in this group of instructions. 1352 1353 // This probably needs to prioritize the redirects if a different 1354 // scheduler is used. Currently the scheduler schedules the oldest 1355 // instruction first, so the branch resolution order will be correct. 1356 ThreadID tid = inst->threadNumber; 1357 1358 if (!fetchRedirect[tid] || 1359 !toCommit->squash[tid] || 1360 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1361 1362 // Prevent testing for misprediction on load instructions, 1363 // that have not been executed. 1364 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1365 1366 if (inst->mispredicted() && !loadNotExecuted) { 1367 fetchRedirect[tid] = true; 1368 1369 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1370 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1371 inst->readPredTarg()); 1372 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1373 inst->pcState()); 1374 // If incorrect, then signal the ROB that it must be squashed. 1375 squashDueToBranch(inst, tid); 1376 1377 ppMispredict->notify(inst); 1378 1379 if (inst->readPredTaken()) { 1380 predictedTakenIncorrect++; 1381 } else { 1382 predictedNotTakenIncorrect++; 1383 } 1384 } else if (ldstQueue.violation(tid)) { 1385 assert(inst->isMemRef()); 1386 // If there was an ordering violation, then get the 1387 // DynInst that caused the violation. Note that this 1388 // clears the violation signal. 1389 DynInstPtr violator; 1390 violator = ldstQueue.getMemDepViolator(tid); 1391 1392 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1393 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1394 violator->pcState(), violator->seqNum, 1395 inst->pcState(), inst->seqNum, inst->physEffAddr); 1396 1397 fetchRedirect[tid] = true; 1398 1399 // Tell the instruction queue that a violation has occured. 1400 instQueue.violation(inst, violator); 1401 1402 // Squash. 1403 squashDueToMemOrder(violator, tid); 1404 1405 ++memOrderViolationEvents; 1406 } else if (ldstQueue.loadBlocked(tid) && 1407 !ldstQueue.isLoadBlockedHandled(tid)) { 1408 fetchRedirect[tid] = true; 1409 1410 DPRINTF(IEW, "Load operation couldn't execute because the " 1411 "memory system is blocked. PC: %s [sn:%lli]\n", 1412 inst->pcState(), inst->seqNum); 1413 1414 squashDueToMemBlocked(inst, tid); 1415 } 1416 } else { 1417 // Reset any state associated with redirects that will not 1418 // be used. 1419 if (ldstQueue.violation(tid)) { 1420 assert(inst->isMemRef()); 1421 1422 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1423 1424 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1425 "%s, inst PC: %s. Addr is: %#x.\n", 1426 violator->pcState(), inst->pcState(), 1427 inst->physEffAddr); 1428 DPRINTF(IEW, "Violation will not be handled because " 1429 "already squashing\n"); 1430 1431 ++memOrderViolationEvents; 1432 } 1433 if (ldstQueue.loadBlocked(tid) && 1434 !ldstQueue.isLoadBlockedHandled(tid)) { 1435 DPRINTF(IEW, "Load operation couldn't execute because the " 1436 "memory system is blocked. PC: %s [sn:%lli]\n", 1437 inst->pcState(), inst->seqNum); 1438 DPRINTF(IEW, "Blocked load will not be handled because " 1439 "already squashing\n"); 1440 1441 ldstQueue.setLoadBlockedHandled(tid); 1442 } 1443 1444 } 1445 } 1446 1447 // Update and record activity if we processed any instructions. 1448 if (inst_num) { 1449 if (exeStatus == Idle) { 1450 exeStatus = Running; 1451 } 1452 1453 updatedQueues = true; 1454 1455 cpu->activityThisCycle(); 1456 } 1457 1458 // Need to reset this in case a writeback event needs to write into the 1459 // iew queue. That way the writeback event will write into the correct 1460 // spot in the queue. 1461 wbNumInst = 0; 1462 1463} 1464 1465template <class Impl> 1466void 1467DefaultIEW<Impl>::writebackInsts() 1468{ 1469 // Loop through the head of the time buffer and wake any 1470 // dependents. These instructions are about to write back. Also 1471 // mark scoreboard that this instruction is finally complete. 1472 // Either have IEW have direct access to scoreboard, or have this 1473 // as part of backwards communication. 1474 for (int inst_num = 0; inst_num < wbWidth && 1475 toCommit->insts[inst_num]; inst_num++) { 1476 DynInstPtr inst = toCommit->insts[inst_num]; 1477 ThreadID tid = inst->threadNumber; 1478 1479 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1480 inst->seqNum, inst->pcState()); 1481 1482 iewInstsToCommit[tid]++; 1483 1484 // Some instructions will be sent to commit without having 1485 // executed because they need commit to handle them. 1486 // E.g. Uncached loads have not actually executed when they 1487 // are first sent to commit. Instead commit must tell the LSQ 1488 // when it's ready to execute the uncached load. 1489 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1490 int dependents = instQueue.wakeDependents(inst); 1491 1492 for (int i = 0; i < inst->numDestRegs(); i++) { 1493 //mark as Ready 1494 DPRINTF(IEW,"Setting Destination Register %i\n", 1495 inst->renamedDestRegIdx(i)); 1496 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1497 } 1498 1499 if (dependents) { 1500 producerInst[tid]++; 1501 consumerInst[tid]+= dependents; 1502 } 1503 writebackCount[tid]++; 1504 } 1505 1506 decrWb(inst->seqNum); 1507 } 1508} 1509 1510template<class Impl> 1511void 1512DefaultIEW<Impl>::tick() 1513{ 1514 wbNumInst = 0; 1515 wbCycle = 0; 1516 1517 wroteToTimeBuffer = false; 1518 updatedQueues = false; 1519 1520 sortInsts(); 1521 1522 // Free function units marked as being freed this cycle. 1523 fuPool->processFreeUnits(); 1524 1525 list<ThreadID>::iterator threads = activeThreads->begin(); 1526 list<ThreadID>::iterator end = activeThreads->end(); 1527 1528 // Check stall and squash signals, dispatch any instructions. 1529 while (threads != end) { 1530 ThreadID tid = *threads++; 1531 1532 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1533 1534 checkSignalsAndUpdate(tid); 1535 dispatch(tid); 1536 } 1537 1538 if (exeStatus != Squashing) { 1539 executeInsts(); 1540 1541 writebackInsts(); 1542 1543 // Have the instruction queue try to schedule any ready instructions. 1544 // (In actuality, this scheduling is for instructions that will 1545 // be executed next cycle.) 1546 instQueue.scheduleReadyInsts(); 1547 1548 // Also should advance its own time buffers if the stage ran. 1549 // Not the best place for it, but this works (hopefully). 1550 issueToExecQueue.advance(); 1551 } 1552 1553 bool broadcast_free_entries = false; 1554 1555 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1556 exeStatus = Idle; 1557 updateLSQNextCycle = false; 1558 1559 broadcast_free_entries = true; 1560 } 1561 1562 // Writeback any stores using any leftover bandwidth. 1563 ldstQueue.writebackStores(); 1564 1565 // Check the committed load/store signals to see if there's a load 1566 // or store to commit. Also check if it's being told to execute a 1567 // nonspeculative instruction. 1568 // This is pretty inefficient... 1569 1570 threads = activeThreads->begin(); 1571 while (threads != end) { 1572 ThreadID tid = (*threads++); 1573 1574 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1575 1576 // Update structures based on instructions committed. 1577 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1578 !fromCommit->commitInfo[tid].squash && 1579 !fromCommit->commitInfo[tid].robSquashing) { 1580 1581 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1582 1583 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1584 1585 updateLSQNextCycle = true; 1586 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1587 } 1588 1589 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1590 1591 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1592 if (fromCommit->commitInfo[tid].uncached) { 1593 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1594 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1595 } else { 1596 instQueue.scheduleNonSpec( 1597 fromCommit->commitInfo[tid].nonSpecSeqNum); 1598 } 1599 } 1600 1601 if (broadcast_free_entries) { 1602 toFetch->iewInfo[tid].iqCount = 1603 instQueue.getCount(tid); 1604 toFetch->iewInfo[tid].ldstqCount = 1605 ldstQueue.getCount(tid); 1606 1607 toRename->iewInfo[tid].usedIQ = true; 1608 toRename->iewInfo[tid].freeIQEntries = 1609 instQueue.numFreeEntries(tid); 1610 toRename->iewInfo[tid].usedLSQ = true; 1611 1612 toRename->iewInfo[tid].freeLQEntries = 1613 ldstQueue.numFreeLoadEntries(tid); 1614 toRename->iewInfo[tid].freeSQEntries = 1615 ldstQueue.numFreeStoreEntries(tid); 1616 1617 wroteToTimeBuffer = true; 1618 } 1619 1620 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1621 tid, toRename->iewInfo[tid].dispatched); 1622 } 1623 1624 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1625 "LQ has %i free entries. SQ has %i free entries.\n", 1626 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1627 ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 1628 1629 updateStatus(); 1630 1631 if (wroteToTimeBuffer) { 1632 DPRINTF(Activity, "Activity this cycle.\n"); 1633 cpu->activityThisCycle(); 1634 } 1635} 1636 1637template <class Impl> 1638void 1639DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1640{ 1641 ThreadID tid = inst->threadNumber; 1642 1643 iewExecutedInsts++; 1644 1645#if TRACING_ON 1646 if (DTRACE(O3PipeView)) { 1647 inst->completeTick = curTick() - inst->fetchTick; 1648 } 1649#endif 1650 1651 // 1652 // Control operations 1653 // 1654 if (inst->isControl()) 1655 iewExecutedBranches[tid]++; 1656 1657 // 1658 // Memory operations 1659 // 1660 if (inst->isMemRef()) { 1661 iewExecutedRefs[tid]++; 1662 1663 if (inst->isLoad()) { 1664 iewExecLoadInsts[tid]++; 1665 } 1666 } 1667} 1668 1669template <class Impl> 1670void 1671DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1672{ 1673 ThreadID tid = inst->threadNumber; 1674 1675 if (!fetchRedirect[tid] || 1676 !toCommit->squash[tid] || 1677 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1678 1679 if (inst->mispredicted()) { 1680 fetchRedirect[tid] = true; 1681 1682 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1683 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1684 inst->predInstAddr(), inst->predNextInstAddr()); 1685 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1686 " NPC: %#x.\n", inst->nextInstAddr(), 1687 inst->nextInstAddr()); 1688 // If incorrect, then signal the ROB that it must be squashed. 1689 squashDueToBranch(inst, tid); 1690 1691 if (inst->readPredTaken()) { 1692 predictedTakenIncorrect++; 1693 } else { 1694 predictedNotTakenIncorrect++; 1695 } 1696 } 1697 } 1698} 1699 1700#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1701