iew_impl.hh revision 9944
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461060SN/A// @todo: Fix the instantaneous communication among all the stages within 471060SN/A// iew. There's a clear delay between issue and execute, yet backwards 481689SN/A// communication happens simultaneously. 491060SN/A 501060SN/A#include <queue> 511060SN/A 528230Snate@binkert.org#include "arch/utility.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 552292SN/A#include "cpu/o3/fu_pool.hh" 561717SN/A#include "cpu/o3/iew.hh" 578229Snate@binkert.org#include "cpu/timebuf.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/IEW.hh" 619527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 625529Snate@binkert.org#include "params/DerivO3CPU.hh" 631060SN/A 646221Snate@binkert.orgusing namespace std; 656221Snate@binkert.org 661681SN/Atemplate<class Impl> 675529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 682873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 694329Sktlim@umich.edu cpu(_cpu), 704329Sktlim@umich.edu instQueue(_cpu, this, params), 714329Sktlim@umich.edu ldstQueue(_cpu, this, params), 722292SN/A fuPool(params->fuPool), 732292SN/A commitToIEWDelay(params->commitToIEWDelay), 742292SN/A renameToIEWDelay(params->renameToIEWDelay), 752292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 762820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 772292SN/A issueWidth(params->issueWidth), 782820Sktlim@umich.edu wbOutstanding(0), 792820Sktlim@umich.edu wbWidth(params->wbWidth), 809444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 811060SN/A{ 822292SN/A _status = Active; 832292SN/A exeStatus = Running; 842292SN/A wbStatus = Idle; 851060SN/A 861060SN/A // Setup wire to read instructions coming from issue. 871060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 881060SN/A 891060SN/A // Instruction queue needs the queue between issue and execute. 901060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 911681SN/A 926221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 936221Snate@binkert.org dispatchStatus[tid] = Running; 946221Snate@binkert.org stalls[tid].commit = false; 956221Snate@binkert.org fetchRedirect[tid] = false; 962292SN/A } 972292SN/A 982820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 992820Sktlim@umich.edu 1002292SN/A updateLSQNextCycle = false; 1012292SN/A 1022820Sktlim@umich.edu ableToIssue = true; 1032820Sktlim@umich.edu 1042292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1052292SN/A} 1062292SN/A 1072292SN/Atemplate <class Impl> 1082292SN/Astd::string 1092292SN/ADefaultIEW<Impl>::name() const 1102292SN/A{ 1112292SN/A return cpu->name() + ".iew"; 1121060SN/A} 1131060SN/A 1141681SN/Atemplate <class Impl> 1151062SN/Avoid 1162292SN/ADefaultIEW<Impl>::regStats() 1171062SN/A{ 1182301SN/A using namespace Stats; 1192301SN/A 1201062SN/A instQueue.regStats(); 1212727Sktlim@umich.edu ldstQueue.regStats(); 1221062SN/A 1231062SN/A iewIdleCycles 1241062SN/A .name(name() + ".iewIdleCycles") 1251062SN/A .desc("Number of cycles IEW is idle"); 1261062SN/A 1271062SN/A iewSquashCycles 1281062SN/A .name(name() + ".iewSquashCycles") 1291062SN/A .desc("Number of cycles IEW is squashing"); 1301062SN/A 1311062SN/A iewBlockCycles 1321062SN/A .name(name() + ".iewBlockCycles") 1331062SN/A .desc("Number of cycles IEW is blocking"); 1341062SN/A 1351062SN/A iewUnblockCycles 1361062SN/A .name(name() + ".iewUnblockCycles") 1371062SN/A .desc("Number of cycles IEW is unblocking"); 1381062SN/A 1391062SN/A iewDispatchedInsts 1401062SN/A .name(name() + ".iewDispatchedInsts") 1411062SN/A .desc("Number of instructions dispatched to IQ"); 1421062SN/A 1431062SN/A iewDispSquashedInsts 1441062SN/A .name(name() + ".iewDispSquashedInsts") 1451062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1461062SN/A 1471062SN/A iewDispLoadInsts 1481062SN/A .name(name() + ".iewDispLoadInsts") 1491062SN/A .desc("Number of dispatched load instructions"); 1501062SN/A 1511062SN/A iewDispStoreInsts 1521062SN/A .name(name() + ".iewDispStoreInsts") 1531062SN/A .desc("Number of dispatched store instructions"); 1541062SN/A 1551062SN/A iewDispNonSpecInsts 1561062SN/A .name(name() + ".iewDispNonSpecInsts") 1571062SN/A .desc("Number of dispatched non-speculative instructions"); 1581062SN/A 1591062SN/A iewIQFullEvents 1601062SN/A .name(name() + ".iewIQFullEvents") 1611062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1621062SN/A 1632292SN/A iewLSQFullEvents 1642292SN/A .name(name() + ".iewLSQFullEvents") 1652292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1662292SN/A 1671062SN/A memOrderViolationEvents 1681062SN/A .name(name() + ".memOrderViolationEvents") 1691062SN/A .desc("Number of memory order violations"); 1701062SN/A 1711062SN/A predictedTakenIncorrect 1721062SN/A .name(name() + ".predictedTakenIncorrect") 1731062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1742292SN/A 1752292SN/A predictedNotTakenIncorrect 1762292SN/A .name(name() + ".predictedNotTakenIncorrect") 1772292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1782292SN/A 1792292SN/A branchMispredicts 1802292SN/A .name(name() + ".branchMispredicts") 1812292SN/A .desc("Number of branch mispredicts detected at execute"); 1822292SN/A 1832292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1842301SN/A 1852727Sktlim@umich.edu iewExecutedInsts 1862353SN/A .name(name() + ".iewExecutedInsts") 1872727Sktlim@umich.edu .desc("Number of executed instructions"); 1882727Sktlim@umich.edu 1892727Sktlim@umich.edu iewExecLoadInsts 1906221Snate@binkert.org .init(cpu->numThreads) 1912353SN/A .name(name() + ".iewExecLoadInsts") 1922727Sktlim@umich.edu .desc("Number of load instructions executed") 1932727Sktlim@umich.edu .flags(total); 1942727Sktlim@umich.edu 1952727Sktlim@umich.edu iewExecSquashedInsts 1962353SN/A .name(name() + ".iewExecSquashedInsts") 1972727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1982727Sktlim@umich.edu 1992727Sktlim@umich.edu iewExecutedSwp 2006221Snate@binkert.org .init(cpu->numThreads) 2018240Snate@binkert.org .name(name() + ".exec_swp") 2022301SN/A .desc("number of swp insts executed") 2032727Sktlim@umich.edu .flags(total); 2042301SN/A 2052727Sktlim@umich.edu iewExecutedNop 2066221Snate@binkert.org .init(cpu->numThreads) 2078240Snate@binkert.org .name(name() + ".exec_nop") 2082301SN/A .desc("number of nop insts executed") 2092727Sktlim@umich.edu .flags(total); 2102301SN/A 2112727Sktlim@umich.edu iewExecutedRefs 2126221Snate@binkert.org .init(cpu->numThreads) 2138240Snate@binkert.org .name(name() + ".exec_refs") 2142301SN/A .desc("number of memory reference insts executed") 2152727Sktlim@umich.edu .flags(total); 2162301SN/A 2172727Sktlim@umich.edu iewExecutedBranches 2186221Snate@binkert.org .init(cpu->numThreads) 2198240Snate@binkert.org .name(name() + ".exec_branches") 2202301SN/A .desc("Number of branches executed") 2212727Sktlim@umich.edu .flags(total); 2222301SN/A 2232301SN/A iewExecStoreInsts 2248240Snate@binkert.org .name(name() + ".exec_stores") 2252301SN/A .desc("Number of stores executed") 2262727Sktlim@umich.edu .flags(total); 2272727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu iewExecRate 2308240Snate@binkert.org .name(name() + ".exec_rate") 2312727Sktlim@umich.edu .desc("Inst execution rate") 2322727Sktlim@umich.edu .flags(total); 2332727Sktlim@umich.edu 2342727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2352301SN/A 2362301SN/A iewInstsToCommit 2376221Snate@binkert.org .init(cpu->numThreads) 2388240Snate@binkert.org .name(name() + ".wb_sent") 2392301SN/A .desc("cumulative count of insts sent to commit") 2402727Sktlim@umich.edu .flags(total); 2412301SN/A 2422326SN/A writebackCount 2436221Snate@binkert.org .init(cpu->numThreads) 2448240Snate@binkert.org .name(name() + ".wb_count") 2452301SN/A .desc("cumulative count of insts written-back") 2462727Sktlim@umich.edu .flags(total); 2472301SN/A 2482326SN/A producerInst 2496221Snate@binkert.org .init(cpu->numThreads) 2508240Snate@binkert.org .name(name() + ".wb_producers") 2512301SN/A .desc("num instructions producing a value") 2522727Sktlim@umich.edu .flags(total); 2532301SN/A 2542326SN/A consumerInst 2556221Snate@binkert.org .init(cpu->numThreads) 2568240Snate@binkert.org .name(name() + ".wb_consumers") 2572301SN/A .desc("num instructions consuming a value") 2582727Sktlim@umich.edu .flags(total); 2592301SN/A 2602326SN/A wbPenalized 2616221Snate@binkert.org .init(cpu->numThreads) 2628240Snate@binkert.org .name(name() + ".wb_penalized") 2632301SN/A .desc("number of instrctions required to write to 'other' IQ") 2642727Sktlim@umich.edu .flags(total); 2652301SN/A 2662326SN/A wbPenalizedRate 2678240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2682301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2692727Sktlim@umich.edu .flags(total); 2702301SN/A 2712326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2722301SN/A 2732326SN/A wbFanout 2748240Snate@binkert.org .name(name() + ".wb_fanout") 2752301SN/A .desc("average fanout of values written-back") 2762727Sktlim@umich.edu .flags(total); 2772301SN/A 2782326SN/A wbFanout = producerInst / consumerInst; 2792301SN/A 2802326SN/A wbRate 2818240Snate@binkert.org .name(name() + ".wb_rate") 2822301SN/A .desc("insts written-back per cycle") 2832727Sktlim@umich.edu .flags(total); 2842326SN/A wbRate = writebackCount / cpu->numCycles; 2851062SN/A} 2861062SN/A 2871681SN/Atemplate<class Impl> 2881060SN/Avoid 2899427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 2901060SN/A{ 2916221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2922292SN/A toRename->iewInfo[tid].usedIQ = true; 2932292SN/A toRename->iewInfo[tid].freeIQEntries = 2942292SN/A instQueue.numFreeEntries(tid); 2952292SN/A 2962292SN/A toRename->iewInfo[tid].usedLSQ = true; 2972292SN/A toRename->iewInfo[tid].freeLSQEntries = 2982292SN/A ldstQueue.numFreeEntries(tid); 2992292SN/A } 3002292SN/A 3018887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3028733Sgeoffrey.blake@arm.com if (cpu->checker) { 3038850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3048887Sgeoffrey.blake@arm.com } 3058733Sgeoffrey.blake@arm.com 3062733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3071060SN/A} 3081060SN/A 3091681SN/Atemplate<class Impl> 3101060SN/Avoid 3112292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3121060SN/A{ 3131060SN/A timeBuffer = tb_ptr; 3141060SN/A 3151060SN/A // Setup wire to read information from time buffer, from commit. 3161060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3171060SN/A 3181060SN/A // Setup wire to write information back to previous stages. 3191060SN/A toRename = timeBuffer->getWire(0); 3201060SN/A 3212292SN/A toFetch = timeBuffer->getWire(0); 3222292SN/A 3231060SN/A // Instruction queue also needs main time buffer. 3241060SN/A instQueue.setTimeBuffer(tb_ptr); 3251060SN/A} 3261060SN/A 3271681SN/Atemplate<class Impl> 3281060SN/Avoid 3292292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3301060SN/A{ 3311060SN/A renameQueue = rq_ptr; 3321060SN/A 3331060SN/A // Setup wire to read information from rename queue. 3341060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3351060SN/A} 3361060SN/A 3371681SN/Atemplate<class Impl> 3381060SN/Avoid 3392292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3401060SN/A{ 3411060SN/A iewQueue = iq_ptr; 3421060SN/A 3431060SN/A // Setup wire to write instructions to commit. 3441060SN/A toCommit = iewQueue->getWire(0); 3451060SN/A} 3461060SN/A 3471681SN/Atemplate<class Impl> 3481060SN/Avoid 3496221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3501060SN/A{ 3512292SN/A activeThreads = at_ptr; 3522292SN/A 3532292SN/A ldstQueue.setActiveThreads(at_ptr); 3542292SN/A instQueue.setActiveThreads(at_ptr); 3551060SN/A} 3561060SN/A 3571681SN/Atemplate<class Impl> 3581060SN/Avoid 3592292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3601060SN/A{ 3612292SN/A scoreboard = sb_ptr; 3621060SN/A} 3631060SN/A 3642307SN/Atemplate <class Impl> 3652863Sktlim@umich.edubool 3669444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3672307SN/A{ 3689444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3699444SAndreas.Sandberg@ARM.com 3709444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3719444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3729444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3739444SAndreas.Sandberg@ARM.com drained = false; 3749444SAndreas.Sandberg@ARM.com } 3759444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3769444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3779444SAndreas.Sandberg@ARM.com drained = false; 3789444SAndreas.Sandberg@ARM.com } 3799444SAndreas.Sandberg@ARM.com } 3809444SAndreas.Sandberg@ARM.com 3819783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 3829783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 3839783Sandreas.hansson@arm.com // above 3849783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 3859783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 3869783Sandreas.hansson@arm.com drained = false; 3879783Sandreas.hansson@arm.com } 3889783Sandreas.hansson@arm.com 3899444SAndreas.Sandberg@ARM.com return drained; 3901681SN/A} 3911681SN/A 3922316SN/Atemplate <class Impl> 3931681SN/Avoid 3949444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 3952843Sktlim@umich.edu{ 3969444SAndreas.Sandberg@ARM.com assert(isDrained()); 3972843Sktlim@umich.edu 3989444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 3999444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4001681SN/A} 4011681SN/A 4022307SN/Atemplate <class Impl> 4031681SN/Avoid 4042307SN/ADefaultIEW<Impl>::takeOverFrom() 4051060SN/A{ 4062348SN/A // Reset all state. 4072307SN/A _status = Active; 4082307SN/A exeStatus = Running; 4092307SN/A wbStatus = Idle; 4101060SN/A 4112307SN/A instQueue.takeOverFrom(); 4122307SN/A ldstQueue.takeOverFrom(); 4139444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4141060SN/A 4159427SAndreas.Sandberg@ARM.com startupStage(); 4162307SN/A cpu->activityThisCycle(); 4171060SN/A 4186221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4196221Snate@binkert.org dispatchStatus[tid] = Running; 4206221Snate@binkert.org stalls[tid].commit = false; 4216221Snate@binkert.org fetchRedirect[tid] = false; 4222307SN/A } 4231060SN/A 4242307SN/A updateLSQNextCycle = false; 4252307SN/A 4262873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4272307SN/A issueToExecQueue.advance(); 4281060SN/A } 4291060SN/A} 4301060SN/A 4311681SN/Atemplate<class Impl> 4321060SN/Avoid 4336221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4342107SN/A{ 4356221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4362107SN/A 4372292SN/A // Tell the IQ to start squashing. 4382292SN/A instQueue.squash(tid); 4392107SN/A 4402292SN/A // Tell the LDSTQ to start squashing. 4412326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4422292SN/A updatedQueues = true; 4432107SN/A 4442292SN/A // Clear the skid buffer in case it has any data in it. 4452935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4464632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4472935Sksewell@umich.edu 4482292SN/A while (!skidBuffer[tid].empty()) { 4492292SN/A if (skidBuffer[tid].front()->isLoad() || 4502292SN/A skidBuffer[tid].front()->isStore() ) { 4512292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4522292SN/A } 4532107SN/A 4542292SN/A toRename->iewInfo[tid].dispatched++; 4552107SN/A 4562292SN/A skidBuffer[tid].pop(); 4572292SN/A } 4582107SN/A 4592702Sktlim@umich.edu emptyRenameInsts(tid); 4602107SN/A} 4612107SN/A 4622107SN/Atemplate<class Impl> 4632107SN/Avoid 4646221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4652292SN/A{ 4667720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4677720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4682292SN/A 4697852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4707852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4717852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4727852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4737852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4742935Sksewell@umich.edu 4757852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4767852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4772292SN/A 4787852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4797852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4807852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4812292SN/A 4827852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4837852SMatt.Horsnell@arm.com } 4847852SMatt.Horsnell@arm.com 4852292SN/A} 4862292SN/A 4872292SN/Atemplate<class Impl> 4882292SN/Avoid 4896221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4902292SN/A{ 4918513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 4928513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4938513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 4948513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 4958513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 4968513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 4978513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 4988513SGiacomo.Gabrielli@arm.com // the squash. 4998513SGiacomo.Gabrielli@arm.com if (toCommit->squash[tid] == false || 5008513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5018513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5022292SN/A 5037852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5048513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5058137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5062292SN/A 5078513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5088513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5092292SN/A 5107852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5117852SMatt.Horsnell@arm.com } 5122292SN/A} 5132292SN/A 5142292SN/Atemplate<class Impl> 5152292SN/Avoid 5166221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5172292SN/A{ 5182292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5197720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5207852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5217852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5227852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5232292SN/A 5247852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5257852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5268137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5272292SN/A 5287852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5297852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5302292SN/A 5317852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5322292SN/A 5337852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5347852SMatt.Horsnell@arm.com } 5352292SN/A} 5362292SN/A 5372292SN/Atemplate<class Impl> 5382292SN/Avoid 5396221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5402292SN/A{ 5412292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5422292SN/A 5432292SN/A if (dispatchStatus[tid] != Blocked && 5442292SN/A dispatchStatus[tid] != Unblocking) { 5452292SN/A toRename->iewBlock[tid] = true; 5462292SN/A wroteToTimeBuffer = true; 5472292SN/A } 5482292SN/A 5492292SN/A // Add the current inputs to the skid buffer so they can be 5502292SN/A // reprocessed when this stage unblocks. 5512292SN/A skidInsert(tid); 5522292SN/A 5532292SN/A dispatchStatus[tid] = Blocked; 5542292SN/A} 5552292SN/A 5562292SN/Atemplate<class Impl> 5572292SN/Avoid 5586221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5592292SN/A{ 5602292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5612292SN/A "buffer %u.\n",tid, tid); 5622292SN/A 5632292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5642292SN/A // Also switch status to running. 5652292SN/A if (skidBuffer[tid].empty()) { 5662292SN/A toRename->iewUnblock[tid] = true; 5672292SN/A wroteToTimeBuffer = true; 5682292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5692292SN/A dispatchStatus[tid] = Running; 5702292SN/A } 5712292SN/A} 5722292SN/A 5732292SN/Atemplate<class Impl> 5742292SN/Avoid 5752292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5761060SN/A{ 5771681SN/A instQueue.wakeDependents(inst); 5781060SN/A} 5791060SN/A 5802292SN/Atemplate<class Impl> 5812292SN/Avoid 5822292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5832292SN/A{ 5842292SN/A instQueue.rescheduleMemInst(inst); 5852292SN/A} 5861681SN/A 5871681SN/Atemplate<class Impl> 5881060SN/Avoid 5892292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5901060SN/A{ 5912292SN/A instQueue.replayMemInst(inst); 5922292SN/A} 5931060SN/A 5942292SN/Atemplate<class Impl> 5952292SN/Avoid 5962292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5972292SN/A{ 5983221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5993221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6003221Sktlim@umich.edu // being added to the queue to commit without being processed by 6013221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6023221Sktlim@umich.edu 6032292SN/A // First check the time slot that this instruction will write 6042292SN/A // to. If there are free write ports at the time, then go ahead 6052292SN/A // and write the instruction to that time. If there are not, 6062292SN/A // keep looking back to see where's the first time there's a 6072326SN/A // free slot. 6082292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6092292SN/A ++wbNumInst; 6102820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6112292SN/A ++wbCycle; 6122292SN/A wbNumInst = 0; 6132292SN/A } 6142292SN/A 6152353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6162292SN/A } 6172292SN/A 6182353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6192353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6202292SN/A // Add finished instruction to queue to commit. 6212292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6222292SN/A (*iewQueue)[wbCycle].size++; 6232292SN/A} 6242292SN/A 6252292SN/Atemplate <class Impl> 6262292SN/Aunsigned 6272292SN/ADefaultIEW<Impl>::validInstsFromRename() 6282292SN/A{ 6292292SN/A unsigned inst_count = 0; 6302292SN/A 6312292SN/A for (int i=0; i<fromRename->size; i++) { 6322731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6332292SN/A inst_count++; 6342292SN/A } 6352292SN/A 6362292SN/A return inst_count; 6372292SN/A} 6382292SN/A 6392292SN/Atemplate<class Impl> 6402292SN/Avoid 6416221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6422292SN/A{ 6432292SN/A DynInstPtr inst = NULL; 6442292SN/A 6452292SN/A while (!insts[tid].empty()) { 6462292SN/A inst = insts[tid].front(); 6472292SN/A 6482292SN/A insts[tid].pop(); 6492292SN/A 6509937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6512292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6527720Sgblack@eecs.umich.edu inst->pcState(),tid); 6532292SN/A 6542292SN/A skidBuffer[tid].push(inst); 6552292SN/A } 6562292SN/A 6572292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6582292SN/A "Skidbuffer Exceeded Max Size"); 6592292SN/A} 6602292SN/A 6612292SN/Atemplate<class Impl> 6622292SN/Aint 6632292SN/ADefaultIEW<Impl>::skidCount() 6642292SN/A{ 6652292SN/A int max=0; 6662292SN/A 6676221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6686221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6692292SN/A 6703867Sbinkertn@umich.edu while (threads != end) { 6716221Snate@binkert.org ThreadID tid = *threads++; 6723867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6732292SN/A if (max < thread_count) 6742292SN/A max = thread_count; 6752292SN/A } 6762292SN/A 6772292SN/A return max; 6782292SN/A} 6792292SN/A 6802292SN/Atemplate<class Impl> 6812292SN/Abool 6822292SN/ADefaultIEW<Impl>::skidsEmpty() 6832292SN/A{ 6846221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6856221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6862292SN/A 6873867Sbinkertn@umich.edu while (threads != end) { 6886221Snate@binkert.org ThreadID tid = *threads++; 6893867Sbinkertn@umich.edu 6903867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6912292SN/A return false; 6922292SN/A } 6932292SN/A 6942292SN/A return true; 6951062SN/A} 6961062SN/A 6971681SN/Atemplate <class Impl> 6981062SN/Avoid 6992292SN/ADefaultIEW<Impl>::updateStatus() 7001062SN/A{ 7012292SN/A bool any_unblocking = false; 7021062SN/A 7036221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7046221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7051062SN/A 7063867Sbinkertn@umich.edu while (threads != end) { 7076221Snate@binkert.org ThreadID tid = *threads++; 7081062SN/A 7092292SN/A if (dispatchStatus[tid] == Unblocking) { 7102292SN/A any_unblocking = true; 7112292SN/A break; 7122292SN/A } 7132292SN/A } 7141062SN/A 7152292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7162292SN/A // and there's no stores waiting to write back, and dispatch is not 7172292SN/A // unblocking, then there is no internal activity for the IEW stage. 7187897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7192292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7202292SN/A !ldstQueue.willWB() && !any_unblocking) { 7212292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7221062SN/A 7232292SN/A deactivateStage(); 7241062SN/A 7252292SN/A _status = Inactive; 7262292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7272292SN/A ldstQueue.willWB() || 7282292SN/A any_unblocking)) { 7292292SN/A // Otherwise there is internal activity. Set to active. 7302292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7311062SN/A 7322292SN/A activateStage(); 7331062SN/A 7342292SN/A _status = Active; 7351062SN/A } 7361062SN/A} 7371062SN/A 7381681SN/Atemplate <class Impl> 7391062SN/Avoid 7402292SN/ADefaultIEW<Impl>::resetEntries() 7411062SN/A{ 7422292SN/A instQueue.resetEntries(); 7432292SN/A ldstQueue.resetEntries(); 7442292SN/A} 7451062SN/A 7462292SN/Atemplate <class Impl> 7472292SN/Avoid 7486221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7492292SN/A{ 7502292SN/A if (fromCommit->commitBlock[tid]) { 7512292SN/A stalls[tid].commit = true; 7522292SN/A } 7531062SN/A 7542292SN/A if (fromCommit->commitUnblock[tid]) { 7552292SN/A assert(stalls[tid].commit); 7562292SN/A stalls[tid].commit = false; 7572292SN/A } 7582292SN/A} 7592292SN/A 7602292SN/Atemplate <class Impl> 7612292SN/Abool 7626221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7632292SN/A{ 7642292SN/A bool ret_val(false); 7652292SN/A 7662292SN/A if (stalls[tid].commit) { 7672292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7682292SN/A ret_val = true; 7692292SN/A } else if (instQueue.isFull(tid)) { 7702292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7712292SN/A ret_val = true; 7722292SN/A } else if (ldstQueue.isFull(tid)) { 7732292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7742292SN/A 7752292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7762292SN/A 7772292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7782292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7792292SN/A } 7802292SN/A 7812292SN/A if (ldstQueue.numStores(tid) > 0) { 7822292SN/A 7832292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7842292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7852292SN/A } 7862292SN/A 7872292SN/A ret_val = true; 7882292SN/A } else if (ldstQueue.isStalled(tid)) { 7892292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7902292SN/A ret_val = true; 7912292SN/A } 7922292SN/A 7932292SN/A return ret_val; 7942292SN/A} 7952292SN/A 7962292SN/Atemplate <class Impl> 7972292SN/Avoid 7986221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7992292SN/A{ 8002292SN/A // Check if there's a squash signal, squash if there is 8012292SN/A // Check stall signals, block if there is. 8022292SN/A // If status was Blocked 8032292SN/A // if so then go to unblocking 8042292SN/A // If status was Squashing 8052292SN/A // check if squashing is not high. Switch to running this cycle. 8062292SN/A 8072292SN/A readStallSignals(tid); 8082292SN/A 8092292SN/A if (fromCommit->commitInfo[tid].squash) { 8102292SN/A squash(tid); 8112292SN/A 8122292SN/A if (dispatchStatus[tid] == Blocked || 8132292SN/A dispatchStatus[tid] == Unblocking) { 8142292SN/A toRename->iewUnblock[tid] = true; 8152292SN/A wroteToTimeBuffer = true; 8162292SN/A } 8172292SN/A 8182292SN/A dispatchStatus[tid] = Squashing; 8192292SN/A fetchRedirect[tid] = false; 8202292SN/A return; 8212292SN/A } 8222292SN/A 8232292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8242702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8252292SN/A 8262292SN/A dispatchStatus[tid] = Squashing; 8272702Sktlim@umich.edu emptyRenameInsts(tid); 8282702Sktlim@umich.edu wroteToTimeBuffer = true; 8292292SN/A return; 8302292SN/A } 8312292SN/A 8322292SN/A if (checkStall(tid)) { 8332292SN/A block(tid); 8342292SN/A dispatchStatus[tid] = Blocked; 8352292SN/A return; 8362292SN/A } 8372292SN/A 8382292SN/A if (dispatchStatus[tid] == Blocked) { 8392292SN/A // Status from previous cycle was blocked, but there are no more stall 8402292SN/A // conditions. Switch over to unblocking. 8412292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8422292SN/A tid); 8432292SN/A 8442292SN/A dispatchStatus[tid] = Unblocking; 8452292SN/A 8462292SN/A unblock(tid); 8472292SN/A 8482292SN/A return; 8492292SN/A } 8502292SN/A 8512292SN/A if (dispatchStatus[tid] == Squashing) { 8522292SN/A // Switch status to running if rename isn't being told to block or 8532292SN/A // squash this cycle. 8542292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8552292SN/A tid); 8562292SN/A 8572292SN/A dispatchStatus[tid] = Running; 8582292SN/A 8592292SN/A return; 8602292SN/A } 8612292SN/A} 8622292SN/A 8632292SN/Atemplate <class Impl> 8642292SN/Avoid 8652292SN/ADefaultIEW<Impl>::sortInsts() 8662292SN/A{ 8672292SN/A int insts_from_rename = fromRename->size; 8682326SN/A#ifdef DEBUG 8696221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8706221Snate@binkert.org assert(insts[tid].empty()); 8712326SN/A#endif 8722292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8732292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8742292SN/A } 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Avoid 8796221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8802702Sktlim@umich.edu{ 8814632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8822935Sksewell@umich.edu 8832702Sktlim@umich.edu while (!insts[tid].empty()) { 8842935Sksewell@umich.edu 8852702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8862702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8872702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8882702Sktlim@umich.edu } 8892702Sktlim@umich.edu 8902702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8912702Sktlim@umich.edu 8922702Sktlim@umich.edu insts[tid].pop(); 8932702Sktlim@umich.edu } 8942702Sktlim@umich.edu} 8952702Sktlim@umich.edu 8962702Sktlim@umich.edutemplate <class Impl> 8972702Sktlim@umich.eduvoid 8982292SN/ADefaultIEW<Impl>::wakeCPU() 8992292SN/A{ 9002292SN/A cpu->wakeCPU(); 9012292SN/A} 9022292SN/A 9032292SN/Atemplate <class Impl> 9042292SN/Avoid 9052292SN/ADefaultIEW<Impl>::activityThisCycle() 9062292SN/A{ 9072292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9082292SN/A cpu->activityThisCycle(); 9092292SN/A} 9102292SN/A 9112292SN/Atemplate <class Impl> 9122292SN/Ainline void 9132292SN/ADefaultIEW<Impl>::activateStage() 9142292SN/A{ 9152292SN/A DPRINTF(Activity, "Activating stage.\n"); 9162733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9172292SN/A} 9182292SN/A 9192292SN/Atemplate <class Impl> 9202292SN/Ainline void 9212292SN/ADefaultIEW<Impl>::deactivateStage() 9222292SN/A{ 9232292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9242733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9252292SN/A} 9262292SN/A 9272292SN/Atemplate<class Impl> 9282292SN/Avoid 9296221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9302292SN/A{ 9312292SN/A // If status is Running or idle, 9322292SN/A // call dispatchInsts() 9332292SN/A // If status is Unblocking, 9342292SN/A // buffer any instructions coming from rename 9352292SN/A // continue trying to empty skid buffer 9362292SN/A // check if stall conditions have passed 9372292SN/A 9382292SN/A if (dispatchStatus[tid] == Blocked) { 9392292SN/A ++iewBlockCycles; 9402292SN/A 9412292SN/A } else if (dispatchStatus[tid] == Squashing) { 9422292SN/A ++iewSquashCycles; 9432292SN/A } 9442292SN/A 9452292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9462292SN/A // will allow, as long as it is not currently blocked. 9472292SN/A if (dispatchStatus[tid] == Running || 9482292SN/A dispatchStatus[tid] == Idle) { 9492292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9502292SN/A "dispatch.\n", tid); 9512292SN/A 9522292SN/A dispatchInsts(tid); 9532292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9542292SN/A // Make sure that the skid buffer has something in it if the 9552292SN/A // status is unblocking. 9562292SN/A assert(!skidsEmpty()); 9572292SN/A 9582292SN/A // If the status was unblocking, then instructions from the skid 9592292SN/A // buffer were used. Remove those instructions and handle 9602292SN/A // the rest of unblocking. 9612292SN/A dispatchInsts(tid); 9622292SN/A 9632292SN/A ++iewUnblockCycles; 9642292SN/A 9655215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9662292SN/A // Add the current inputs to the skid buffer so they can be 9672292SN/A // reprocessed when this stage unblocks. 9682292SN/A skidInsert(tid); 9692292SN/A } 9702292SN/A 9712292SN/A unblock(tid); 9722292SN/A } 9732292SN/A} 9742292SN/A 9752292SN/Atemplate <class Impl> 9762292SN/Avoid 9776221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9782292SN/A{ 9792292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9802292SN/A // otherwise. 9812292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9822292SN/A dispatchStatus[tid] == Unblocking ? 9832292SN/A skidBuffer[tid] : insts[tid]; 9842292SN/A 9852292SN/A int insts_to_add = insts_to_dispatch.size(); 9862292SN/A 9872292SN/A DynInstPtr inst; 9882292SN/A bool add_to_iq = false; 9892292SN/A int dis_num_inst = 0; 9902292SN/A 9912292SN/A // Loop through the instructions, putting them in the instruction 9922292SN/A // queue. 9932292SN/A for ( ; dis_num_inst < insts_to_add && 9942820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9952292SN/A ++dis_num_inst) 9962292SN/A { 9972292SN/A inst = insts_to_dispatch.front(); 9982292SN/A 9992292SN/A if (dispatchStatus[tid] == Unblocking) { 10002292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10012292SN/A "buffer\n", tid); 10022292SN/A } 10032292SN/A 10042292SN/A // Make sure there's a valid instruction there. 10052292SN/A assert(inst); 10062292SN/A 10077720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10082292SN/A "IQ.\n", 10097720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10102292SN/A 10112292SN/A // Be sure to mark these instructions as ready so that the 10122292SN/A // commit stage can go ahead and execute them, and mark 10132292SN/A // them as issued so the IQ doesn't reprocess them. 10142292SN/A 10152292SN/A // Check for squashed instructions. 10162292SN/A if (inst->isSquashed()) { 10172292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10182292SN/A "not adding to IQ.\n", tid); 10192292SN/A 10202292SN/A ++iewDispSquashedInsts; 10212292SN/A 10222292SN/A insts_to_dispatch.pop(); 10232292SN/A 10242292SN/A //Tell Rename That An Instruction has been processed 10252292SN/A if (inst->isLoad() || inst->isStore()) { 10262292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10272292SN/A } 10282292SN/A toRename->iewInfo[tid].dispatched++; 10292292SN/A 10302292SN/A continue; 10312292SN/A } 10322292SN/A 10332292SN/A // Check for full conditions. 10342292SN/A if (instQueue.isFull(tid)) { 10352292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10362292SN/A 10372292SN/A // Call function to start blocking. 10382292SN/A block(tid); 10392292SN/A 10402292SN/A // Set unblock to false. Special case where we are using 10412292SN/A // skidbuffer (unblocking) instructions but then we still 10422292SN/A // get full in the IQ. 10432292SN/A toRename->iewUnblock[tid] = false; 10442292SN/A 10452292SN/A ++iewIQFullEvents; 10462292SN/A break; 10472292SN/A } else if (ldstQueue.isFull(tid)) { 10482292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10492292SN/A 10502292SN/A // Call function to start blocking. 10512292SN/A block(tid); 10522292SN/A 10532292SN/A // Set unblock to false. Special case where we are using 10542292SN/A // skidbuffer (unblocking) instructions but then we still 10552292SN/A // get full in the IQ. 10562292SN/A toRename->iewUnblock[tid] = false; 10572292SN/A 10582292SN/A ++iewLSQFullEvents; 10592292SN/A break; 10602292SN/A } 10612292SN/A 10622292SN/A // Otherwise issue the instruction just fine. 10632292SN/A if (inst->isLoad()) { 10642292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10652292SN/A "encountered, adding to LSQ.\n", tid); 10662292SN/A 10672292SN/A // Reserve a spot in the load store queue for this 10682292SN/A // memory access. 10692292SN/A ldstQueue.insertLoad(inst); 10702292SN/A 10712292SN/A ++iewDispLoadInsts; 10722292SN/A 10732292SN/A add_to_iq = true; 10742292SN/A 10752292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10762292SN/A } else if (inst->isStore()) { 10772292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10782292SN/A "encountered, adding to LSQ.\n", tid); 10792292SN/A 10802292SN/A ldstQueue.insertStore(inst); 10812292SN/A 10822292SN/A ++iewDispStoreInsts; 10832292SN/A 10842336SN/A if (inst->isStoreConditional()) { 10852336SN/A // Store conditionals need to be set as "canCommit()" 10862336SN/A // so that commit can process them when they reach the 10872336SN/A // head of commit. 10882348SN/A // @todo: This is somewhat specific to Alpha. 10892292SN/A inst->setCanCommit(); 10902292SN/A instQueue.insertNonSpec(inst); 10912292SN/A add_to_iq = false; 10922292SN/A 10932292SN/A ++iewDispNonSpecInsts; 10942292SN/A } else { 10952292SN/A add_to_iq = true; 10962292SN/A } 10972292SN/A 10982292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10992292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11002326SN/A // Same as non-speculative stores. 11012292SN/A inst->setCanCommit(); 11022292SN/A instQueue.insertBarrier(inst); 11032292SN/A add_to_iq = false; 11042292SN/A } else if (inst->isNop()) { 11052292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11062292SN/A "skipping.\n", tid); 11072292SN/A 11082292SN/A inst->setIssued(); 11092292SN/A inst->setExecuted(); 11102292SN/A inst->setCanCommit(); 11112292SN/A 11122326SN/A instQueue.recordProducer(inst); 11132292SN/A 11142727Sktlim@umich.edu iewExecutedNop[tid]++; 11152301SN/A 11162292SN/A add_to_iq = false; 11172292SN/A } else if (inst->isExecuted()) { 11182292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11192292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11202292SN/A "skipping.\n"); 11212292SN/A 11222292SN/A inst->setIssued(); 11232292SN/A inst->setCanCommit(); 11242292SN/A 11252326SN/A instQueue.recordProducer(inst); 11262292SN/A 11272292SN/A add_to_iq = false; 11282292SN/A } else { 11292292SN/A add_to_iq = true; 11302292SN/A } 11314033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11324033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11334033Sktlim@umich.edu "encountered, skipping.\n", tid); 11344033Sktlim@umich.edu 11354033Sktlim@umich.edu // Same as non-speculative stores. 11364033Sktlim@umich.edu inst->setCanCommit(); 11374033Sktlim@umich.edu 11384033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11394033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11404033Sktlim@umich.edu 11414033Sktlim@umich.edu ++iewDispNonSpecInsts; 11424033Sktlim@umich.edu 11434033Sktlim@umich.edu add_to_iq = false; 11444033Sktlim@umich.edu } 11452292SN/A 11462292SN/A // If the instruction queue is not full, then add the 11472292SN/A // instruction. 11482292SN/A if (add_to_iq) { 11492292SN/A instQueue.insert(inst); 11502292SN/A } 11512292SN/A 11522292SN/A insts_to_dispatch.pop(); 11532292SN/A 11542292SN/A toRename->iewInfo[tid].dispatched++; 11552292SN/A 11562292SN/A ++iewDispatchedInsts; 11578471SGiacomo.Gabrielli@arm.com 11588471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11599046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11608471SGiacomo.Gabrielli@arm.com#endif 11612292SN/A } 11622292SN/A 11632292SN/A if (!insts_to_dispatch.empty()) { 11642935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11652292SN/A block(tid); 11662292SN/A toRename->iewUnblock[tid] = false; 11672292SN/A } 11682292SN/A 11692292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11702292SN/A dispatchStatus[tid] = Running; 11712292SN/A 11722292SN/A updatedQueues = true; 11732292SN/A } 11742292SN/A 11752292SN/A dis_num_inst = 0; 11762292SN/A} 11772292SN/A 11782292SN/Atemplate <class Impl> 11792292SN/Avoid 11802292SN/ADefaultIEW<Impl>::printAvailableInsts() 11812292SN/A{ 11822292SN/A int inst = 0; 11832292SN/A 11842980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11852292SN/A 11862292SN/A while (fromIssue->insts[inst]) { 11872292SN/A 11882980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11892292SN/A 11907720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11912292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11922292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11932292SN/A 11942292SN/A inst++; 11952292SN/A 11962292SN/A } 11972292SN/A 11982980Sgblack@eecs.umich.edu std::cout << "\n"; 11992292SN/A} 12002292SN/A 12012292SN/Atemplate <class Impl> 12022292SN/Avoid 12032292SN/ADefaultIEW<Impl>::executeInsts() 12042292SN/A{ 12052292SN/A wbNumInst = 0; 12062292SN/A wbCycle = 0; 12072292SN/A 12086221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12096221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12102292SN/A 12113867Sbinkertn@umich.edu while (threads != end) { 12126221Snate@binkert.org ThreadID tid = *threads++; 12132292SN/A fetchRedirect[tid] = false; 12142292SN/A } 12152292SN/A 12162698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12177599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12182698Sktlim@umich.edu// printAvailableInsts(); 12191062SN/A 12201062SN/A // Execute/writeback any instructions that are available. 12212333SN/A int insts_to_execute = fromIssue->size; 12222292SN/A int inst_num = 0; 12232333SN/A for (; inst_num < insts_to_execute; 12242326SN/A ++inst_num) { 12251062SN/A 12262292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12271062SN/A 12282333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12291062SN/A 12307720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12317720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12321062SN/A 12331062SN/A // Check if the instruction is squashed; if so then skip it 12341062SN/A if (inst->isSquashed()) { 12358315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12368315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12378315Sgeoffrey.blake@arm.com inst->seqNum); 12381062SN/A 12391062SN/A // Consider this instruction executed so that commit can go 12401062SN/A // ahead and retire the instruction. 12411062SN/A inst->setExecuted(); 12421062SN/A 12432292SN/A // Not sure if I should set this here or just let commit try to 12442292SN/A // commit any squashed instructions. I like the latter a bit more. 12452292SN/A inst->setCanCommit(); 12461062SN/A 12471062SN/A ++iewExecSquashedInsts; 12481062SN/A 12492820Sktlim@umich.edu decrWb(inst->seqNum); 12501062SN/A continue; 12511062SN/A } 12521062SN/A 12532292SN/A Fault fault = NoFault; 12541062SN/A 12551062SN/A // Execute instruction. 12561062SN/A // Note that if the instruction faults, it will be handled 12571062SN/A // at the commit stage. 12587850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12592292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12601062SN/A "reference.\n"); 12611062SN/A 12621062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12631062SN/A if (inst->isLoad()) { 12642292SN/A // Loads will mark themselves as executed, and their writeback 12652292SN/A // event adds the instruction to the queue to commit 12662292SN/A fault = ldstQueue.executeLoad(inst); 12677944SGiacomo.Gabrielli@arm.com 12687944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12697944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12707944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12717944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12727944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12737944SGiacomo.Gabrielli@arm.com "load.\n"); 12747944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12757944SGiacomo.Gabrielli@arm.com continue; 12767944SGiacomo.Gabrielli@arm.com } 12777944SGiacomo.Gabrielli@arm.com 12787850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12798073SAli.Saidi@ARM.com inst->fault = NoFault; 12807850SMatt.Horsnell@arm.com } 12811062SN/A } else if (inst->isStore()) { 12822367SN/A fault = ldstQueue.executeStore(inst); 12831062SN/A 12847944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12857944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12867944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12877944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12887944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12897944SGiacomo.Gabrielli@arm.com "store.\n"); 12907944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12917944SGiacomo.Gabrielli@arm.com continue; 12927944SGiacomo.Gabrielli@arm.com } 12937944SGiacomo.Gabrielli@arm.com 12942292SN/A // If the store had a fault then it may not have a mem req 12957782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12967782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12977782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12987782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12992367SN/A // Send this instruction to commit, also make sure iew stage 13002367SN/A // realizes there is activity. 13012367SN/A inst->setExecuted(); 13022367SN/A instToCommit(inst); 13032367SN/A activityThisCycle(); 13042292SN/A } 13052326SN/A 13062326SN/A // Store conditionals will mark themselves as 13072326SN/A // executed, and their writeback event will add the 13082326SN/A // instruction to the queue to commit. 13091062SN/A } else { 13102292SN/A panic("Unexpected memory type!\n"); 13111062SN/A } 13121062SN/A 13131062SN/A } else { 13147847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13157847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13167847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13177847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13187847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13197847Sminkyu.jeong@arm.com inst->execute(); 13207848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 13217848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13227847Sminkyu.jeong@arm.com } 13231062SN/A 13242292SN/A inst->setExecuted(); 13252292SN/A 13262292SN/A instToCommit(inst); 13271062SN/A } 13281062SN/A 13292301SN/A updateExeInstStats(inst); 13301681SN/A 13312326SN/A // Check if branch prediction was correct, if not then we need 13322326SN/A // to tell commit to squash in flight instructions. Only 13332326SN/A // handle this if there hasn't already been something that 13342107SN/A // redirects fetch in this group of instructions. 13351681SN/A 13362292SN/A // This probably needs to prioritize the redirects if a different 13372292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13382292SN/A // instruction first, so the branch resolution order will be correct. 13396221Snate@binkert.org ThreadID tid = inst->threadNumber; 13401062SN/A 13413732Sktlim@umich.edu if (!fetchRedirect[tid] || 13427852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13433732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13441062SN/A 13457856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13467856SMatt.Horsnell@arm.com // that have not been executed. 13477856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13487856SMatt.Horsnell@arm.com 13497856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13502292SN/A fetchRedirect[tid] = true; 13511062SN/A 13522292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13538674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13548674Snilay@cs.wisc.edu inst->readPredTarg()); 13557720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13568674Snilay@cs.wisc.edu inst->pcState()); 13571062SN/A // If incorrect, then signal the ROB that it must be squashed. 13582292SN/A squashDueToBranch(inst, tid); 13591062SN/A 13603795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13611062SN/A predictedTakenIncorrect++; 13622292SN/A } else { 13632292SN/A predictedNotTakenIncorrect++; 13641062SN/A } 13652292SN/A } else if (ldstQueue.violation(tid)) { 13664033Sktlim@umich.edu assert(inst->isMemRef()); 13672326SN/A // If there was an ordering violation, then get the 13682326SN/A // DynInst that caused the violation. Note that this 13692292SN/A // clears the violation signal. 13702292SN/A DynInstPtr violator; 13712292SN/A violator = ldstQueue.getMemDepViolator(tid); 13721062SN/A 13737720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13747720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13757720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13767720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13777720Sgblack@eecs.umich.edu 13783732Sktlim@umich.edu fetchRedirect[tid] = true; 13793732Sktlim@umich.edu 13801062SN/A // Tell the instruction queue that a violation has occured. 13811062SN/A instQueue.violation(inst, violator); 13821062SN/A 13831062SN/A // Squash. 13848513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13851062SN/A 13861062SN/A ++memOrderViolationEvents; 13872292SN/A } else if (ldstQueue.loadBlocked(tid) && 13882292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13892292SN/A fetchRedirect[tid] = true; 13902292SN/A 13912292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13927720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13937720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13942292SN/A 13952292SN/A squashDueToMemBlocked(inst, tid); 13961062SN/A } 13974033Sktlim@umich.edu } else { 13984033Sktlim@umich.edu // Reset any state associated with redirects that will not 13994033Sktlim@umich.edu // be used. 14004033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14014033Sktlim@umich.edu assert(inst->isMemRef()); 14024033Sktlim@umich.edu 14034033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14044033Sktlim@umich.edu 14054033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14067720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14077720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14087720Sgblack@eecs.umich.edu inst->physEffAddr); 14094033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14104033Sktlim@umich.edu "already squashing\n"); 14114033Sktlim@umich.edu 14124033Sktlim@umich.edu ++memOrderViolationEvents; 14134033Sktlim@umich.edu } 14144033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14154033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14164033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14177720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14187720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14194033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14204033Sktlim@umich.edu "already squashing\n"); 14214033Sktlim@umich.edu 14224033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14234033Sktlim@umich.edu } 14244033Sktlim@umich.edu 14251062SN/A } 14261062SN/A } 14272292SN/A 14282348SN/A // Update and record activity if we processed any instructions. 14292292SN/A if (inst_num) { 14302292SN/A if (exeStatus == Idle) { 14312292SN/A exeStatus = Running; 14322292SN/A } 14332292SN/A 14342292SN/A updatedQueues = true; 14352292SN/A 14362292SN/A cpu->activityThisCycle(); 14372292SN/A } 14382292SN/A 14392292SN/A // Need to reset this in case a writeback event needs to write into the 14402292SN/A // iew queue. That way the writeback event will write into the correct 14412292SN/A // spot in the queue. 14422292SN/A wbNumInst = 0; 14437852SMatt.Horsnell@arm.com 14442107SN/A} 14452107SN/A 14462292SN/Atemplate <class Impl> 14472107SN/Avoid 14482292SN/ADefaultIEW<Impl>::writebackInsts() 14492107SN/A{ 14502326SN/A // Loop through the head of the time buffer and wake any 14512326SN/A // dependents. These instructions are about to write back. Also 14522326SN/A // mark scoreboard that this instruction is finally complete. 14532326SN/A // Either have IEW have direct access to scoreboard, or have this 14542326SN/A // as part of backwards communication. 14553958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14562292SN/A toCommit->insts[inst_num]; inst_num++) { 14572107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14586221Snate@binkert.org ThreadID tid = inst->threadNumber; 14592107SN/A 14607720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14617720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14622107SN/A 14632301SN/A iewInstsToCommit[tid]++; 14642301SN/A 14652292SN/A // Some instructions will be sent to commit without having 14662292SN/A // executed because they need commit to handle them. 14672292SN/A // E.g. Uncached loads have not actually executed when they 14682292SN/A // are first sent to commit. Instead commit must tell the LSQ 14692292SN/A // when it's ready to execute the uncached load. 14702367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14712301SN/A int dependents = instQueue.wakeDependents(inst); 14722107SN/A 14732292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14742292SN/A //mark as Ready 14752292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14762292SN/A inst->renamedDestRegIdx(i)); 14772292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14782107SN/A } 14792301SN/A 14802348SN/A if (dependents) { 14812348SN/A producerInst[tid]++; 14822348SN/A consumerInst[tid]+= dependents; 14832348SN/A } 14842326SN/A writebackCount[tid]++; 14852107SN/A } 14862820Sktlim@umich.edu 14872820Sktlim@umich.edu decrWb(inst->seqNum); 14882107SN/A } 14891060SN/A} 14901060SN/A 14911681SN/Atemplate<class Impl> 14921060SN/Avoid 14932292SN/ADefaultIEW<Impl>::tick() 14941060SN/A{ 14952292SN/A wbNumInst = 0; 14962292SN/A wbCycle = 0; 14971060SN/A 14982292SN/A wroteToTimeBuffer = false; 14992292SN/A updatedQueues = false; 15001060SN/A 15012292SN/A sortInsts(); 15021060SN/A 15032326SN/A // Free function units marked as being freed this cycle. 15042326SN/A fuPool->processFreeUnits(); 15051062SN/A 15066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15076221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15081060SN/A 15092326SN/A // Check stall and squash signals, dispatch any instructions. 15103867Sbinkertn@umich.edu while (threads != end) { 15116221Snate@binkert.org ThreadID tid = *threads++; 15121060SN/A 15132292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15141060SN/A 15152292SN/A checkSignalsAndUpdate(tid); 15162292SN/A dispatch(tid); 15171060SN/A } 15181060SN/A 15192292SN/A if (exeStatus != Squashing) { 15202292SN/A executeInsts(); 15211060SN/A 15222292SN/A writebackInsts(); 15232292SN/A 15242292SN/A // Have the instruction queue try to schedule any ready instructions. 15252292SN/A // (In actuality, this scheduling is for instructions that will 15262292SN/A // be executed next cycle.) 15272292SN/A instQueue.scheduleReadyInsts(); 15282292SN/A 15292292SN/A // Also should advance its own time buffers if the stage ran. 15302292SN/A // Not the best place for it, but this works (hopefully). 15312292SN/A issueToExecQueue.advance(); 15322292SN/A } 15332292SN/A 15342292SN/A bool broadcast_free_entries = false; 15352292SN/A 15362292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15372292SN/A exeStatus = Idle; 15382292SN/A updateLSQNextCycle = false; 15392292SN/A 15402292SN/A broadcast_free_entries = true; 15412292SN/A } 15422292SN/A 15432292SN/A // Writeback any stores using any leftover bandwidth. 15441681SN/A ldstQueue.writebackStores(); 15451681SN/A 15461061SN/A // Check the committed load/store signals to see if there's a load 15471061SN/A // or store to commit. Also check if it's being told to execute a 15481061SN/A // nonspeculative instruction. 15491681SN/A // This is pretty inefficient... 15502292SN/A 15513867Sbinkertn@umich.edu threads = activeThreads->begin(); 15523867Sbinkertn@umich.edu while (threads != end) { 15536221Snate@binkert.org ThreadID tid = (*threads++); 15542292SN/A 15552292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15562292SN/A 15572348SN/A // Update structures based on instructions committed. 15582292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15592292SN/A !fromCommit->commitInfo[tid].squash && 15602292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15612292SN/A 15622292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15632292SN/A 15642292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15652292SN/A 15662292SN/A updateLSQNextCycle = true; 15672292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15682292SN/A } 15692292SN/A 15702292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15712292SN/A 15722292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15732292SN/A if (fromCommit->commitInfo[tid].uncached) { 15742292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15754033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15762292SN/A } else { 15772292SN/A instQueue.scheduleNonSpec( 15782292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15792292SN/A } 15802292SN/A } 15812292SN/A 15822292SN/A if (broadcast_free_entries) { 15832292SN/A toFetch->iewInfo[tid].iqCount = 15842292SN/A instQueue.getCount(tid); 15852292SN/A toFetch->iewInfo[tid].ldstqCount = 15862292SN/A ldstQueue.getCount(tid); 15872292SN/A 15882292SN/A toRename->iewInfo[tid].usedIQ = true; 15892292SN/A toRename->iewInfo[tid].freeIQEntries = 15902292SN/A instQueue.numFreeEntries(); 15912292SN/A toRename->iewInfo[tid].usedLSQ = true; 15922292SN/A toRename->iewInfo[tid].freeLSQEntries = 15932292SN/A ldstQueue.numFreeEntries(tid); 15942292SN/A 15952292SN/A wroteToTimeBuffer = true; 15962292SN/A } 15972292SN/A 15982292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15992292SN/A tid, toRename->iewInfo[tid].dispatched); 16001061SN/A } 16011061SN/A 16022292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 16032292SN/A "LSQ has %i free entries.\n", 16042292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 16052292SN/A ldstQueue.numFreeEntries()); 16062292SN/A 16072292SN/A updateStatus(); 16082292SN/A 16092292SN/A if (wroteToTimeBuffer) { 16102292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16112292SN/A cpu->activityThisCycle(); 16121061SN/A } 16131060SN/A} 16141060SN/A 16152301SN/Atemplate <class Impl> 16161060SN/Avoid 16172301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16181060SN/A{ 16196221Snate@binkert.org ThreadID tid = inst->threadNumber; 16201060SN/A 16212669Sktlim@umich.edu iewExecutedInsts++; 16221060SN/A 16238471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16249527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16259527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16269527SMatt.Horsnell@arm.com } 16278471SGiacomo.Gabrielli@arm.com#endif 16288471SGiacomo.Gabrielli@arm.com 16292301SN/A // 16302301SN/A // Control operations 16312301SN/A // 16322301SN/A if (inst->isControl()) 16336221Snate@binkert.org iewExecutedBranches[tid]++; 16341060SN/A 16352301SN/A // 16362301SN/A // Memory operations 16372301SN/A // 16382301SN/A if (inst->isMemRef()) { 16396221Snate@binkert.org iewExecutedRefs[tid]++; 16401060SN/A 16412301SN/A if (inst->isLoad()) { 16426221Snate@binkert.org iewExecLoadInsts[tid]++; 16431060SN/A } 16441060SN/A } 16451060SN/A} 16467598Sminkyu.jeong@arm.com 16477598Sminkyu.jeong@arm.comtemplate <class Impl> 16487598Sminkyu.jeong@arm.comvoid 16497598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16507598Sminkyu.jeong@arm.com{ 16517598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16527598Sminkyu.jeong@arm.com 16537598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16547852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16557598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16567598Sminkyu.jeong@arm.com 16577598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16587598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16597598Sminkyu.jeong@arm.com 16607598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16617598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16627720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16637598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16647720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16657720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16667598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16677598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16687598Sminkyu.jeong@arm.com 16697598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16707598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16717598Sminkyu.jeong@arm.com } else { 16727598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16737598Sminkyu.jeong@arm.com } 16747598Sminkyu.jeong@arm.com } 16757598Sminkyu.jeong@arm.com } 16767598Sminkyu.jeong@arm.com} 16779944Smatt.horsnell@ARM.com 16789944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1679