iew_impl.hh revision 8471
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010 ARM Limited 310239Sbinhpham@cs.rutgers.edu * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 147598Sminkyu.jeong@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 152326SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412665Ssaidi@eecs.umich.edu */ 421689SN/A 431689SN/A// @todo: Fix the instantaneous communication among all the stages within 449944Smatt.horsnell@ARM.com// iew. There's a clear delay between issue and execute, yet backwards 459944Smatt.horsnell@ARM.com// communication happens simultaneously. 469944Smatt.horsnell@ARM.com 471060SN/A#include <queue> 481060SN/A 491689SN/A#include "arch/utility.hh" 501060SN/A#include "config/the_isa.hh" 511060SN/A#include "cpu/o3/fu_pool.hh" 521060SN/A#include "cpu/o3/iew.hh" 538230Snate@binkert.org#include "cpu/timebuf.hh" 546658Snate@binkert.org#include "debug/Activity.hh" 558887Sgeoffrey.blake@arm.com#include "debug/Decode.hh" 562292SN/A#include "debug/IEW.hh" 571717SN/A#include "params/DerivO3CPU.hh" 588229Snate@binkert.org 598232Snate@binkert.orgusing namespace std; 609444SAndreas.Sandberg@ARM.com 618232Snate@binkert.orgtemplate<class Impl> 629527SMatt.Horsnell@arm.comDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 635529Snate@binkert.org : issueToExecQueue(params->backComSize, params->forwardComSize), 641060SN/A cpu(_cpu), 656221Snate@binkert.org instQueue(_cpu, this, params), 666221Snate@binkert.org ldstQueue(_cpu, this, params), 671681SN/A fuPool(params->fuPool), 685529Snate@binkert.org commitToIEWDelay(params->commitToIEWDelay), 692873Sktlim@umich.edu renameToIEWDelay(params->renameToIEWDelay), 704329Sktlim@umich.edu issueToExecuteDelay(params->issueToExecuteDelay), 714329Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 724329Sktlim@umich.edu issueWidth(params->issueWidth), 732292SN/A wbOutstanding(0), 742292SN/A wbWidth(params->wbWidth), 752292SN/A numThreads(params->numThreads), 762292SN/A switchedOut(false) 772820Sktlim@umich.edu{ 782292SN/A _status = Active; 7913453Srekai.gonzalezalberquilla@arm.com exeStatus = Running; 8013453Srekai.gonzalezalberquilla@arm.com wbStatus = Idle; 812820Sktlim@umich.edu 829444SAndreas.Sandberg@ARM.com // Setup wire to read instructions coming from issue. 831060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 8410172Sdam.sunwoo@arm.com 8510172Sdam.sunwoo@arm.com // Instruction queue needs the queue between issue and execute. 8610172Sdam.sunwoo@arm.com instQueue.setIssueToExecuteQueue(&issueToExecQueue); 8710172Sdam.sunwoo@arm.com 8810172Sdam.sunwoo@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 8910172Sdam.sunwoo@arm.com dispatchStatus[tid] = Running; 9010172Sdam.sunwoo@arm.com stalls[tid].commit = false; 9110172Sdam.sunwoo@arm.com fetchRedirect[tid] = false; 9210172Sdam.sunwoo@arm.com } 9310172Sdam.sunwoo@arm.com 9410172Sdam.sunwoo@arm.com wbMax = wbWidth * params->wbDepth; 9510172Sdam.sunwoo@arm.com 9610172Sdam.sunwoo@arm.com updateLSQNextCycle = false; 972292SN/A 982292SN/A ableToIssue = true; 992292SN/A 1001060SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1011060SN/A} 1021060SN/A 1031060SN/Atemplate <class Impl> 1041060SN/Astd::string 1051060SN/ADefaultIEW<Impl>::name() const 1061681SN/A{ 10713453Srekai.gonzalezalberquilla@arm.com return cpu->name() + ".iew"; 1086221Snate@binkert.org} 1096221Snate@binkert.org 1102292SN/Atemplate <class Impl> 1112292SN/Avoid 1122292SN/ADefaultIEW<Impl>::regStats() 1132292SN/A{ 11410328Smitch.hayenga@arm.com using namespace Stats; 1152292SN/A 1162292SN/A instQueue.regStats(); 1172292SN/A ldstQueue.regStats(); 1182292SN/A 1192292SN/A iewIdleCycles 1202292SN/A .name(name() + ".iewIdleCycles") 1212292SN/A .desc("Number of cycles IEW is idle"); 1221060SN/A 1231060SN/A iewSquashCycles 1241681SN/A .name(name() + ".iewSquashCycles") 1251062SN/A .desc("Number of cycles IEW is squashing"); 12610023Smatt.horsnell@ARM.com 12710023Smatt.horsnell@ARM.com iewBlockCycles 12810023Smatt.horsnell@ARM.com .name(name() + ".iewBlockCycles") 12910023Smatt.horsnell@ARM.com .desc("Number of cycles IEW is blocking"); 13011246Sradhika.jagtap@ARM.com 13111246Sradhika.jagtap@ARM.com iewUnblockCycles 13211246Sradhika.jagtap@ARM.com .name(name() + ".iewUnblockCycles") 13311246Sradhika.jagtap@ARM.com .desc("Number of cycles IEW is unblocking"); 13411246Sradhika.jagtap@ARM.com 13511246Sradhika.jagtap@ARM.com iewDispatchedInsts 13611246Sradhika.jagtap@ARM.com .name(name() + ".iewDispatchedInsts") 13711246Sradhika.jagtap@ARM.com .desc("Number of instructions dispatched to IQ"); 13811246Sradhika.jagtap@ARM.com 13911246Sradhika.jagtap@ARM.com iewDispSquashedInsts 14011246Sradhika.jagtap@ARM.com .name(name() + ".iewDispSquashedInsts") 14111246Sradhika.jagtap@ARM.com .desc("Number of squashed instructions skipped by dispatch"); 14210023Smatt.horsnell@ARM.com 14310023Smatt.horsnell@ARM.com iewDispLoadInsts 14410023Smatt.horsnell@ARM.com .name(name() + ".iewDispLoadInsts") 14510023Smatt.horsnell@ARM.com .desc("Number of dispatched load instructions"); 1462292SN/A 1471062SN/A iewDispStoreInsts 1482301SN/A .name(name() + ".iewDispStoreInsts") 1492301SN/A .desc("Number of dispatched store instructions"); 1501062SN/A 1512727Sktlim@umich.edu iewDispNonSpecInsts 1521062SN/A .name(name() + ".iewDispNonSpecInsts") 1531062SN/A .desc("Number of dispatched non-speculative instructions"); 1541062SN/A 1551062SN/A iewIQFullEvents 1561062SN/A .name(name() + ".iewIQFullEvents") 1571062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1581062SN/A 1591062SN/A iewLSQFullEvents 1601062SN/A .name(name() + ".iewLSQFullEvents") 1611062SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1621062SN/A 1631062SN/A memOrderViolationEvents 1641062SN/A .name(name() + ".memOrderViolationEvents") 1651062SN/A .desc("Number of memory order violations"); 1661062SN/A 1671062SN/A predictedTakenIncorrect 1681062SN/A .name(name() + ".predictedTakenIncorrect") 1691062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1701062SN/A 1711062SN/A predictedNotTakenIncorrect 1721062SN/A .name(name() + ".predictedNotTakenIncorrect") 1731062SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1741062SN/A 1751062SN/A branchMispredicts 1761062SN/A .name(name() + ".branchMispredicts") 1771062SN/A .desc("Number of branch mispredicts detected at execute"); 1781062SN/A 1791062SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1801062SN/A 1811062SN/A iewExecutedInsts 1821062SN/A .name(name() + ".iewExecutedInsts") 1831062SN/A .desc("Number of executed instructions"); 1841062SN/A 1851062SN/A iewExecLoadInsts 1861062SN/A .init(cpu->numThreads) 1871062SN/A .name(name() + ".iewExecLoadInsts") 1881062SN/A .desc("Number of load instructions executed") 1891062SN/A .flags(total); 1901062SN/A 1911062SN/A iewExecSquashedInsts 1921062SN/A .name(name() + ".iewExecSquashedInsts") 1932292SN/A .desc("Number of squashed instructions skipped in execute"); 1942292SN/A 1952292SN/A iewExecutedSwp 1962292SN/A .init(cpu->numThreads) 1971062SN/A .name(name() + ".exec_swp") 1981062SN/A .desc("number of swp insts executed") 1991062SN/A .flags(total); 2001062SN/A 2011062SN/A iewExecutedNop 2021062SN/A .init(cpu->numThreads) 2031062SN/A .name(name() + ".exec_nop") 2042292SN/A .desc("number of nop insts executed") 2052292SN/A .flags(total); 2062292SN/A 2072292SN/A iewExecutedRefs 2082292SN/A .init(cpu->numThreads) 2092292SN/A .name(name() + ".exec_refs") 2102292SN/A .desc("number of memory reference insts executed") 2112292SN/A .flags(total); 2122292SN/A 2132292SN/A iewExecutedBranches 2142301SN/A .init(cpu->numThreads) 2152727Sktlim@umich.edu .name(name() + ".exec_branches") 2162353SN/A .desc("Number of branches executed") 2172727Sktlim@umich.edu .flags(total); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu iewExecStoreInsts 2206221Snate@binkert.org .name(name() + ".exec_stores") 2212353SN/A .desc("Number of stores executed") 2222727Sktlim@umich.edu .flags(total); 2232727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecRate 2262353SN/A .name(name() + ".exec_rate") 2272727Sktlim@umich.edu .desc("Inst execution rate") 2282727Sktlim@umich.edu .flags(total); 2292727Sktlim@umich.edu 2306221Snate@binkert.org iewExecRate = iewExecutedInsts / cpu->numCycles; 2318240Snate@binkert.org 2322301SN/A iewInstsToCommit 2332727Sktlim@umich.edu .init(cpu->numThreads) 2342301SN/A .name(name() + ".wb_sent") 2352727Sktlim@umich.edu .desc("cumulative count of insts sent to commit") 2366221Snate@binkert.org .flags(total); 2378240Snate@binkert.org 2382301SN/A writebackCount 2392727Sktlim@umich.edu .init(cpu->numThreads) 2402301SN/A .name(name() + ".wb_count") 2412727Sktlim@umich.edu .desc("cumulative count of insts written-back") 2426221Snate@binkert.org .flags(total); 2438240Snate@binkert.org 2442301SN/A producerInst 2452727Sktlim@umich.edu .init(cpu->numThreads) 2462301SN/A .name(name() + ".wb_producers") 2472727Sktlim@umich.edu .desc("num instructions producing a value") 2486221Snate@binkert.org .flags(total); 2498240Snate@binkert.org 2502301SN/A consumerInst 2512727Sktlim@umich.edu .init(cpu->numThreads) 2522301SN/A .name(name() + ".wb_consumers") 2532301SN/A .desc("num instructions consuming a value") 2548240Snate@binkert.org .flags(total); 2552301SN/A 2562727Sktlim@umich.edu wbPenalized 2572727Sktlim@umich.edu .init(cpu->numThreads) 2582727Sktlim@umich.edu .name(name() + ".wb_penalized") 2592727Sktlim@umich.edu .desc("number of instrctions required to write to 'other' IQ") 2608240Snate@binkert.org .flags(total); 2612727Sktlim@umich.edu 2622727Sktlim@umich.edu wbPenalizedRate 2632727Sktlim@umich.edu .name(name() + ".wb_penalized_rate") 2642727Sktlim@umich.edu .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2652301SN/A .flags(total); 2662301SN/A 2676221Snate@binkert.org wbPenalizedRate = wbPenalized / writebackCount; 2688240Snate@binkert.org 2692301SN/A wbFanout 2702727Sktlim@umich.edu .name(name() + ".wb_fanout") 2712301SN/A .desc("average fanout of values written-back") 2722326SN/A .flags(total); 2736221Snate@binkert.org 2748240Snate@binkert.org wbFanout = producerInst / consumerInst; 2752301SN/A 2762727Sktlim@umich.edu wbRate 2772301SN/A .name(name() + ".wb_rate") 2782326SN/A .desc("insts written-back per cycle") 2796221Snate@binkert.org .flags(total); 2808240Snate@binkert.org wbRate = writebackCount / cpu->numCycles; 2812301SN/A} 2822727Sktlim@umich.edu 2832301SN/Atemplate<class Impl> 2842326SN/Avoid 2856221Snate@binkert.orgDefaultIEW<Impl>::initStage() 2868240Snate@binkert.org{ 2872301SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2882727Sktlim@umich.edu toRename->iewInfo[tid].usedIQ = true; 2892301SN/A toRename->iewInfo[tid].freeIQEntries = 2902326SN/A instQueue.numFreeEntries(tid); 2918240Snate@binkert.org 2922301SN/A toRename->iewInfo[tid].usedLSQ = true; 2932727Sktlim@umich.edu toRename->iewInfo[tid].freeLSQEntries = 2942301SN/A ldstQueue.numFreeEntries(tid); 2952326SN/A } 2962301SN/A 2972326SN/A cpu->activateStage(O3CPU::IEWIdx); 2988240Snate@binkert.org} 2992301SN/A 3002727Sktlim@umich.edutemplate<class Impl> 3012326SN/Avoid 3021062SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3031062SN/A{ 3041681SN/A timeBuffer = tb_ptr; 3051060SN/A 3069427SAndreas.Sandberg@ARM.com // Setup wire to read information from time buffer, from commit. 3071060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3086221Snate@binkert.org 3092292SN/A // Setup wire to write information back to previous stages. 3102292SN/A toRename = timeBuffer->getWire(0); 3112292SN/A 3122292SN/A toFetch = timeBuffer->getWire(0); 3132292SN/A 31410239Sbinhpham@cs.rutgers.edu // Instruction queue also needs main time buffer. 31510239Sbinhpham@cs.rutgers.edu instQueue.setTimeBuffer(tb_ptr); 3162292SN/A} 3172292SN/A 3188887Sgeoffrey.blake@arm.comtemplate<class Impl> 3198733Sgeoffrey.blake@arm.comvoid 3208850Sandreas.hansson@arm.comDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3218887Sgeoffrey.blake@arm.com{ 3228733Sgeoffrey.blake@arm.com renameQueue = rq_ptr; 3232733Sktlim@umich.edu 3241060SN/A // Setup wire to read information from rename queue. 3251060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3261681SN/A} 3271060SN/A 3282292SN/Atemplate<class Impl> 3291060SN/Avoid 3301060SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3311060SN/A{ 3321060SN/A iewQueue = iq_ptr; 3331060SN/A 3341060SN/A // Setup wire to write instructions to commit. 3351060SN/A toCommit = iewQueue->getWire(0); 3361060SN/A} 3371060SN/A 3382292SN/Atemplate<class Impl> 3392292SN/Avoid 3401060SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3411060SN/A{ 3421060SN/A activeThreads = at_ptr; 3431060SN/A 3441681SN/A ldstQueue.setActiveThreads(at_ptr); 3451060SN/A instQueue.setActiveThreads(at_ptr); 3462292SN/A} 3471060SN/A 3481060SN/Atemplate<class Impl> 3491060SN/Avoid 3501060SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3511060SN/A{ 3521060SN/A scoreboard = sb_ptr; 3531060SN/A} 3541681SN/A 3551060SN/Atemplate <class Impl> 3562292SN/Abool 3571060SN/ADefaultIEW<Impl>::drain() 3581060SN/A{ 3591060SN/A // IEW is ready to drain at any time. 3601060SN/A cpu->signalDrained(); 3611060SN/A return true; 3621060SN/A} 3631060SN/A 3641681SN/Atemplate <class Impl> 3651060SN/Avoid 3666221Snate@binkert.orgDefaultIEW<Impl>::resume() 3671060SN/A{ 3682292SN/A} 3692292SN/A 3702292SN/Atemplate <class Impl> 3712292SN/Avoid 3721060SN/ADefaultIEW<Impl>::switchOut() 3731060SN/A{ 3741681SN/A // Clear any state. 3751060SN/A switchedOut = true; 3762292SN/A assert(insts[0].empty()); 3771060SN/A assert(skidBuffer[0].empty()); 3782292SN/A 3791060SN/A instQueue.switchOut(); 3801060SN/A ldstQueue.switchOut(); 3812307SN/A fuPool->switchOut(); 3822863Sktlim@umich.edu 3839444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3842307SN/A while (!insts[tid].empty()) 38510510Smitch.hayenga@arm.com insts[tid].pop(); 3869444SAndreas.Sandberg@ARM.com while (!skidBuffer[tid].empty()) 3879444SAndreas.Sandberg@ARM.com skidBuffer[tid].pop(); 3889444SAndreas.Sandberg@ARM.com } 3899444SAndreas.Sandberg@ARM.com} 3909444SAndreas.Sandberg@ARM.com 3919444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3929444SAndreas.Sandberg@ARM.comvoid 3939444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::takeOverFrom() 3949444SAndreas.Sandberg@ARM.com{ 3959444SAndreas.Sandberg@ARM.com // Reset all state. 39611650Srekai.gonzalezalberquilla@arm.com _status = Active; 3979444SAndreas.Sandberg@ARM.com exeStatus = Running; 3989444SAndreas.Sandberg@ARM.com wbStatus = Idle; 3999783Sandreas.hansson@arm.com switchedOut = false; 4009783Sandreas.hansson@arm.com 4019783Sandreas.hansson@arm.com instQueue.takeOverFrom(); 4029783Sandreas.hansson@arm.com ldstQueue.takeOverFrom(); 4039783Sandreas.hansson@arm.com fuPool->takeOverFrom(); 4049783Sandreas.hansson@arm.com 4059783Sandreas.hansson@arm.com initStage(); 4069783Sandreas.hansson@arm.com cpu->activityThisCycle(); 4079444SAndreas.Sandberg@ARM.com 4081681SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4091681SN/A dispatchStatus[tid] = Running; 4102316SN/A stalls[tid].commit = false; 4111681SN/A fetchRedirect[tid] = false; 4129444SAndreas.Sandberg@ARM.com } 4132843Sktlim@umich.edu 4149444SAndreas.Sandberg@ARM.com updateLSQNextCycle = false; 4152843Sktlim@umich.edu 4169444SAndreas.Sandberg@ARM.com for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4179444SAndreas.Sandberg@ARM.com issueToExecQueue.advance(); 4181681SN/A } 4191681SN/A} 4202307SN/A 4211681SN/Atemplate<class Impl> 4222307SN/Avoid 4231060SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4242348SN/A{ 4252307SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4262307SN/A 4272307SN/A // Tell the IQ to start squashing. 4281060SN/A instQueue.squash(tid); 4292307SN/A 4302307SN/A // Tell the LDSTQ to start squashing. 4319444SAndreas.Sandberg@ARM.com ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4321060SN/A updatedQueues = true; 4339427SAndreas.Sandberg@ARM.com 4342307SN/A // Clear the skid buffer in case it has any data in it. 4351060SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4366221Snate@binkert.org tid, fromCommit->commitInfo[tid].doneSeqNum); 4376221Snate@binkert.org 4386221Snate@binkert.org while (!skidBuffer[tid].empty()) { 4392307SN/A if (skidBuffer[tid].front()->isLoad() || 4401060SN/A skidBuffer[tid].front()->isStore() ) { 4412307SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4422307SN/A } 4432873Sktlim@umich.edu 4442307SN/A toRename->iewInfo[tid].dispatched++; 4451060SN/A 4461060SN/A skidBuffer[tid].pop(); 4471060SN/A } 4481681SN/A 4491060SN/A emptyRenameInsts(tid); 4506221Snate@binkert.org} 4512107SN/A 4526221Snate@binkert.orgtemplate<class Impl> 4532107SN/Avoid 4542292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4552292SN/A{ 4562107SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4572292SN/A "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4582326SN/A 4592292SN/A if (toCommit->squash[tid] == false || 4602107SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4612292SN/A toCommit->squash[tid] = true; 4622935Sksewell@umich.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 4634632Sgblack@eecs.umich.edu toCommit->branchTaken[tid] = inst->pcState().branching(); 4642935Sksewell@umich.edu 4652292SN/A TheISA::PCState pc = inst->pcState(); 46610239Sbinhpham@cs.rutgers.edu TheISA::advancePC(pc, inst->staticInst); 46710239Sbinhpham@cs.rutgers.edu 46810239Sbinhpham@cs.rutgers.edu toCommit->pc[tid] = pc; 46910239Sbinhpham@cs.rutgers.edu toCommit->mispredictInst[tid] = inst; 47010239Sbinhpham@cs.rutgers.edu toCommit->includeSquashInst[tid] = false; 4712292SN/A 4722107SN/A wroteToTimeBuffer = true; 4732292SN/A } 4742107SN/A 4752292SN/A} 4762292SN/A 4772107SN/Atemplate<class Impl> 4782702Sktlim@umich.eduvoid 4792107SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4802107SN/A{ 4812107SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4822107SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 48313429Srekai.gonzalezalberquilla@arm.com 4842292SN/A if (toCommit->squash[tid] == false || 4857720Sgblack@eecs.umich.edu inst->seqNum < toCommit->squashedSeqNum[tid]) { 4867720Sgblack@eecs.umich.edu toCommit->squash[tid] = true; 4872292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 48810231Ssteve.reinhardt@amd.com TheISA::PCState pc; 4897852SMatt.Horsnell@arm.com if (inst->isMemRef() && inst->isIndirectCtrl()) { 4907852SMatt.Horsnell@arm.com // If an operation is a control operation as well as a memory 4917852SMatt.Horsnell@arm.com // reference we need to use the predicted PC, not the PC+N 4927852SMatt.Horsnell@arm.com // This instruction will verify misprediction based on predPC 4932935Sksewell@umich.edu pc = inst->readPredTarg(); 4947852SMatt.Horsnell@arm.com } else { 4957852SMatt.Horsnell@arm.com pc = inst->pcState(); 4962292SN/A TheISA::advancePC(pc, inst->staticInst); 4977852SMatt.Horsnell@arm.com } 4987852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4997852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = NULL; 5002292SN/A 5017852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5027852SMatt.Horsnell@arm.com 5037852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5042292SN/A } 5052292SN/A} 5062292SN/A 5072292SN/Atemplate<class Impl> 50813429Srekai.gonzalezalberquilla@arm.comvoid 5092292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5108513SGiacomo.Gabrielli@arm.com{ 5118513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5128513SGiacomo.Gabrielli@arm.com "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5138513SGiacomo.Gabrielli@arm.com if (toCommit->squash[tid] == false || 5148513SGiacomo.Gabrielli@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5158513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5168513SGiacomo.Gabrielli@arm.com 5178513SGiacomo.Gabrielli@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 51810231Ssteve.reinhardt@amd.com toCommit->pc[tid] = inst->pcState(); 5198513SGiacomo.Gabrielli@arm.com toCommit->mispredictInst[tid] = NULL; 5208513SGiacomo.Gabrielli@arm.com 5212292SN/A // Must include the broadcasted SN in the squash. 5227852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5238513SGiacomo.Gabrielli@arm.com 5248137SAli.Saidi@ARM.com ldstQueue.setLoadBlockedHandled(tid); 5252292SN/A 5268513SGiacomo.Gabrielli@arm.com wroteToTimeBuffer = true; 5278513SGiacomo.Gabrielli@arm.com } 5282292SN/A} 5297852SMatt.Horsnell@arm.com 5307852SMatt.Horsnell@arm.comtemplate<class Impl> 5312292SN/Avoid 5322292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5332292SN/A{ 5342292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5356221Snate@binkert.org 5362292SN/A if (dispatchStatus[tid] != Blocked && 5372292SN/A dispatchStatus[tid] != Unblocking) { 5382292SN/A toRename->iewBlock[tid] = true; 5392292SN/A wroteToTimeBuffer = true; 5402292SN/A } 5412292SN/A 5422292SN/A // Add the current inputs to the skid buffer so they can be 5432292SN/A // reprocessed when this stage unblocks. 5442292SN/A skidInsert(tid); 5452292SN/A 5462292SN/A dispatchStatus[tid] = Blocked; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate<class Impl> 5502292SN/Avoid 5512292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5522292SN/A{ 5532292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5546221Snate@binkert.org "buffer %u.\n",tid, tid); 5552292SN/A 5562292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5572292SN/A // Also switch status to running. 5582292SN/A if (skidBuffer[tid].empty()) { 5592292SN/A toRename->iewUnblock[tid] = true; 5602292SN/A wroteToTimeBuffer = true; 5612292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5622292SN/A dispatchStatus[tid] = Running; 5632292SN/A } 5642292SN/A} 5652292SN/A 5662292SN/Atemplate<class Impl> 5672292SN/Avoid 5682292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5692292SN/A{ 5702292SN/A instQueue.wakeDependents(inst); 57113429Srekai.gonzalezalberquilla@arm.com} 5721060SN/A 5731681SN/Atemplate<class Impl> 5741060SN/Avoid 5751060SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5762292SN/A{ 5772292SN/A instQueue.rescheduleMemInst(inst); 57813429Srekai.gonzalezalberquilla@arm.com} 5792292SN/A 5802292SN/Atemplate<class Impl> 5812292SN/Avoid 5821681SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5831681SN/A{ 5841060SN/A instQueue.replayMemInst(inst); 58513429Srekai.gonzalezalberquilla@arm.com} 5861060SN/A 5872292SN/Atemplate<class Impl> 5882292SN/Avoid 5891060SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5902292SN/A{ 5912292SN/A // This function should not be called after writebackInsts in a 59213429Srekai.gonzalezalberquilla@arm.com // single cycle. That will cause problems with an instruction 59310333Smitch.hayenga@arm.com // being added to the queue to commit without being processed by 59410333Smitch.hayenga@arm.com // writebackInsts prior to being sent to commit. 59510333Smitch.hayenga@arm.com 59610333Smitch.hayenga@arm.com // First check the time slot that this instruction will write 59710333Smitch.hayenga@arm.com // to. If there are free write ports at the time, then go ahead 59810333Smitch.hayenga@arm.com // and write the instruction to that time. If there are not, 59910333Smitch.hayenga@arm.com // keep looking back to see where's the first time there's a 60010333Smitch.hayenga@arm.com // free slot. 60110333Smitch.hayenga@arm.com while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 60210333Smitch.hayenga@arm.com ++wbNumInst; 60310333Smitch.hayenga@arm.com if (wbNumInst == wbWidth) { 60410333Smitch.hayenga@arm.com ++wbCycle; 60510333Smitch.hayenga@arm.com wbNumInst = 0; 60613429Srekai.gonzalezalberquilla@arm.com } 6072292SN/A 6083221Sktlim@umich.edu assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6093221Sktlim@umich.edu } 6103221Sktlim@umich.edu 6113221Sktlim@umich.edu DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6123221Sktlim@umich.edu wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6132292SN/A // Add finished instruction to queue to commit. 6142292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6152292SN/A (*iewQueue)[wbCycle].size++; 6162292SN/A} 6172326SN/A 6182292SN/Atemplate <class Impl> 6192292SN/Aunsigned 6202820Sktlim@umich.eduDefaultIEW<Impl>::validInstsFromRename() 6212292SN/A{ 6222292SN/A unsigned inst_count = 0; 6232292SN/A 6242292SN/A for (int i=0; i<fromRename->size; i++) { 6252292SN/A if (!fromRename->insts[i]->isSquashed()) 6262353SN/A inst_count++; 6272353SN/A } 6282292SN/A 6292292SN/A return inst_count; 6302292SN/A} 6312292SN/A 6322292SN/Atemplate<class Impl> 6332292SN/Avoid 6342292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6352292SN/A{ 6362292SN/A DynInstPtr inst = NULL; 6372292SN/A 6382292SN/A while (!insts[tid].empty()) { 6392292SN/A inst = insts[tid].front(); 6402731Sktlim@umich.edu 6412292SN/A insts[tid].pop(); 6422292SN/A 6432292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6442292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6452292SN/A inst->pcState(),tid); 6462292SN/A 6472292SN/A skidBuffer[tid].push(inst); 6482292SN/A } 6496221Snate@binkert.org 6502292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6512292SN/A "Skidbuffer Exceeded Max Size"); 6522292SN/A} 6532292SN/A 6542292SN/Atemplate<class Impl> 6552292SN/Aint 6562292SN/ADefaultIEW<Impl>::skidCount() 6572292SN/A{ 6589937SFaissal.Sleiman@arm.com int max=0; 6592292SN/A 6607720Sgblack@eecs.umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 6612292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6622292SN/A 6632292SN/A while (threads != end) { 6642292SN/A ThreadID tid = *threads++; 6652292SN/A unsigned thread_count = skidBuffer[tid].size(); 6662292SN/A if (max < thread_count) 6672292SN/A max = thread_count; 6682292SN/A } 6692292SN/A 6702292SN/A return max; 6712292SN/A} 6722292SN/A 6732292SN/Atemplate<class Impl> 6742292SN/Abool 6756221Snate@binkert.orgDefaultIEW<Impl>::skidsEmpty() 6766221Snate@binkert.org{ 6772292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6783867Sbinkertn@umich.edu list<ThreadID>::iterator end = activeThreads->end(); 6796221Snate@binkert.org 6803867Sbinkertn@umich.edu while (threads != end) { 6812292SN/A ThreadID tid = *threads++; 6822292SN/A 6832292SN/A if (!skidBuffer[tid].empty()) 6842292SN/A return false; 6852292SN/A } 6862292SN/A 6872292SN/A return true; 6882292SN/A} 6892292SN/A 6902292SN/Atemplate <class Impl> 6912292SN/Avoid 6926221Snate@binkert.orgDefaultIEW<Impl>::updateStatus() 6936221Snate@binkert.org{ 6942292SN/A bool any_unblocking = false; 6953867Sbinkertn@umich.edu 6966221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6973867Sbinkertn@umich.edu list<ThreadID>::iterator end = activeThreads->end(); 6983867Sbinkertn@umich.edu 6992292SN/A while (threads != end) { 7002292SN/A ThreadID tid = *threads++; 7012292SN/A 7022292SN/A if (dispatchStatus[tid] == Unblocking) { 7031062SN/A any_unblocking = true; 7041062SN/A break; 7051681SN/A } 7061062SN/A } 7072292SN/A 7081062SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7092292SN/A // and there's no stores waiting to write back, and dispatch is not 7101062SN/A // unblocking, then there is no internal activity for the IEW stage. 7116221Snate@binkert.org instQueue.intInstQueueReads++; 7126221Snate@binkert.org if (_status == Active && !instQueue.hasReadyInsts() && 7131062SN/A !ldstQueue.willWB() && !any_unblocking) { 7143867Sbinkertn@umich.edu DPRINTF(IEW, "IEW switching to idle\n"); 7156221Snate@binkert.org 7161062SN/A deactivateStage(); 7172292SN/A 7182292SN/A _status = Inactive; 7192292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7202292SN/A ldstQueue.willWB() || 7212292SN/A any_unblocking)) { 7221062SN/A // Otherwise there is internal activity. Set to active. 7232292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7242292SN/A 7252292SN/A activateStage(); 7267897Shestness@cs.utexas.edu 7272292SN/A _status = Active; 7282292SN/A } 7292292SN/A} 7301062SN/A 7312292SN/Atemplate <class Impl> 7321062SN/Avoid 7332292SN/ADefaultIEW<Impl>::resetEntries() 7342292SN/A{ 7352292SN/A instQueue.resetEntries(); 7362292SN/A ldstQueue.resetEntries(); 7372292SN/A} 7382292SN/A 7391062SN/Atemplate <class Impl> 7402292SN/Avoid 7411062SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7422292SN/A{ 7431062SN/A if (fromCommit->commitBlock[tid]) { 7441062SN/A stalls[tid].commit = true; 7451062SN/A } 7461681SN/A 7471062SN/A if (fromCommit->commitUnblock[tid]) { 7482292SN/A assert(stalls[tid].commit); 7491062SN/A stalls[tid].commit = false; 7502292SN/A } 7512292SN/A} 7522292SN/A 7531062SN/Atemplate <class Impl> 7542292SN/Abool 7552292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7566221Snate@binkert.org{ 7572292SN/A bool ret_val(false); 7582292SN/A 7592292SN/A if (stalls[tid].commit) { 76010328Smitch.hayenga@arm.com DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7612292SN/A ret_val = true; 7622292SN/A } else if (instQueue.isFull(tid)) { 7632292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7642292SN/A ret_val = true; 7652292SN/A } else if (ldstQueue.isFull(tid)) { 7662292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7672292SN/A 7682292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7692292SN/A 7702292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7712292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7722292SN/A } 7736221Snate@binkert.org 7742292SN/A if (ldstQueue.numStores(tid) > 0) { 7752292SN/A 7762292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7772292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7782292SN/A } 7792292SN/A 7802292SN/A ret_val = true; 7812292SN/A } else if (ldstQueue.isStalled(tid)) { 7822292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7832292SN/A ret_val = true; 7842292SN/A } 7852292SN/A 7862292SN/A return ret_val; 7872292SN/A} 7882292SN/A 7892292SN/Atemplate <class Impl> 7902292SN/Avoid 7912292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7922292SN/A{ 7932292SN/A // Check if there's a squash signal, squash if there is 7942292SN/A // Check stall signals, block if there is. 7952292SN/A // If status was Blocked 7962292SN/A // if so then go to unblocking 7972702Sktlim@umich.edu // If status was Squashing 7982292SN/A // check if squashing is not high. Switch to running this cycle. 7992292SN/A 8002702Sktlim@umich.edu readStallSignals(tid); 8012702Sktlim@umich.edu 8022292SN/A if (fromCommit->commitInfo[tid].squash) { 8032292SN/A squash(tid); 8042292SN/A 8052292SN/A if (dispatchStatus[tid] == Blocked || 8062292SN/A dispatchStatus[tid] == Unblocking) { 8072292SN/A toRename->iewUnblock[tid] = true; 8082292SN/A wroteToTimeBuffer = true; 8092292SN/A } 8102292SN/A 8112292SN/A dispatchStatus[tid] = Squashing; 8122292SN/A fetchRedirect[tid] = false; 8132292SN/A return; 8142292SN/A } 8152292SN/A 8162292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8172292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8182292SN/A 8192292SN/A dispatchStatus[tid] = Squashing; 8202292SN/A emptyRenameInsts(tid); 8212292SN/A wroteToTimeBuffer = true; 8222292SN/A return; 8232292SN/A } 8242292SN/A 8252292SN/A if (checkStall(tid)) { 8262292SN/A block(tid); 8272292SN/A dispatchStatus[tid] = Blocked; 8282292SN/A return; 8292292SN/A } 8302292SN/A 8312292SN/A if (dispatchStatus[tid] == Blocked) { 8322292SN/A // Status from previous cycle was blocked, but there are no more stall 8332292SN/A // conditions. Switch over to unblocking. 8342292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8352292SN/A tid); 8362292SN/A 8372292SN/A dispatchStatus[tid] = Unblocking; 8382292SN/A 8392292SN/A unblock(tid); 8402326SN/A 8416221Snate@binkert.org return; 8426221Snate@binkert.org } 8432326SN/A 8442292SN/A if (dispatchStatus[tid] == Squashing) { 8452292SN/A // Switch status to running if rename isn't being told to block or 8462292SN/A // squash this cycle. 8472292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8482292SN/A tid); 8492292SN/A 8502292SN/A dispatchStatus[tid] = Running; 8516221Snate@binkert.org 8522702Sktlim@umich.edu return; 8534632Sgblack@eecs.umich.edu } 8542935Sksewell@umich.edu} 8552702Sktlim@umich.edu 8562935Sksewell@umich.edutemplate <class Impl> 85710239Sbinhpham@cs.rutgers.eduvoid 85810239Sbinhpham@cs.rutgers.eduDefaultIEW<Impl>::sortInsts() 85910239Sbinhpham@cs.rutgers.edu{ 86010239Sbinhpham@cs.rutgers.edu int insts_from_rename = fromRename->size; 86110239Sbinhpham@cs.rutgers.edu#ifdef DEBUG 8622702Sktlim@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) 8632702Sktlim@umich.edu assert(insts[tid].empty()); 8642702Sktlim@umich.edu#endif 8652702Sktlim@umich.edu for (int i = 0; i < insts_from_rename; ++i) { 8662702Sktlim@umich.edu insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8672702Sktlim@umich.edu } 8682702Sktlim@umich.edu} 8692702Sktlim@umich.edu 8702702Sktlim@umich.edutemplate <class Impl> 8712702Sktlim@umich.eduvoid 8722292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8732292SN/A{ 8742292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8752292SN/A 8762292SN/A while (!insts[tid].empty()) { 8772292SN/A 8782292SN/A if (insts[tid].front()->isLoad() || 8792292SN/A insts[tid].front()->isStore() ) { 8802292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 8812292SN/A } 8822292SN/A 8832292SN/A toRename->iewInfo[tid].dispatched++; 8842292SN/A 8852292SN/A insts[tid].pop(); 8862292SN/A } 8872292SN/A} 8882292SN/A 8892292SN/Atemplate <class Impl> 8902733Sktlim@umich.eduvoid 8912292SN/ADefaultIEW<Impl>::wakeCPU() 8922292SN/A{ 8932292SN/A cpu->wakeCPU(); 8942292SN/A} 8952292SN/A 8962292SN/Atemplate <class Impl> 8972292SN/Avoid 8982733Sktlim@umich.eduDefaultIEW<Impl>::activityThisCycle() 8992292SN/A{ 9002292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9012292SN/A cpu->activityThisCycle(); 9022292SN/A} 9036221Snate@binkert.org 9042292SN/Atemplate <class Impl> 9052292SN/Ainline void 9062292SN/ADefaultIEW<Impl>::activateStage() 9072292SN/A{ 9082292SN/A DPRINTF(Activity, "Activating stage.\n"); 9092292SN/A cpu->activateStage(O3CPU::IEWIdx); 9102292SN/A} 9112292SN/A 9122292SN/Atemplate <class Impl> 9132292SN/Ainline void 9142292SN/ADefaultIEW<Impl>::deactivateStage() 9152292SN/A{ 9162292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9172292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9182292SN/A} 9192292SN/A 9202292SN/Atemplate<class Impl> 9212292SN/Avoid 9222292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9232292SN/A{ 9242292SN/A // If status is Running or idle, 9252292SN/A // call dispatchInsts() 9262292SN/A // If status is Unblocking, 9272292SN/A // buffer any instructions coming from rename 9282292SN/A // continue trying to empty skid buffer 9292292SN/A // check if stall conditions have passed 9302292SN/A 9312292SN/A if (dispatchStatus[tid] == Blocked) { 9322292SN/A ++iewBlockCycles; 9332292SN/A 9342292SN/A } else if (dispatchStatus[tid] == Squashing) { 9352292SN/A ++iewSquashCycles; 9362292SN/A } 9372292SN/A 9382292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9395215Sgblack@eecs.umich.edu // will allow, as long as it is not currently blocked. 9402292SN/A if (dispatchStatus[tid] == Running || 9412292SN/A dispatchStatus[tid] == Idle) { 9422292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9432292SN/A "dispatch.\n", tid); 9442292SN/A 9452292SN/A dispatchInsts(tid); 9462292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9472292SN/A // Make sure that the skid buffer has something in it if the 9482292SN/A // status is unblocking. 9492292SN/A assert(!skidsEmpty()); 9502292SN/A 9516221Snate@binkert.org // If the status was unblocking, then instructions from the skid 9522292SN/A // buffer were used. Remove those instructions and handle 9532292SN/A // the rest of unblocking. 9542292SN/A dispatchInsts(tid); 9552292SN/A 9562292SN/A ++iewUnblockCycles; 9572292SN/A 9582292SN/A if (validInstsFromRename()) { 9592292SN/A // Add the current inputs to the skid buffer so they can be 9602292SN/A // reprocessed when this stage unblocks. 9612292SN/A skidInsert(tid); 9622292SN/A } 9632292SN/A 9642292SN/A unblock(tid); 9652292SN/A } 9662292SN/A} 9672292SN/A 9682820Sktlim@umich.edutemplate <class Impl> 9692292SN/Avoid 9702292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9712292SN/A{ 9722292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9732292SN/A // otherwise. 9742292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9752292SN/A dispatchStatus[tid] == Unblocking ? 9762292SN/A skidBuffer[tid] : insts[tid]; 9772292SN/A 9782292SN/A int insts_to_add = insts_to_dispatch.size(); 9792292SN/A 9802292SN/A DynInstPtr inst; 9817720Sgblack@eecs.umich.edu bool add_to_iq = false; 9822292SN/A int dis_num_inst = 0; 9837720Sgblack@eecs.umich.edu 9842292SN/A // Loop through the instructions, putting them in the instruction 9852292SN/A // queue. 9862292SN/A for ( ; dis_num_inst < insts_to_add && 9872292SN/A dis_num_inst < dispatchWidth; 9882292SN/A ++dis_num_inst) 9892292SN/A { 9902292SN/A inst = insts_to_dispatch.front(); 9912292SN/A 9922292SN/A if (dispatchStatus[tid] == Unblocking) { 9932292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9942292SN/A "buffer\n", tid); 9952292SN/A } 9962292SN/A 9972292SN/A // Make sure there's a valid instruction there. 9982292SN/A assert(inst); 99910239Sbinhpham@cs.rutgers.edu 100010239Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10012292SN/A "IQ.\n", 100210239Sbinhpham@cs.rutgers.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 100310239Sbinhpham@cs.rutgers.edu 100410239Sbinhpham@cs.rutgers.edu // Be sure to mark these instructions as ready so that the 100510239Sbinhpham@cs.rutgers.edu // commit stage can go ahead and execute them, and mark 10062292SN/A // them as issued so the IQ doesn't reprocess them. 10072292SN/A 10082292SN/A // Check for squashed instructions. 10092292SN/A if (inst->isSquashed()) { 10102292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10112292SN/A "not adding to IQ.\n", tid); 10122292SN/A 10132292SN/A ++iewDispSquashedInsts; 10142292SN/A 10152292SN/A insts_to_dispatch.pop(); 10162292SN/A 10172292SN/A //Tell Rename That An Instruction has been processed 10182292SN/A if (inst->isLoad() || inst->isStore()) { 10192292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10202292SN/A } 10212292SN/A toRename->iewInfo[tid].dispatched++; 10222292SN/A 10232292SN/A continue; 10242292SN/A } 102510240Sbinhpham@cs.rutgers.edu 102610240Sbinhpham@cs.rutgers.edu // Check for full conditions. 102710240Sbinhpham@cs.rutgers.edu if (instQueue.isFull(tid)) { 102810240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 102910240Sbinhpham@cs.rutgers.edu 103010240Sbinhpham@cs.rutgers.edu // Call function to start blocking. 103110240Sbinhpham@cs.rutgers.edu block(tid); 10322292SN/A 10332292SN/A // Set unblock to false. Special case where we are using 10342292SN/A // skidbuffer (unblocking) instructions but then we still 10352292SN/A // get full in the IQ. 10362292SN/A toRename->iewUnblock[tid] = false; 10372292SN/A 10382292SN/A ++iewIQFullEvents; 10392292SN/A break; 10402292SN/A } else if (ldstQueue.isFull(tid)) { 10412292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10422292SN/A 10432292SN/A // Call function to start blocking. 10442292SN/A block(tid); 10452292SN/A 10462292SN/A // Set unblock to false. Special case where we are using 10472292SN/A // skidbuffer (unblocking) instructions but then we still 10482292SN/A // get full in the IQ. 10492292SN/A toRename->iewUnblock[tid] = false; 10502292SN/A 10512292SN/A ++iewLSQFullEvents; 10522292SN/A break; 10532292SN/A } 10542292SN/A 10552292SN/A // Otherwise issue the instruction just fine. 10562292SN/A if (inst->isLoad()) { 10572292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 105810239Sbinhpham@cs.rutgers.edu "encountered, adding to LSQ.\n", tid); 10592292SN/A 10602292SN/A // Reserve a spot in the load store queue for this 10612292SN/A // memory access. 10622292SN/A ldstQueue.insertLoad(inst); 10632292SN/A 10642292SN/A ++iewDispLoadInsts; 10652292SN/A 10662292SN/A add_to_iq = true; 10672336SN/A 10682336SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10692336SN/A } else if (inst->isStore()) { 10702336SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10712348SN/A "encountered, adding to LSQ.\n", tid); 10722292SN/A 10732292SN/A ldstQueue.insertStore(inst); 10742292SN/A 10752292SN/A ++iewDispStoreInsts; 10762292SN/A 10772292SN/A if (inst->isStoreConditional()) { 10782292SN/A // Store conditionals need to be set as "canCommit()" 10792292SN/A // so that commit can process them when they reach the 10802292SN/A // head of commit. 108110239Sbinhpham@cs.rutgers.edu // @todo: This is somewhat specific to Alpha. 10822292SN/A inst->setCanCommit(); 10832326SN/A instQueue.insertNonSpec(inst); 10842292SN/A add_to_iq = false; 10852292SN/A 10862292SN/A ++iewDispNonSpecInsts; 10872292SN/A } else { 10882292SN/A add_to_iq = true; 10892292SN/A } 10902292SN/A 10912292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10922292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10932292SN/A // Same as non-speculative stores. 10942292SN/A inst->setCanCommit(); 10952326SN/A instQueue.insertBarrier(inst); 10962292SN/A add_to_iq = false; 10972727Sktlim@umich.edu } else if (inst->isNop()) { 10982301SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10992292SN/A "skipping.\n", tid); 11002292SN/A 110110733Snilay@cs.wisc.edu inst->setIssued(); 11022292SN/A inst->setExecuted(); 11032292SN/A inst->setCanCommit(); 110410733Snilay@cs.wisc.edu 110512537Sandreas.sandberg@arm.com instQueue.recordProducer(inst); 11064033Sktlim@umich.edu 11074033Sktlim@umich.edu iewExecutedNop[tid]++; 11084033Sktlim@umich.edu 11094033Sktlim@umich.edu add_to_iq = false; 11104033Sktlim@umich.edu } else if (inst->isExecuted()) { 11114033Sktlim@umich.edu assert(0 && "Instruction shouldn't be executed.\n"); 11124033Sktlim@umich.edu DPRINTF(IEW, "Issue: Executed branch encountered, " 11134033Sktlim@umich.edu "skipping.\n"); 11144033Sktlim@umich.edu 11154033Sktlim@umich.edu inst->setIssued(); 11164033Sktlim@umich.edu inst->setCanCommit(); 11174033Sktlim@umich.edu 11184033Sktlim@umich.edu instQueue.recordProducer(inst); 11192292SN/A 11202292SN/A add_to_iq = false; 11212292SN/A } else { 11222292SN/A add_to_iq = true; 11232292SN/A } 11242292SN/A if (inst->isNonSpeculative()) { 11252292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11262292SN/A "encountered, skipping.\n", tid); 11272292SN/A 11282292SN/A // Same as non-speculative stores. 11292292SN/A inst->setCanCommit(); 11302292SN/A 11318471SGiacomo.Gabrielli@arm.com // Specifically insert it as nonspeculative. 11328471SGiacomo.Gabrielli@arm.com instQueue.insertNonSpec(inst); 11339046SAli.Saidi@ARM.com 11348471SGiacomo.Gabrielli@arm.com ++iewDispNonSpecInsts; 113510023Smatt.horsnell@ARM.com 11362292SN/A add_to_iq = false; 11372292SN/A } 11382292SN/A 11392935Sksewell@umich.edu // If the instruction queue is not full, then add the 11402292SN/A // instruction. 11412292SN/A if (add_to_iq) { 11422292SN/A instQueue.insert(inst); 11432292SN/A } 11442292SN/A 11452292SN/A insts_to_dispatch.pop(); 11462292SN/A 11472292SN/A toRename->iewInfo[tid].dispatched++; 11482292SN/A 11492292SN/A ++iewDispatchedInsts; 11502292SN/A 11512292SN/A#if TRACING_ON 11522292SN/A inst->dispatchTick = curTick(); 11532292SN/A#endif 11542292SN/A } 11552292SN/A 11562292SN/A if (!insts_to_dispatch.empty()) { 11572292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11582292SN/A block(tid); 11592980Sgblack@eecs.umich.edu toRename->iewUnblock[tid] = false; 11602292SN/A } 11612292SN/A 11622292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11632980Sgblack@eecs.umich.edu dispatchStatus[tid] = Running; 11642292SN/A 11657720Sgblack@eecs.umich.edu updatedQueues = true; 11662292SN/A } 11672292SN/A 11682292SN/A dis_num_inst = 0; 11692292SN/A} 11702292SN/A 11712292SN/Atemplate <class Impl> 11722292SN/Avoid 11732980Sgblack@eecs.umich.eduDefaultIEW<Impl>::printAvailableInsts() 11742292SN/A{ 11752292SN/A int inst = 0; 11762292SN/A 11772292SN/A std::cout << "Available Instructions: "; 11782292SN/A 11792292SN/A while (fromIssue->insts[inst]) { 11802292SN/A 11812292SN/A if (inst%3==0) std::cout << "\n\t"; 11822292SN/A 11836221Snate@binkert.org std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11846221Snate@binkert.org << " TN: " << fromIssue->insts[inst]->threadNumber 11852292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11863867Sbinkertn@umich.edu 11876221Snate@binkert.org inst++; 11882292SN/A 11892292SN/A } 11902292SN/A 11912698Sktlim@umich.edu std::cout << "\n"; 11927599Sminkyu.jeong@arm.com} 11932698Sktlim@umich.edu 11941062SN/Atemplate <class Impl> 11951062SN/Avoid 11962333SN/ADefaultIEW<Impl>::executeInsts() 11972292SN/A{ 11982333SN/A wbNumInst = 0; 11992326SN/A wbCycle = 0; 12001062SN/A 12012292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 12021062SN/A list<ThreadID>::iterator end = activeThreads->end(); 12032333SN/A 12041062SN/A while (threads != end) { 12057720Sgblack@eecs.umich.edu ThreadID tid = *threads++; 12067720Sgblack@eecs.umich.edu fetchRedirect[tid] = false; 12071062SN/A } 120811246Sradhika.jagtap@ARM.com 120911246Sradhika.jagtap@ARM.com // Uncomment this if you want to see all available instructions. 121011246Sradhika.jagtap@ARM.com // @todo This doesn't actually work anymore, we should fix it. 121111246Sradhika.jagtap@ARM.com// printAvailableInsts(); 12121062SN/A 12131062SN/A // Execute/writeback any instructions that are available. 12148315Sgeoffrey.blake@arm.com int insts_to_execute = fromIssue->size; 12158315Sgeoffrey.blake@arm.com int inst_num = 0; 12168315Sgeoffrey.blake@arm.com for (; inst_num < insts_to_execute; 12171062SN/A ++inst_num) { 12181062SN/A 12191062SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12201062SN/A 12211062SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12222292SN/A 12232292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12242292SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12251062SN/A 12261062SN/A // Check if the instruction is squashed; if so then skip it 12271062SN/A if (inst->isSquashed()) { 12281062SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12291062SN/A " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12301062SN/A inst->seqNum); 12312292SN/A 12321062SN/A // Consider this instruction executed so that commit can go 12331062SN/A // ahead and retire the instruction. 12341062SN/A inst->setExecuted(); 12351062SN/A 12367850SMatt.Horsnell@arm.com // Not sure if I should set this here or just let commit try to 12372292SN/A // commit any squashed instructions. I like the latter a bit more. 12381062SN/A inst->setCanCommit(); 12391062SN/A 12401062SN/A ++iewExecSquashedInsts; 12411062SN/A 12422292SN/A decrWb(inst->seqNum); 12432292SN/A continue; 12442292SN/A } 12457944SGiacomo.Gabrielli@arm.com 12467944SGiacomo.Gabrielli@arm.com Fault fault = NoFault; 12477944SGiacomo.Gabrielli@arm.com 12487944SGiacomo.Gabrielli@arm.com // Execute instruction. 12497944SGiacomo.Gabrielli@arm.com // Note that if the instruction faults, it will be handled 12507944SGiacomo.Gabrielli@arm.com // at the commit stage. 12517944SGiacomo.Gabrielli@arm.com if (inst->isMemRef()) { 12527944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Calculating address for memory " 12537944SGiacomo.Gabrielli@arm.com "reference.\n"); 12547944SGiacomo.Gabrielli@arm.com 12557944SGiacomo.Gabrielli@arm.com // Tell the LDSTQ to execute this instruction (if it is a load). 12567850SMatt.Horsnell@arm.com if (inst->isLoad()) { 12578073SAli.Saidi@ARM.com // Loads will mark themselves as executed, and their writeback 12587850SMatt.Horsnell@arm.com // event adds the instruction to the queue to commit 12591062SN/A fault = ldstQueue.executeLoad(inst); 12602367SN/A 12611062SN/A if (inst->isTranslationDelayed() && 12627944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12637944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12647944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12657944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12667944SGiacomo.Gabrielli@arm.com "load.\n"); 12677944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12687944SGiacomo.Gabrielli@arm.com continue; 12697944SGiacomo.Gabrielli@arm.com } 12707944SGiacomo.Gabrielli@arm.com 12717944SGiacomo.Gabrielli@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12722292SN/A inst->fault = NoFault; 127310231Ssteve.reinhardt@amd.com } 12747782Sminkyu.jeong@arm.com } else if (inst->isStore()) { 12757782Sminkyu.jeong@arm.com fault = ldstQueue.executeStore(inst); 12767782Sminkyu.jeong@arm.com 12772367SN/A if (inst->isTranslationDelayed() && 12782367SN/A fault == NoFault) { 12792367SN/A // A hw page table walk is currently going on; the 12802367SN/A // instruction must be deferred. 12812367SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12822292SN/A "store.\n"); 12832326SN/A instQueue.deferMemInst(inst); 12842326SN/A continue; 12852326SN/A } 12862326SN/A 12871062SN/A // If the store had a fault then it may not have a mem req 12882292SN/A if (fault != NoFault || inst->readPredicate() == false || 12891062SN/A !inst->isStoreConditional()) { 12901062SN/A // If the instruction faulted, then we need to send it along 12911062SN/A // to commit without the instruction completing. 12927847Sminkyu.jeong@arm.com // Send this instruction to commit, also make sure iew stage 12937847Sminkyu.jeong@arm.com // realizes there is activity. 12947847Sminkyu.jeong@arm.com inst->setExecuted(); 12957847Sminkyu.jeong@arm.com instToCommit(inst); 12967847Sminkyu.jeong@arm.com activityThisCycle(); 12977847Sminkyu.jeong@arm.com } 129810231Ssteve.reinhardt@amd.com 12997848SAli.Saidi@ARM.com // Store conditionals will mark themselves as 13007847Sminkyu.jeong@arm.com // executed, and their writeback event will add the 13011062SN/A // instruction to the queue to commit. 13022292SN/A } else { 13032292SN/A panic("Unexpected memory type!\n"); 13042292SN/A } 13051062SN/A 13061062SN/A } else { 13072301SN/A // If the instruction has already faulted, then skip executing it. 13081681SN/A // Such case can happen when it faulted during ITLB translation. 13092326SN/A // If we execute the instruction (even if it's a nop) the fault 13102326SN/A // will be replaced and we will lose it. 13112326SN/A if (inst->getFault() == NoFault) { 13122107SN/A inst->execute(); 13131681SN/A if (inst->readPredicate() == false) 13142292SN/A inst->forwardOldRegs(); 13152292SN/A } 13162292SN/A 13176221Snate@binkert.org inst->setExecuted(); 13181062SN/A 13193732Sktlim@umich.edu instToCommit(inst); 13207852SMatt.Horsnell@arm.com } 13213732Sktlim@umich.edu 13221062SN/A updateExeInstStats(inst); 13237856SMatt.Horsnell@arm.com 13247856SMatt.Horsnell@arm.com // Check if branch prediction was correct, if not then we need 13257856SMatt.Horsnell@arm.com // to tell commit to squash in flight instructions. Only 13267856SMatt.Horsnell@arm.com // handle this if there hasn't already been something that 13277856SMatt.Horsnell@arm.com // redirects fetch in this group of instructions. 13282292SN/A 13291062SN/A // This probably needs to prioritize the redirects if a different 13302292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13318674Snilay@cs.wisc.edu // instruction first, so the branch resolution order will be correct. 13328674Snilay@cs.wisc.edu ThreadID tid = inst->threadNumber; 13337720Sgblack@eecs.umich.edu 13348674Snilay@cs.wisc.edu if (!fetchRedirect[tid] || 13351062SN/A !toCommit->squash[tid] || 13362292SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 13371062SN/A 133810023Smatt.horsnell@ARM.com // Prevent testing for misprediction on load instructions, 133910023Smatt.horsnell@ARM.com // that have not been executed. 13403795Sgblack@eecs.umich.edu bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13411062SN/A 13422292SN/A if (inst->mispredicted() && !loadNotExecuted) { 13432292SN/A fetchRedirect[tid] = true; 13441062SN/A 13452292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13464033Sktlim@umich.edu DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13472326SN/A inst->predInstAddr(), inst->predNextInstAddr()); 13482326SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13492292SN/A inst->pcState(), inst->nextInstAddr()); 13502292SN/A // If incorrect, then signal the ROB that it must be squashed. 13512292SN/A squashDueToBranch(inst, tid); 13521062SN/A 13537720Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13547720Sgblack@eecs.umich.edu predictedTakenIncorrect++; 13557720Sgblack@eecs.umich.edu } else { 135611097Songal@cs.wisc.edu predictedNotTakenIncorrect++; 13577720Sgblack@eecs.umich.edu } 13583732Sktlim@umich.edu } else if (ldstQueue.violation(tid)) { 13593732Sktlim@umich.edu assert(inst->isMemRef()); 13601062SN/A // If there was an ordering violation, then get the 13611062SN/A // DynInst that caused the violation. Note that this 13621062SN/A // clears the violation signal. 13631062SN/A DynInstPtr violator; 13648513SGiacomo.Gabrielli@arm.com violator = ldstQueue.getMemDepViolator(tid); 13651062SN/A 13661062SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13671062SN/A "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13684033Sktlim@umich.edu violator->pcState(), violator->seqNum, 13694033Sktlim@umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13704033Sktlim@umich.edu 13714033Sktlim@umich.edu fetchRedirect[tid] = true; 13724033Sktlim@umich.edu 13734033Sktlim@umich.edu // Tell the instruction queue that a violation has occured. 13744033Sktlim@umich.edu instQueue.violation(inst, violator); 13754033Sktlim@umich.edu 13764033Sktlim@umich.edu // Squash. 13777720Sgblack@eecs.umich.edu squashDueToMemOrder(inst,tid); 13787720Sgblack@eecs.umich.edu 137911097Songal@cs.wisc.edu ++memOrderViolationEvents; 13804033Sktlim@umich.edu } else if (ldstQueue.loadBlocked(tid) && 13814033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13824033Sktlim@umich.edu fetchRedirect[tid] = true; 13834033Sktlim@umich.edu 13844033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13851062SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 13861062SN/A inst->pcState(), inst->seqNum); 13872292SN/A 13882348SN/A squashDueToMemBlocked(inst, tid); 13892292SN/A } 13902292SN/A } else { 13912292SN/A // Reset any state associated with redirects that will not 13922292SN/A // be used. 13932292SN/A if (ldstQueue.violation(tid)) { 13942292SN/A assert(inst->isMemRef()); 13952292SN/A 13962292SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13972292SN/A 13982292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13992292SN/A "%s, inst PC: %s. Addr is: %#x.\n", 14002292SN/A violator->pcState(), inst->pcState(), 14012292SN/A inst->physEffAddr); 14022292SN/A DPRINTF(IEW, "Violation will not be handled because " 14037852SMatt.Horsnell@arm.com "already squashing\n"); 14042107SN/A 14052107SN/A ++memOrderViolationEvents; 14062292SN/A } 14072107SN/A if (ldstQueue.loadBlocked(tid) && 14082292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 14092107SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14102326SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 14112326SN/A inst->pcState(), inst->seqNum); 14122326SN/A DPRINTF(IEW, "Blocked load will not be handled because " 14132326SN/A "already squashing\n"); 14142326SN/A 14153958Sgblack@eecs.umich.edu ldstQueue.setLoadBlockedHandled(tid); 14162292SN/A } 14172107SN/A 14186221Snate@binkert.org } 14192107SN/A } 14207720Sgblack@eecs.umich.edu 14217720Sgblack@eecs.umich.edu // Update and record activity if we processed any instructions. 14222107SN/A if (inst_num) { 14232301SN/A if (exeStatus == Idle) { 142411246Sradhika.jagtap@ARM.com exeStatus = Running; 142511246Sradhika.jagtap@ARM.com } 142611246Sradhika.jagtap@ARM.com 14272301SN/A updatedQueues = true; 14282292SN/A 14292292SN/A cpu->activityThisCycle(); 143010824SAndreas.Sandberg@ARM.com } 14312292SN/A 143210824SAndreas.Sandberg@ARM.com // Need to reset this in case a writeback event needs to write into the 14332367SN/A // iew queue. That way the writeback event will write into the correct 14342301SN/A // spot in the queue. 14352107SN/A wbNumInst = 0; 14362292SN/A 14372292SN/A} 143812105Snathanael.premillieu@arm.com 143912106SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 144012106SRekai.GonzalezAlberquilla@arm.comvoid 14412292SN/ADefaultIEW<Impl>::writebackInsts() 14422107SN/A{ 14432301SN/A // Loop through the head of the time buffer and wake any 14442348SN/A // dependents. These instructions are about to write back. Also 14452348SN/A // mark scoreboard that this instruction is finally complete. 14462348SN/A // Either have IEW have direct access to scoreboard, or have this 14472348SN/A // as part of backwards communication. 14482326SN/A for (int inst_num = 0; inst_num < wbWidth && 14492107SN/A toCommit->insts[inst_num]; inst_num++) { 14502107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14511060SN/A ThreadID tid = inst->threadNumber; 14521060SN/A 14531681SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14541060SN/A inst->seqNum, inst->pcState()); 14552292SN/A 14561060SN/A iewInstsToCommit[tid]++; 14572292SN/A 14582292SN/A // Some instructions will be sent to commit without having 14591060SN/A // executed because they need commit to handle them. 14602292SN/A // E.g. Uncached loads have not actually executed when they 14612292SN/A // are first sent to commit. Instead commit must tell the LSQ 14621060SN/A // when it's ready to execute the uncached load. 14632292SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14641060SN/A int dependents = instQueue.wakeDependents(inst); 14652326SN/A 14662326SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14671062SN/A //mark as Ready 14686221Snate@binkert.org DPRINTF(IEW,"Setting Destination Register %i\n", 14696221Snate@binkert.org inst->renamedDestRegIdx(i)); 14701060SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14712326SN/A } 14723867Sbinkertn@umich.edu 14736221Snate@binkert.org if (dependents) { 14741060SN/A producerInst[tid]++; 14752292SN/A consumerInst[tid]+= dependents; 14761060SN/A } 14772292SN/A writebackCount[tid]++; 14782292SN/A } 14791060SN/A 14801060SN/A decrWb(inst->seqNum); 14812292SN/A } 14822292SN/A} 14831060SN/A 14842292SN/Atemplate<class Impl> 14852292SN/Avoid 14862292SN/ADefaultIEW<Impl>::tick() 14872292SN/A{ 14882292SN/A wbNumInst = 0; 14892292SN/A wbCycle = 0; 14902292SN/A 14912292SN/A wroteToTimeBuffer = false; 14922292SN/A updatedQueues = false; 14932292SN/A 14942292SN/A sortInsts(); 14952292SN/A 14962292SN/A // Free function units marked as being freed this cycle. 14972292SN/A fuPool->processFreeUnits(); 14982292SN/A 14992292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 15002292SN/A list<ThreadID>::iterator end = activeThreads->end(); 15012292SN/A 15022292SN/A // Check stall and squash signals, dispatch any instructions. 15032292SN/A while (threads != end) { 15042292SN/A ThreadID tid = *threads++; 15052292SN/A 15061681SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15071681SN/A 15081061SN/A checkSignalsAndUpdate(tid); 15091061SN/A dispatch(tid); 15101061SN/A } 15111681SN/A 15122292SN/A if (exeStatus != Squashing) { 15133867Sbinkertn@umich.edu executeInsts(); 15143867Sbinkertn@umich.edu 15156221Snate@binkert.org writebackInsts(); 15162292SN/A 15172292SN/A // Have the instruction queue try to schedule any ready instructions. 15182292SN/A // (In actuality, this scheduling is for instructions that will 15192348SN/A // be executed next cycle.) 15202292SN/A instQueue.scheduleReadyInsts(); 15212292SN/A 15222292SN/A // Also should advance its own time buffers if the stage ran. 15232292SN/A // Not the best place for it, but this works (hopefully). 15242292SN/A issueToExecQueue.advance(); 15252292SN/A } 15262292SN/A 15272292SN/A bool broadcast_free_entries = false; 15282292SN/A 15292292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15302292SN/A exeStatus = Idle; 15312292SN/A updateLSQNextCycle = false; 15322292SN/A 15332292SN/A broadcast_free_entries = true; 15342292SN/A } 153510824SAndreas.Sandberg@ARM.com 153610824SAndreas.Sandberg@ARM.com // Writeback any stores using any leftover bandwidth. 153710824SAndreas.Sandberg@ARM.com ldstQueue.writebackStores(); 153810824SAndreas.Sandberg@ARM.com 15392292SN/A // Check the committed load/store signals to see if there's a load 15402292SN/A // or store to commit. Also check if it's being told to execute a 15412292SN/A // nonspeculative instruction. 15422292SN/A // This is pretty inefficient... 15432292SN/A 15442292SN/A threads = activeThreads->begin(); 15452292SN/A while (threads != end) { 15462292SN/A ThreadID tid = (*threads++); 15472292SN/A 15482292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15492292SN/A 15502292SN/A // Update structures based on instructions committed. 15512292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15522292SN/A !fromCommit->commitInfo[tid].squash && 155310164Ssleimanf@umich.edu !fromCommit->commitInfo[tid].robSquashing) { 15542292SN/A 155510239Sbinhpham@cs.rutgers.edu ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 155610239Sbinhpham@cs.rutgers.edu 155710239Sbinhpham@cs.rutgers.edu ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 155810239Sbinhpham@cs.rutgers.edu 155910239Sbinhpham@cs.rutgers.edu updateLSQNextCycle = true; 15602292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15612292SN/A } 15622292SN/A 15632292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15642292SN/A 15652292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15661061SN/A if (fromCommit->commitInfo[tid].uncached) { 15671061SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15682292SN/A fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 156910239Sbinhpham@cs.rutgers.edu } else { 15702292SN/A instQueue.scheduleNonSpec( 157110239Sbinhpham@cs.rutgers.edu fromCommit->commitInfo[tid].nonSpecSeqNum); 15722292SN/A } 15732292SN/A } 15742292SN/A 15752292SN/A if (broadcast_free_entries) { 15762292SN/A toFetch->iewInfo[tid].iqCount = 15772292SN/A instQueue.getCount(tid); 15781061SN/A toFetch->iewInfo[tid].ldstqCount = 15791060SN/A ldstQueue.getCount(tid); 15801060SN/A 15812301SN/A toRename->iewInfo[tid].usedIQ = true; 15821060SN/A toRename->iewInfo[tid].freeIQEntries = 158313429Srekai.gonzalezalberquilla@arm.com instQueue.numFreeEntries(); 15841060SN/A toRename->iewInfo[tid].usedLSQ = true; 15856221Snate@binkert.org toRename->iewInfo[tid].freeLSQEntries = 15861060SN/A ldstQueue.numFreeEntries(tid); 15872669Sktlim@umich.edu 15881060SN/A wroteToTimeBuffer = true; 15898471SGiacomo.Gabrielli@arm.com } 15909527SMatt.Horsnell@arm.com 15919527SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15929527SMatt.Horsnell@arm.com tid, toRename->iewInfo[tid].dispatched); 15938471SGiacomo.Gabrielli@arm.com } 15948471SGiacomo.Gabrielli@arm.com 15952301SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15962301SN/A "LSQ has %i free entries.\n", 15972301SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15982301SN/A ldstQueue.numFreeEntries()); 15996221Snate@binkert.org 16001060SN/A updateStatus(); 16012301SN/A 16022301SN/A if (wroteToTimeBuffer) { 16032301SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16042301SN/A cpu->activityThisCycle(); 16056221Snate@binkert.org } 16061060SN/A} 16072301SN/A 16086221Snate@binkert.orgtemplate <class Impl> 16091060SN/Avoid 16101060SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16111060SN/A{ 16127598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16137598Sminkyu.jeong@arm.com 16147598Sminkyu.jeong@arm.com // 161513429Srekai.gonzalezalberquilla@arm.com // Pick off the software prefetches 16167598Sminkyu.jeong@arm.com // 16177598Sminkyu.jeong@arm.com#ifdef TARGET_ALPHA 16187598Sminkyu.jeong@arm.com if (inst->isDataPrefetch()) 16197598Sminkyu.jeong@arm.com iewExecutedSwp[tid]++; 16207852SMatt.Horsnell@arm.com else 16217598Sminkyu.jeong@arm.com iewIewExecutedcutedInsts++; 16227598Sminkyu.jeong@arm.com#else 16237598Sminkyu.jeong@arm.com iewExecutedInsts++; 16247598Sminkyu.jeong@arm.com#endif 16257598Sminkyu.jeong@arm.com 16267598Sminkyu.jeong@arm.com#if TRACING_ON 16277598Sminkyu.jeong@arm.com inst->completeTick = curTick(); 16287720Sgblack@eecs.umich.edu#endif 16297598Sminkyu.jeong@arm.com 16307720Sgblack@eecs.umich.edu // 16317720Sgblack@eecs.umich.edu // Control operations 16327598Sminkyu.jeong@arm.com // 16337598Sminkyu.jeong@arm.com if (inst->isControl()) 16347598Sminkyu.jeong@arm.com iewExecutedBranches[tid]++; 16357598Sminkyu.jeong@arm.com 16367598Sminkyu.jeong@arm.com // 16377598Sminkyu.jeong@arm.com // Memory operations 16387598Sminkyu.jeong@arm.com // 16397598Sminkyu.jeong@arm.com if (inst->isMemRef()) { 16407598Sminkyu.jeong@arm.com iewExecutedRefs[tid]++; 16417598Sminkyu.jeong@arm.com 16427598Sminkyu.jeong@arm.com if (inst->isLoad()) { 16439944Smatt.horsnell@ARM.com iewExecLoadInsts[tid]++; 16449944Smatt.horsnell@ARM.com } 1645 } 1646} 1647 1648template <class Impl> 1649void 1650DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1651{ 1652 ThreadID tid = inst->threadNumber; 1653 1654 if (!fetchRedirect[tid] || 1655 !toCommit->squash[tid] || 1656 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1657 1658 if (inst->mispredicted()) { 1659 fetchRedirect[tid] = true; 1660 1661 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1662 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1663 inst->predInstAddr(), inst->predNextInstAddr()); 1664 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1665 " NPC: %#x.\n", inst->nextInstAddr(), 1666 inst->nextInstAddr()); 1667 // If incorrect, then signal the ROB that it must be squashed. 1668 squashDueToBranch(inst, tid); 1669 1670 if (inst->readPredTaken()) { 1671 predictedTakenIncorrect++; 1672 } else { 1673 predictedNotTakenIncorrect++; 1674 } 1675 } 1676 } 1677} 1678