iew_impl.hh revision 8315
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 431060SN/A// @todo: Fix the instantaneous communication among all the stages within 441060SN/A// iew. There's a clear delay between issue and execute, yet backwards 451689SN/A// communication happens simultaneously. 461060SN/A 471060SN/A#include <queue> 481060SN/A 498230Snate@binkert.org#include "arch/utility.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/iew.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 548232Snate@binkert.org#include "debug/Activity.hh" 558232Snate@binkert.org#include "debug/Decode.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 575529Snate@binkert.org#include "params/DerivO3CPU.hh" 581060SN/A 596221Snate@binkert.orgusing namespace std; 606221Snate@binkert.org 611681SN/Atemplate<class Impl> 625529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 632873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 644329Sktlim@umich.edu cpu(_cpu), 654329Sktlim@umich.edu instQueue(_cpu, this, params), 664329Sktlim@umich.edu ldstQueue(_cpu, this, params), 672292SN/A fuPool(params->fuPool), 682292SN/A commitToIEWDelay(params->commitToIEWDelay), 692292SN/A renameToIEWDelay(params->renameToIEWDelay), 702292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 712820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 722292SN/A issueWidth(params->issueWidth), 732820Sktlim@umich.edu wbOutstanding(0), 742820Sktlim@umich.edu wbWidth(params->wbWidth), 755529Snate@binkert.org numThreads(params->numThreads), 762307SN/A switchedOut(false) 771060SN/A{ 782292SN/A _status = Active; 792292SN/A exeStatus = Running; 802292SN/A wbStatus = Idle; 811060SN/A 821060SN/A // Setup wire to read instructions coming from issue. 831060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 841060SN/A 851060SN/A // Instruction queue needs the queue between issue and execute. 861060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 871681SN/A 886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 896221Snate@binkert.org dispatchStatus[tid] = Running; 906221Snate@binkert.org stalls[tid].commit = false; 916221Snate@binkert.org fetchRedirect[tid] = false; 922292SN/A } 932292SN/A 942820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 952820Sktlim@umich.edu 962292SN/A updateLSQNextCycle = false; 972292SN/A 982820Sktlim@umich.edu ableToIssue = true; 992820Sktlim@umich.edu 1002292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1012292SN/A} 1022292SN/A 1032292SN/Atemplate <class Impl> 1042292SN/Astd::string 1052292SN/ADefaultIEW<Impl>::name() const 1062292SN/A{ 1072292SN/A return cpu->name() + ".iew"; 1081060SN/A} 1091060SN/A 1101681SN/Atemplate <class Impl> 1111062SN/Avoid 1122292SN/ADefaultIEW<Impl>::regStats() 1131062SN/A{ 1142301SN/A using namespace Stats; 1152301SN/A 1161062SN/A instQueue.regStats(); 1172727Sktlim@umich.edu ldstQueue.regStats(); 1181062SN/A 1191062SN/A iewIdleCycles 1201062SN/A .name(name() + ".iewIdleCycles") 1211062SN/A .desc("Number of cycles IEW is idle"); 1221062SN/A 1231062SN/A iewSquashCycles 1241062SN/A .name(name() + ".iewSquashCycles") 1251062SN/A .desc("Number of cycles IEW is squashing"); 1261062SN/A 1271062SN/A iewBlockCycles 1281062SN/A .name(name() + ".iewBlockCycles") 1291062SN/A .desc("Number of cycles IEW is blocking"); 1301062SN/A 1311062SN/A iewUnblockCycles 1321062SN/A .name(name() + ".iewUnblockCycles") 1331062SN/A .desc("Number of cycles IEW is unblocking"); 1341062SN/A 1351062SN/A iewDispatchedInsts 1361062SN/A .name(name() + ".iewDispatchedInsts") 1371062SN/A .desc("Number of instructions dispatched to IQ"); 1381062SN/A 1391062SN/A iewDispSquashedInsts 1401062SN/A .name(name() + ".iewDispSquashedInsts") 1411062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1421062SN/A 1431062SN/A iewDispLoadInsts 1441062SN/A .name(name() + ".iewDispLoadInsts") 1451062SN/A .desc("Number of dispatched load instructions"); 1461062SN/A 1471062SN/A iewDispStoreInsts 1481062SN/A .name(name() + ".iewDispStoreInsts") 1491062SN/A .desc("Number of dispatched store instructions"); 1501062SN/A 1511062SN/A iewDispNonSpecInsts 1521062SN/A .name(name() + ".iewDispNonSpecInsts") 1531062SN/A .desc("Number of dispatched non-speculative instructions"); 1541062SN/A 1551062SN/A iewIQFullEvents 1561062SN/A .name(name() + ".iewIQFullEvents") 1571062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1581062SN/A 1592292SN/A iewLSQFullEvents 1602292SN/A .name(name() + ".iewLSQFullEvents") 1612292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1622292SN/A 1631062SN/A memOrderViolationEvents 1641062SN/A .name(name() + ".memOrderViolationEvents") 1651062SN/A .desc("Number of memory order violations"); 1661062SN/A 1671062SN/A predictedTakenIncorrect 1681062SN/A .name(name() + ".predictedTakenIncorrect") 1691062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1702292SN/A 1712292SN/A predictedNotTakenIncorrect 1722292SN/A .name(name() + ".predictedNotTakenIncorrect") 1732292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1742292SN/A 1752292SN/A branchMispredicts 1762292SN/A .name(name() + ".branchMispredicts") 1772292SN/A .desc("Number of branch mispredicts detected at execute"); 1782292SN/A 1792292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1802301SN/A 1812727Sktlim@umich.edu iewExecutedInsts 1822353SN/A .name(name() + ".iewExecutedInsts") 1832727Sktlim@umich.edu .desc("Number of executed instructions"); 1842727Sktlim@umich.edu 1852727Sktlim@umich.edu iewExecLoadInsts 1866221Snate@binkert.org .init(cpu->numThreads) 1872353SN/A .name(name() + ".iewExecLoadInsts") 1882727Sktlim@umich.edu .desc("Number of load instructions executed") 1892727Sktlim@umich.edu .flags(total); 1902727Sktlim@umich.edu 1912727Sktlim@umich.edu iewExecSquashedInsts 1922353SN/A .name(name() + ".iewExecSquashedInsts") 1932727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1942727Sktlim@umich.edu 1952727Sktlim@umich.edu iewExecutedSwp 1966221Snate@binkert.org .init(cpu->numThreads) 1978240Snate@binkert.org .name(name() + ".exec_swp") 1982301SN/A .desc("number of swp insts executed") 1992727Sktlim@umich.edu .flags(total); 2002301SN/A 2012727Sktlim@umich.edu iewExecutedNop 2026221Snate@binkert.org .init(cpu->numThreads) 2038240Snate@binkert.org .name(name() + ".exec_nop") 2042301SN/A .desc("number of nop insts executed") 2052727Sktlim@umich.edu .flags(total); 2062301SN/A 2072727Sktlim@umich.edu iewExecutedRefs 2086221Snate@binkert.org .init(cpu->numThreads) 2098240Snate@binkert.org .name(name() + ".exec_refs") 2102301SN/A .desc("number of memory reference insts executed") 2112727Sktlim@umich.edu .flags(total); 2122301SN/A 2132727Sktlim@umich.edu iewExecutedBranches 2146221Snate@binkert.org .init(cpu->numThreads) 2158240Snate@binkert.org .name(name() + ".exec_branches") 2162301SN/A .desc("Number of branches executed") 2172727Sktlim@umich.edu .flags(total); 2182301SN/A 2192301SN/A iewExecStoreInsts 2208240Snate@binkert.org .name(name() + ".exec_stores") 2212301SN/A .desc("Number of stores executed") 2222727Sktlim@umich.edu .flags(total); 2232727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecRate 2268240Snate@binkert.org .name(name() + ".exec_rate") 2272727Sktlim@umich.edu .desc("Inst execution rate") 2282727Sktlim@umich.edu .flags(total); 2292727Sktlim@umich.edu 2302727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2312301SN/A 2322301SN/A iewInstsToCommit 2336221Snate@binkert.org .init(cpu->numThreads) 2348240Snate@binkert.org .name(name() + ".wb_sent") 2352301SN/A .desc("cumulative count of insts sent to commit") 2362727Sktlim@umich.edu .flags(total); 2372301SN/A 2382326SN/A writebackCount 2396221Snate@binkert.org .init(cpu->numThreads) 2408240Snate@binkert.org .name(name() + ".wb_count") 2412301SN/A .desc("cumulative count of insts written-back") 2422727Sktlim@umich.edu .flags(total); 2432301SN/A 2442326SN/A producerInst 2456221Snate@binkert.org .init(cpu->numThreads) 2468240Snate@binkert.org .name(name() + ".wb_producers") 2472301SN/A .desc("num instructions producing a value") 2482727Sktlim@umich.edu .flags(total); 2492301SN/A 2502326SN/A consumerInst 2516221Snate@binkert.org .init(cpu->numThreads) 2528240Snate@binkert.org .name(name() + ".wb_consumers") 2532301SN/A .desc("num instructions consuming a value") 2542727Sktlim@umich.edu .flags(total); 2552301SN/A 2562326SN/A wbPenalized 2576221Snate@binkert.org .init(cpu->numThreads) 2588240Snate@binkert.org .name(name() + ".wb_penalized") 2592301SN/A .desc("number of instrctions required to write to 'other' IQ") 2602727Sktlim@umich.edu .flags(total); 2612301SN/A 2622326SN/A wbPenalizedRate 2638240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2642301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2652727Sktlim@umich.edu .flags(total); 2662301SN/A 2672326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2682301SN/A 2692326SN/A wbFanout 2708240Snate@binkert.org .name(name() + ".wb_fanout") 2712301SN/A .desc("average fanout of values written-back") 2722727Sktlim@umich.edu .flags(total); 2732301SN/A 2742326SN/A wbFanout = producerInst / consumerInst; 2752301SN/A 2762326SN/A wbRate 2778240Snate@binkert.org .name(name() + ".wb_rate") 2782301SN/A .desc("insts written-back per cycle") 2792727Sktlim@umich.edu .flags(total); 2802326SN/A wbRate = writebackCount / cpu->numCycles; 2811062SN/A} 2821062SN/A 2831681SN/Atemplate<class Impl> 2841060SN/Avoid 2852292SN/ADefaultIEW<Impl>::initStage() 2861060SN/A{ 2876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2882292SN/A toRename->iewInfo[tid].usedIQ = true; 2892292SN/A toRename->iewInfo[tid].freeIQEntries = 2902292SN/A instQueue.numFreeEntries(tid); 2912292SN/A 2922292SN/A toRename->iewInfo[tid].usedLSQ = true; 2932292SN/A toRename->iewInfo[tid].freeLSQEntries = 2942292SN/A ldstQueue.numFreeEntries(tid); 2952292SN/A } 2962292SN/A 2972733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2981060SN/A} 2991060SN/A 3001681SN/Atemplate<class Impl> 3011060SN/Avoid 3022292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3031060SN/A{ 3041060SN/A timeBuffer = tb_ptr; 3051060SN/A 3061060SN/A // Setup wire to read information from time buffer, from commit. 3071060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3081060SN/A 3091060SN/A // Setup wire to write information back to previous stages. 3101060SN/A toRename = timeBuffer->getWire(0); 3111060SN/A 3122292SN/A toFetch = timeBuffer->getWire(0); 3132292SN/A 3141060SN/A // Instruction queue also needs main time buffer. 3151060SN/A instQueue.setTimeBuffer(tb_ptr); 3161060SN/A} 3171060SN/A 3181681SN/Atemplate<class Impl> 3191060SN/Avoid 3202292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3211060SN/A{ 3221060SN/A renameQueue = rq_ptr; 3231060SN/A 3241060SN/A // Setup wire to read information from rename queue. 3251060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3261060SN/A} 3271060SN/A 3281681SN/Atemplate<class Impl> 3291060SN/Avoid 3302292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3311060SN/A{ 3321060SN/A iewQueue = iq_ptr; 3331060SN/A 3341060SN/A // Setup wire to write instructions to commit. 3351060SN/A toCommit = iewQueue->getWire(0); 3361060SN/A} 3371060SN/A 3381681SN/Atemplate<class Impl> 3391060SN/Avoid 3406221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3411060SN/A{ 3422292SN/A activeThreads = at_ptr; 3432292SN/A 3442292SN/A ldstQueue.setActiveThreads(at_ptr); 3452292SN/A instQueue.setActiveThreads(at_ptr); 3461060SN/A} 3471060SN/A 3481681SN/Atemplate<class Impl> 3491060SN/Avoid 3502292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3511060SN/A{ 3522292SN/A scoreboard = sb_ptr; 3531060SN/A} 3541060SN/A 3552307SN/Atemplate <class Impl> 3562863Sktlim@umich.edubool 3572843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3582307SN/A{ 3592843Sktlim@umich.edu // IEW is ready to drain at any time. 3602843Sktlim@umich.edu cpu->signalDrained(); 3612863Sktlim@umich.edu return true; 3621681SN/A} 3631681SN/A 3642316SN/Atemplate <class Impl> 3651681SN/Avoid 3662843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3672843Sktlim@umich.edu{ 3682843Sktlim@umich.edu} 3692843Sktlim@umich.edu 3702843Sktlim@umich.edutemplate <class Impl> 3712843Sktlim@umich.eduvoid 3722843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3731681SN/A{ 3742348SN/A // Clear any state. 3752307SN/A switchedOut = true; 3762367SN/A assert(insts[0].empty()); 3772367SN/A assert(skidBuffer[0].empty()); 3781681SN/A 3792307SN/A instQueue.switchOut(); 3802307SN/A ldstQueue.switchOut(); 3812307SN/A fuPool->switchOut(); 3822307SN/A 3836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3846221Snate@binkert.org while (!insts[tid].empty()) 3856221Snate@binkert.org insts[tid].pop(); 3866221Snate@binkert.org while (!skidBuffer[tid].empty()) 3876221Snate@binkert.org skidBuffer[tid].pop(); 3882307SN/A } 3891681SN/A} 3901681SN/A 3912307SN/Atemplate <class Impl> 3921681SN/Avoid 3932307SN/ADefaultIEW<Impl>::takeOverFrom() 3941060SN/A{ 3952348SN/A // Reset all state. 3962307SN/A _status = Active; 3972307SN/A exeStatus = Running; 3982307SN/A wbStatus = Idle; 3992307SN/A switchedOut = false; 4001060SN/A 4012307SN/A instQueue.takeOverFrom(); 4022307SN/A ldstQueue.takeOverFrom(); 4032307SN/A fuPool->takeOverFrom(); 4041060SN/A 4052307SN/A initStage(); 4062307SN/A cpu->activityThisCycle(); 4071060SN/A 4086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4096221Snate@binkert.org dispatchStatus[tid] = Running; 4106221Snate@binkert.org stalls[tid].commit = false; 4116221Snate@binkert.org fetchRedirect[tid] = false; 4122307SN/A } 4131060SN/A 4142307SN/A updateLSQNextCycle = false; 4152307SN/A 4162873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4172307SN/A issueToExecQueue.advance(); 4181060SN/A } 4191060SN/A} 4201060SN/A 4211681SN/Atemplate<class Impl> 4221060SN/Avoid 4236221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4242107SN/A{ 4256221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4262107SN/A 4272292SN/A // Tell the IQ to start squashing. 4282292SN/A instQueue.squash(tid); 4292107SN/A 4302292SN/A // Tell the LDSTQ to start squashing. 4312326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4322292SN/A updatedQueues = true; 4332107SN/A 4342292SN/A // Clear the skid buffer in case it has any data in it. 4352935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4364632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4372935Sksewell@umich.edu 4382292SN/A while (!skidBuffer[tid].empty()) { 4392292SN/A if (skidBuffer[tid].front()->isLoad() || 4402292SN/A skidBuffer[tid].front()->isStore() ) { 4412292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4422292SN/A } 4432107SN/A 4442292SN/A toRename->iewInfo[tid].dispatched++; 4452107SN/A 4462292SN/A skidBuffer[tid].pop(); 4472292SN/A } 4482107SN/A 4492702Sktlim@umich.edu emptyRenameInsts(tid); 4502107SN/A} 4512107SN/A 4522107SN/Atemplate<class Impl> 4532107SN/Avoid 4546221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4552292SN/A{ 4567720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4577720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4582292SN/A 4597852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4607852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4617852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4627852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4637852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4642935Sksewell@umich.edu 4657852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4667852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4672292SN/A 4687852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4697852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4707852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4712292SN/A 4727852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4737852SMatt.Horsnell@arm.com } 4747852SMatt.Horsnell@arm.com 4752292SN/A} 4762292SN/A 4772292SN/Atemplate<class Impl> 4782292SN/Avoid 4796221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4802292SN/A{ 4812292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4827720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4832292SN/A 4847852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4857852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4867852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4877852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4888298Sgeoffrey.blake@arm.com TheISA::PCState pc; 4898298Sgeoffrey.blake@arm.com if (inst->isMemRef() && inst->isIndirectCtrl()) { 4908298Sgeoffrey.blake@arm.com // If an operation is a control operation as well as a memory 4918298Sgeoffrey.blake@arm.com // reference we need to use the predicted PC, not the PC+N 4928298Sgeoffrey.blake@arm.com // This instruction will verify misprediction based on predPC 4938298Sgeoffrey.blake@arm.com pc = inst->readPredTarg(); 4948298Sgeoffrey.blake@arm.com } else { 4958298Sgeoffrey.blake@arm.com pc = inst->pcState(); 4968298Sgeoffrey.blake@arm.com TheISA::advancePC(pc, inst->staticInst); 4978298Sgeoffrey.blake@arm.com } 4987852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4998137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5002292SN/A 5017852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5022292SN/A 5037852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5047852SMatt.Horsnell@arm.com } 5052292SN/A} 5062292SN/A 5072292SN/Atemplate<class Impl> 5082292SN/Avoid 5096221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5102292SN/A{ 5112292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5127720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5137852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5147852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5157852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5162292SN/A 5177852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5187852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5198137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5202292SN/A 5217852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5227852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5232292SN/A 5247852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5252292SN/A 5267852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5277852SMatt.Horsnell@arm.com } 5282292SN/A} 5292292SN/A 5302292SN/Atemplate<class Impl> 5312292SN/Avoid 5326221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5332292SN/A{ 5342292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5352292SN/A 5362292SN/A if (dispatchStatus[tid] != Blocked && 5372292SN/A dispatchStatus[tid] != Unblocking) { 5382292SN/A toRename->iewBlock[tid] = true; 5392292SN/A wroteToTimeBuffer = true; 5402292SN/A } 5412292SN/A 5422292SN/A // Add the current inputs to the skid buffer so they can be 5432292SN/A // reprocessed when this stage unblocks. 5442292SN/A skidInsert(tid); 5452292SN/A 5462292SN/A dispatchStatus[tid] = Blocked; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate<class Impl> 5502292SN/Avoid 5516221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5522292SN/A{ 5532292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5542292SN/A "buffer %u.\n",tid, tid); 5552292SN/A 5562292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5572292SN/A // Also switch status to running. 5582292SN/A if (skidBuffer[tid].empty()) { 5592292SN/A toRename->iewUnblock[tid] = true; 5602292SN/A wroteToTimeBuffer = true; 5612292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5622292SN/A dispatchStatus[tid] = Running; 5632292SN/A } 5642292SN/A} 5652292SN/A 5662292SN/Atemplate<class Impl> 5672292SN/Avoid 5682292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5691060SN/A{ 5701681SN/A instQueue.wakeDependents(inst); 5711060SN/A} 5721060SN/A 5732292SN/Atemplate<class Impl> 5742292SN/Avoid 5752292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5762292SN/A{ 5772292SN/A instQueue.rescheduleMemInst(inst); 5782292SN/A} 5791681SN/A 5801681SN/Atemplate<class Impl> 5811060SN/Avoid 5822292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5831060SN/A{ 5842292SN/A instQueue.replayMemInst(inst); 5852292SN/A} 5861060SN/A 5872292SN/Atemplate<class Impl> 5882292SN/Avoid 5892292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5902292SN/A{ 5913221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5923221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5933221Sktlim@umich.edu // being added to the queue to commit without being processed by 5943221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5953221Sktlim@umich.edu 5962292SN/A // First check the time slot that this instruction will write 5972292SN/A // to. If there are free write ports at the time, then go ahead 5982292SN/A // and write the instruction to that time. If there are not, 5992292SN/A // keep looking back to see where's the first time there's a 6002326SN/A // free slot. 6012292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6022292SN/A ++wbNumInst; 6032820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6042292SN/A ++wbCycle; 6052292SN/A wbNumInst = 0; 6062292SN/A } 6072292SN/A 6082353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6092292SN/A } 6102292SN/A 6112353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6122353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6132292SN/A // Add finished instruction to queue to commit. 6142292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6152292SN/A (*iewQueue)[wbCycle].size++; 6162292SN/A} 6172292SN/A 6182292SN/Atemplate <class Impl> 6192292SN/Aunsigned 6202292SN/ADefaultIEW<Impl>::validInstsFromRename() 6212292SN/A{ 6222292SN/A unsigned inst_count = 0; 6232292SN/A 6242292SN/A for (int i=0; i<fromRename->size; i++) { 6252731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6262292SN/A inst_count++; 6272292SN/A } 6282292SN/A 6292292SN/A return inst_count; 6302292SN/A} 6312292SN/A 6322292SN/Atemplate<class Impl> 6332292SN/Avoid 6346221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6352292SN/A{ 6362292SN/A DynInstPtr inst = NULL; 6372292SN/A 6382292SN/A while (!insts[tid].empty()) { 6392292SN/A inst = insts[tid].front(); 6402292SN/A 6412292SN/A insts[tid].pop(); 6422292SN/A 6437720Sgblack@eecs.umich.edu DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6442292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6457720Sgblack@eecs.umich.edu inst->pcState(),tid); 6462292SN/A 6472292SN/A skidBuffer[tid].push(inst); 6482292SN/A } 6492292SN/A 6502292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6512292SN/A "Skidbuffer Exceeded Max Size"); 6522292SN/A} 6532292SN/A 6542292SN/Atemplate<class Impl> 6552292SN/Aint 6562292SN/ADefaultIEW<Impl>::skidCount() 6572292SN/A{ 6582292SN/A int max=0; 6592292SN/A 6606221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6616221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6622292SN/A 6633867Sbinkertn@umich.edu while (threads != end) { 6646221Snate@binkert.org ThreadID tid = *threads++; 6653867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6662292SN/A if (max < thread_count) 6672292SN/A max = thread_count; 6682292SN/A } 6692292SN/A 6702292SN/A return max; 6712292SN/A} 6722292SN/A 6732292SN/Atemplate<class Impl> 6742292SN/Abool 6752292SN/ADefaultIEW<Impl>::skidsEmpty() 6762292SN/A{ 6776221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6786221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6792292SN/A 6803867Sbinkertn@umich.edu while (threads != end) { 6816221Snate@binkert.org ThreadID tid = *threads++; 6823867Sbinkertn@umich.edu 6833867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6842292SN/A return false; 6852292SN/A } 6862292SN/A 6872292SN/A return true; 6881062SN/A} 6891062SN/A 6901681SN/Atemplate <class Impl> 6911062SN/Avoid 6922292SN/ADefaultIEW<Impl>::updateStatus() 6931062SN/A{ 6942292SN/A bool any_unblocking = false; 6951062SN/A 6966221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6976221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6981062SN/A 6993867Sbinkertn@umich.edu while (threads != end) { 7006221Snate@binkert.org ThreadID tid = *threads++; 7011062SN/A 7022292SN/A if (dispatchStatus[tid] == Unblocking) { 7032292SN/A any_unblocking = true; 7042292SN/A break; 7052292SN/A } 7062292SN/A } 7071062SN/A 7082292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7092292SN/A // and there's no stores waiting to write back, and dispatch is not 7102292SN/A // unblocking, then there is no internal activity for the IEW stage. 7117897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7122292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7132292SN/A !ldstQueue.willWB() && !any_unblocking) { 7142292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7151062SN/A 7162292SN/A deactivateStage(); 7171062SN/A 7182292SN/A _status = Inactive; 7192292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7202292SN/A ldstQueue.willWB() || 7212292SN/A any_unblocking)) { 7222292SN/A // Otherwise there is internal activity. Set to active. 7232292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7241062SN/A 7252292SN/A activateStage(); 7261062SN/A 7272292SN/A _status = Active; 7281062SN/A } 7291062SN/A} 7301062SN/A 7311681SN/Atemplate <class Impl> 7321062SN/Avoid 7332292SN/ADefaultIEW<Impl>::resetEntries() 7341062SN/A{ 7352292SN/A instQueue.resetEntries(); 7362292SN/A ldstQueue.resetEntries(); 7372292SN/A} 7381062SN/A 7392292SN/Atemplate <class Impl> 7402292SN/Avoid 7416221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7422292SN/A{ 7432292SN/A if (fromCommit->commitBlock[tid]) { 7442292SN/A stalls[tid].commit = true; 7452292SN/A } 7461062SN/A 7472292SN/A if (fromCommit->commitUnblock[tid]) { 7482292SN/A assert(stalls[tid].commit); 7492292SN/A stalls[tid].commit = false; 7502292SN/A } 7512292SN/A} 7522292SN/A 7532292SN/Atemplate <class Impl> 7542292SN/Abool 7556221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7562292SN/A{ 7572292SN/A bool ret_val(false); 7582292SN/A 7592292SN/A if (stalls[tid].commit) { 7602292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7612292SN/A ret_val = true; 7622292SN/A } else if (instQueue.isFull(tid)) { 7632292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7642292SN/A ret_val = true; 7652292SN/A } else if (ldstQueue.isFull(tid)) { 7662292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7672292SN/A 7682292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7692292SN/A 7702292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7712292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7722292SN/A } 7732292SN/A 7742292SN/A if (ldstQueue.numStores(tid) > 0) { 7752292SN/A 7762292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7772292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7782292SN/A } 7792292SN/A 7802292SN/A ret_val = true; 7812292SN/A } else if (ldstQueue.isStalled(tid)) { 7822292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7832292SN/A ret_val = true; 7842292SN/A } 7852292SN/A 7862292SN/A return ret_val; 7872292SN/A} 7882292SN/A 7892292SN/Atemplate <class Impl> 7902292SN/Avoid 7916221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7922292SN/A{ 7932292SN/A // Check if there's a squash signal, squash if there is 7942292SN/A // Check stall signals, block if there is. 7952292SN/A // If status was Blocked 7962292SN/A // if so then go to unblocking 7972292SN/A // If status was Squashing 7982292SN/A // check if squashing is not high. Switch to running this cycle. 7992292SN/A 8002292SN/A readStallSignals(tid); 8012292SN/A 8022292SN/A if (fromCommit->commitInfo[tid].squash) { 8032292SN/A squash(tid); 8042292SN/A 8052292SN/A if (dispatchStatus[tid] == Blocked || 8062292SN/A dispatchStatus[tid] == Unblocking) { 8072292SN/A toRename->iewUnblock[tid] = true; 8082292SN/A wroteToTimeBuffer = true; 8092292SN/A } 8102292SN/A 8112292SN/A dispatchStatus[tid] = Squashing; 8122292SN/A fetchRedirect[tid] = false; 8132292SN/A return; 8142292SN/A } 8152292SN/A 8162292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8172702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8182292SN/A 8192292SN/A dispatchStatus[tid] = Squashing; 8202702Sktlim@umich.edu emptyRenameInsts(tid); 8212702Sktlim@umich.edu wroteToTimeBuffer = true; 8222292SN/A return; 8232292SN/A } 8242292SN/A 8252292SN/A if (checkStall(tid)) { 8262292SN/A block(tid); 8272292SN/A dispatchStatus[tid] = Blocked; 8282292SN/A return; 8292292SN/A } 8302292SN/A 8312292SN/A if (dispatchStatus[tid] == Blocked) { 8322292SN/A // Status from previous cycle was blocked, but there are no more stall 8332292SN/A // conditions. Switch over to unblocking. 8342292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8352292SN/A tid); 8362292SN/A 8372292SN/A dispatchStatus[tid] = Unblocking; 8382292SN/A 8392292SN/A unblock(tid); 8402292SN/A 8412292SN/A return; 8422292SN/A } 8432292SN/A 8442292SN/A if (dispatchStatus[tid] == Squashing) { 8452292SN/A // Switch status to running if rename isn't being told to block or 8462292SN/A // squash this cycle. 8472292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8482292SN/A tid); 8492292SN/A 8502292SN/A dispatchStatus[tid] = Running; 8512292SN/A 8522292SN/A return; 8532292SN/A } 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Avoid 8582292SN/ADefaultIEW<Impl>::sortInsts() 8592292SN/A{ 8602292SN/A int insts_from_rename = fromRename->size; 8612326SN/A#ifdef DEBUG 8626221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8636221Snate@binkert.org assert(insts[tid].empty()); 8642326SN/A#endif 8652292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8662292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8672292SN/A } 8682292SN/A} 8692292SN/A 8702292SN/Atemplate <class Impl> 8712292SN/Avoid 8726221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8732702Sktlim@umich.edu{ 8744632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8752935Sksewell@umich.edu 8762702Sktlim@umich.edu while (!insts[tid].empty()) { 8772935Sksewell@umich.edu 8782702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8792702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8802702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8812702Sktlim@umich.edu } 8822702Sktlim@umich.edu 8832702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8842702Sktlim@umich.edu 8852702Sktlim@umich.edu insts[tid].pop(); 8862702Sktlim@umich.edu } 8872702Sktlim@umich.edu} 8882702Sktlim@umich.edu 8892702Sktlim@umich.edutemplate <class Impl> 8902702Sktlim@umich.eduvoid 8912292SN/ADefaultIEW<Impl>::wakeCPU() 8922292SN/A{ 8932292SN/A cpu->wakeCPU(); 8942292SN/A} 8952292SN/A 8962292SN/Atemplate <class Impl> 8972292SN/Avoid 8982292SN/ADefaultIEW<Impl>::activityThisCycle() 8992292SN/A{ 9002292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9012292SN/A cpu->activityThisCycle(); 9022292SN/A} 9032292SN/A 9042292SN/Atemplate <class Impl> 9052292SN/Ainline void 9062292SN/ADefaultIEW<Impl>::activateStage() 9072292SN/A{ 9082292SN/A DPRINTF(Activity, "Activating stage.\n"); 9092733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9102292SN/A} 9112292SN/A 9122292SN/Atemplate <class Impl> 9132292SN/Ainline void 9142292SN/ADefaultIEW<Impl>::deactivateStage() 9152292SN/A{ 9162292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9172733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9182292SN/A} 9192292SN/A 9202292SN/Atemplate<class Impl> 9212292SN/Avoid 9226221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9232292SN/A{ 9242292SN/A // If status is Running or idle, 9252292SN/A // call dispatchInsts() 9262292SN/A // If status is Unblocking, 9272292SN/A // buffer any instructions coming from rename 9282292SN/A // continue trying to empty skid buffer 9292292SN/A // check if stall conditions have passed 9302292SN/A 9312292SN/A if (dispatchStatus[tid] == Blocked) { 9322292SN/A ++iewBlockCycles; 9332292SN/A 9342292SN/A } else if (dispatchStatus[tid] == Squashing) { 9352292SN/A ++iewSquashCycles; 9362292SN/A } 9372292SN/A 9382292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9392292SN/A // will allow, as long as it is not currently blocked. 9402292SN/A if (dispatchStatus[tid] == Running || 9412292SN/A dispatchStatus[tid] == Idle) { 9422292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9432292SN/A "dispatch.\n", tid); 9442292SN/A 9452292SN/A dispatchInsts(tid); 9462292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9472292SN/A // Make sure that the skid buffer has something in it if the 9482292SN/A // status is unblocking. 9492292SN/A assert(!skidsEmpty()); 9502292SN/A 9512292SN/A // If the status was unblocking, then instructions from the skid 9522292SN/A // buffer were used. Remove those instructions and handle 9532292SN/A // the rest of unblocking. 9542292SN/A dispatchInsts(tid); 9552292SN/A 9562292SN/A ++iewUnblockCycles; 9572292SN/A 9585215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9592292SN/A // Add the current inputs to the skid buffer so they can be 9602292SN/A // reprocessed when this stage unblocks. 9612292SN/A skidInsert(tid); 9622292SN/A } 9632292SN/A 9642292SN/A unblock(tid); 9652292SN/A } 9662292SN/A} 9672292SN/A 9682292SN/Atemplate <class Impl> 9692292SN/Avoid 9706221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9712292SN/A{ 9722292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9732292SN/A // otherwise. 9742292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9752292SN/A dispatchStatus[tid] == Unblocking ? 9762292SN/A skidBuffer[tid] : insts[tid]; 9772292SN/A 9782292SN/A int insts_to_add = insts_to_dispatch.size(); 9792292SN/A 9802292SN/A DynInstPtr inst; 9812292SN/A bool add_to_iq = false; 9822292SN/A int dis_num_inst = 0; 9832292SN/A 9842292SN/A // Loop through the instructions, putting them in the instruction 9852292SN/A // queue. 9862292SN/A for ( ; dis_num_inst < insts_to_add && 9872820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9882292SN/A ++dis_num_inst) 9892292SN/A { 9902292SN/A inst = insts_to_dispatch.front(); 9912292SN/A 9922292SN/A if (dispatchStatus[tid] == Unblocking) { 9932292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9942292SN/A "buffer\n", tid); 9952292SN/A } 9962292SN/A 9972292SN/A // Make sure there's a valid instruction there. 9982292SN/A assert(inst); 9992292SN/A 10007720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10012292SN/A "IQ.\n", 10027720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10032292SN/A 10042292SN/A // Be sure to mark these instructions as ready so that the 10052292SN/A // commit stage can go ahead and execute them, and mark 10062292SN/A // them as issued so the IQ doesn't reprocess them. 10072292SN/A 10082292SN/A // Check for squashed instructions. 10092292SN/A if (inst->isSquashed()) { 10102292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10112292SN/A "not adding to IQ.\n", tid); 10122292SN/A 10132292SN/A ++iewDispSquashedInsts; 10142292SN/A 10152292SN/A insts_to_dispatch.pop(); 10162292SN/A 10172292SN/A //Tell Rename That An Instruction has been processed 10182292SN/A if (inst->isLoad() || inst->isStore()) { 10192292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10202292SN/A } 10212292SN/A toRename->iewInfo[tid].dispatched++; 10222292SN/A 10232292SN/A continue; 10242292SN/A } 10252292SN/A 10262292SN/A // Check for full conditions. 10272292SN/A if (instQueue.isFull(tid)) { 10282292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10292292SN/A 10302292SN/A // Call function to start blocking. 10312292SN/A block(tid); 10322292SN/A 10332292SN/A // Set unblock to false. Special case where we are using 10342292SN/A // skidbuffer (unblocking) instructions but then we still 10352292SN/A // get full in the IQ. 10362292SN/A toRename->iewUnblock[tid] = false; 10372292SN/A 10382292SN/A ++iewIQFullEvents; 10392292SN/A break; 10402292SN/A } else if (ldstQueue.isFull(tid)) { 10412292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10422292SN/A 10432292SN/A // Call function to start blocking. 10442292SN/A block(tid); 10452292SN/A 10462292SN/A // Set unblock to false. Special case where we are using 10472292SN/A // skidbuffer (unblocking) instructions but then we still 10482292SN/A // get full in the IQ. 10492292SN/A toRename->iewUnblock[tid] = false; 10502292SN/A 10512292SN/A ++iewLSQFullEvents; 10522292SN/A break; 10532292SN/A } 10542292SN/A 10552292SN/A // Otherwise issue the instruction just fine. 10562292SN/A if (inst->isLoad()) { 10572292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10582292SN/A "encountered, adding to LSQ.\n", tid); 10592292SN/A 10602292SN/A // Reserve a spot in the load store queue for this 10612292SN/A // memory access. 10622292SN/A ldstQueue.insertLoad(inst); 10632292SN/A 10642292SN/A ++iewDispLoadInsts; 10652292SN/A 10662292SN/A add_to_iq = true; 10672292SN/A 10682292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10692292SN/A } else if (inst->isStore()) { 10702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10712292SN/A "encountered, adding to LSQ.\n", tid); 10722292SN/A 10732292SN/A ldstQueue.insertStore(inst); 10742292SN/A 10752292SN/A ++iewDispStoreInsts; 10762292SN/A 10772336SN/A if (inst->isStoreConditional()) { 10782336SN/A // Store conditionals need to be set as "canCommit()" 10792336SN/A // so that commit can process them when they reach the 10802336SN/A // head of commit. 10812348SN/A // @todo: This is somewhat specific to Alpha. 10822292SN/A inst->setCanCommit(); 10832292SN/A instQueue.insertNonSpec(inst); 10842292SN/A add_to_iq = false; 10852292SN/A 10862292SN/A ++iewDispNonSpecInsts; 10872292SN/A } else { 10882292SN/A add_to_iq = true; 10892292SN/A } 10902292SN/A 10912292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10922292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10932326SN/A // Same as non-speculative stores. 10942292SN/A inst->setCanCommit(); 10952292SN/A instQueue.insertBarrier(inst); 10962292SN/A add_to_iq = false; 10972292SN/A } else if (inst->isNop()) { 10982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10992292SN/A "skipping.\n", tid); 11002292SN/A 11012292SN/A inst->setIssued(); 11022292SN/A inst->setExecuted(); 11032292SN/A inst->setCanCommit(); 11042292SN/A 11052326SN/A instQueue.recordProducer(inst); 11062292SN/A 11072727Sktlim@umich.edu iewExecutedNop[tid]++; 11082301SN/A 11092292SN/A add_to_iq = false; 11102292SN/A } else if (inst->isExecuted()) { 11112292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11122292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11132292SN/A "skipping.\n"); 11142292SN/A 11152292SN/A inst->setIssued(); 11162292SN/A inst->setCanCommit(); 11172292SN/A 11182326SN/A instQueue.recordProducer(inst); 11192292SN/A 11202292SN/A add_to_iq = false; 11212292SN/A } else { 11222292SN/A add_to_iq = true; 11232292SN/A } 11244033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11254033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11264033Sktlim@umich.edu "encountered, skipping.\n", tid); 11274033Sktlim@umich.edu 11284033Sktlim@umich.edu // Same as non-speculative stores. 11294033Sktlim@umich.edu inst->setCanCommit(); 11304033Sktlim@umich.edu 11314033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11324033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11334033Sktlim@umich.edu 11344033Sktlim@umich.edu ++iewDispNonSpecInsts; 11354033Sktlim@umich.edu 11364033Sktlim@umich.edu add_to_iq = false; 11374033Sktlim@umich.edu } 11382292SN/A 11392292SN/A // If the instruction queue is not full, then add the 11402292SN/A // instruction. 11412292SN/A if (add_to_iq) { 11422292SN/A instQueue.insert(inst); 11432292SN/A } 11442292SN/A 11452292SN/A insts_to_dispatch.pop(); 11462292SN/A 11472292SN/A toRename->iewInfo[tid].dispatched++; 11482292SN/A 11492292SN/A ++iewDispatchedInsts; 11502292SN/A } 11512292SN/A 11522292SN/A if (!insts_to_dispatch.empty()) { 11532935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11542292SN/A block(tid); 11552292SN/A toRename->iewUnblock[tid] = false; 11562292SN/A } 11572292SN/A 11582292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11592292SN/A dispatchStatus[tid] = Running; 11602292SN/A 11612292SN/A updatedQueues = true; 11622292SN/A } 11632292SN/A 11642292SN/A dis_num_inst = 0; 11652292SN/A} 11662292SN/A 11672292SN/Atemplate <class Impl> 11682292SN/Avoid 11692292SN/ADefaultIEW<Impl>::printAvailableInsts() 11702292SN/A{ 11712292SN/A int inst = 0; 11722292SN/A 11732980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11742292SN/A 11752292SN/A while (fromIssue->insts[inst]) { 11762292SN/A 11772980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11782292SN/A 11797720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11802292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11812292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11822292SN/A 11832292SN/A inst++; 11842292SN/A 11852292SN/A } 11862292SN/A 11872980Sgblack@eecs.umich.edu std::cout << "\n"; 11882292SN/A} 11892292SN/A 11902292SN/Atemplate <class Impl> 11912292SN/Avoid 11922292SN/ADefaultIEW<Impl>::executeInsts() 11932292SN/A{ 11942292SN/A wbNumInst = 0; 11952292SN/A wbCycle = 0; 11962292SN/A 11976221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11986221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11992292SN/A 12003867Sbinkertn@umich.edu while (threads != end) { 12016221Snate@binkert.org ThreadID tid = *threads++; 12022292SN/A fetchRedirect[tid] = false; 12032292SN/A } 12042292SN/A 12052698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12067599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12072698Sktlim@umich.edu// printAvailableInsts(); 12081062SN/A 12091062SN/A // Execute/writeback any instructions that are available. 12102333SN/A int insts_to_execute = fromIssue->size; 12112292SN/A int inst_num = 0; 12122333SN/A for (; inst_num < insts_to_execute; 12132326SN/A ++inst_num) { 12141062SN/A 12152292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12161062SN/A 12172333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12181062SN/A 12197720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12207720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12211062SN/A 12221062SN/A // Check if the instruction is squashed; if so then skip it 12231062SN/A if (inst->isSquashed()) { 12248315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12258315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12268315Sgeoffrey.blake@arm.com inst->seqNum); 12271062SN/A 12281062SN/A // Consider this instruction executed so that commit can go 12291062SN/A // ahead and retire the instruction. 12301062SN/A inst->setExecuted(); 12311062SN/A 12322292SN/A // Not sure if I should set this here or just let commit try to 12332292SN/A // commit any squashed instructions. I like the latter a bit more. 12342292SN/A inst->setCanCommit(); 12351062SN/A 12361062SN/A ++iewExecSquashedInsts; 12371062SN/A 12382820Sktlim@umich.edu decrWb(inst->seqNum); 12391062SN/A continue; 12401062SN/A } 12411062SN/A 12422292SN/A Fault fault = NoFault; 12431062SN/A 12441062SN/A // Execute instruction. 12451062SN/A // Note that if the instruction faults, it will be handled 12461062SN/A // at the commit stage. 12477850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12482292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12491062SN/A "reference.\n"); 12501062SN/A 12511062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12521062SN/A if (inst->isLoad()) { 12532292SN/A // Loads will mark themselves as executed, and their writeback 12542292SN/A // event adds the instruction to the queue to commit 12552292SN/A fault = ldstQueue.executeLoad(inst); 12567944SGiacomo.Gabrielli@arm.com 12577944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12587944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12597944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12607944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12617944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12627944SGiacomo.Gabrielli@arm.com "load.\n"); 12637944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12647944SGiacomo.Gabrielli@arm.com continue; 12657944SGiacomo.Gabrielli@arm.com } 12667944SGiacomo.Gabrielli@arm.com 12677850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12688073SAli.Saidi@ARM.com inst->fault = NoFault; 12697850SMatt.Horsnell@arm.com } 12701062SN/A } else if (inst->isStore()) { 12712367SN/A fault = ldstQueue.executeStore(inst); 12721062SN/A 12737944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12747944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12757944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12767944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12777944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12787944SGiacomo.Gabrielli@arm.com "store.\n"); 12797944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12807944SGiacomo.Gabrielli@arm.com continue; 12817944SGiacomo.Gabrielli@arm.com } 12827944SGiacomo.Gabrielli@arm.com 12832292SN/A // If the store had a fault then it may not have a mem req 12847782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12857782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12867782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12877782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12882367SN/A // Send this instruction to commit, also make sure iew stage 12892367SN/A // realizes there is activity. 12902367SN/A inst->setExecuted(); 12912367SN/A instToCommit(inst); 12922367SN/A activityThisCycle(); 12932292SN/A } 12942326SN/A 12952326SN/A // Store conditionals will mark themselves as 12962326SN/A // executed, and their writeback event will add the 12972326SN/A // instruction to the queue to commit. 12981062SN/A } else { 12992292SN/A panic("Unexpected memory type!\n"); 13001062SN/A } 13011062SN/A 13021062SN/A } else { 13037847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13047847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13057847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13067847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13077847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13087847Sminkyu.jeong@arm.com inst->execute(); 13097848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 13107848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13117847Sminkyu.jeong@arm.com } 13121062SN/A 13132292SN/A inst->setExecuted(); 13142292SN/A 13152292SN/A instToCommit(inst); 13161062SN/A } 13171062SN/A 13182301SN/A updateExeInstStats(inst); 13191681SN/A 13202326SN/A // Check if branch prediction was correct, if not then we need 13212326SN/A // to tell commit to squash in flight instructions. Only 13222326SN/A // handle this if there hasn't already been something that 13232107SN/A // redirects fetch in this group of instructions. 13241681SN/A 13252292SN/A // This probably needs to prioritize the redirects if a different 13262292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13272292SN/A // instruction first, so the branch resolution order will be correct. 13286221Snate@binkert.org ThreadID tid = inst->threadNumber; 13291062SN/A 13303732Sktlim@umich.edu if (!fetchRedirect[tid] || 13317852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13323732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13331062SN/A 13347856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13357856SMatt.Horsnell@arm.com // that have not been executed. 13367856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13377856SMatt.Horsnell@arm.com 13387856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13392292SN/A fetchRedirect[tid] = true; 13401062SN/A 13412292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13426036Sksewell@umich.edu DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13437720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 13447720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13457720Sgblack@eecs.umich.edu inst->pcState(), inst->nextInstAddr()); 13461062SN/A // If incorrect, then signal the ROB that it must be squashed. 13472292SN/A squashDueToBranch(inst, tid); 13481062SN/A 13493795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13501062SN/A predictedTakenIncorrect++; 13512292SN/A } else { 13522292SN/A predictedNotTakenIncorrect++; 13531062SN/A } 13542292SN/A } else if (ldstQueue.violation(tid)) { 13554033Sktlim@umich.edu assert(inst->isMemRef()); 13562326SN/A // If there was an ordering violation, then get the 13572326SN/A // DynInst that caused the violation. Note that this 13582292SN/A // clears the violation signal. 13592292SN/A DynInstPtr violator; 13602292SN/A violator = ldstQueue.getMemDepViolator(tid); 13611062SN/A 13627720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13637720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13647720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13657720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13667720Sgblack@eecs.umich.edu 13673732Sktlim@umich.edu fetchRedirect[tid] = true; 13683732Sktlim@umich.edu 13691062SN/A // Tell the instruction queue that a violation has occured. 13701062SN/A instQueue.violation(inst, violator); 13711062SN/A 13721062SN/A // Squash. 13732292SN/A squashDueToMemOrder(inst,tid); 13741062SN/A 13751062SN/A ++memOrderViolationEvents; 13762292SN/A } else if (ldstQueue.loadBlocked(tid) && 13772292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13782292SN/A fetchRedirect[tid] = true; 13792292SN/A 13802292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13817720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13827720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13832292SN/A 13842292SN/A squashDueToMemBlocked(inst, tid); 13851062SN/A } 13864033Sktlim@umich.edu } else { 13874033Sktlim@umich.edu // Reset any state associated with redirects that will not 13884033Sktlim@umich.edu // be used. 13894033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13904033Sktlim@umich.edu assert(inst->isMemRef()); 13914033Sktlim@umich.edu 13924033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13934033Sktlim@umich.edu 13944033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13957720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13967720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 13977720Sgblack@eecs.umich.edu inst->physEffAddr); 13984033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13994033Sktlim@umich.edu "already squashing\n"); 14004033Sktlim@umich.edu 14014033Sktlim@umich.edu ++memOrderViolationEvents; 14024033Sktlim@umich.edu } 14034033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14044033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14054033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14067720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14077720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14084033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14094033Sktlim@umich.edu "already squashing\n"); 14104033Sktlim@umich.edu 14114033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14124033Sktlim@umich.edu } 14134033Sktlim@umich.edu 14141062SN/A } 14151062SN/A } 14162292SN/A 14172348SN/A // Update and record activity if we processed any instructions. 14182292SN/A if (inst_num) { 14192292SN/A if (exeStatus == Idle) { 14202292SN/A exeStatus = Running; 14212292SN/A } 14222292SN/A 14232292SN/A updatedQueues = true; 14242292SN/A 14252292SN/A cpu->activityThisCycle(); 14262292SN/A } 14272292SN/A 14282292SN/A // Need to reset this in case a writeback event needs to write into the 14292292SN/A // iew queue. That way the writeback event will write into the correct 14302292SN/A // spot in the queue. 14312292SN/A wbNumInst = 0; 14327852SMatt.Horsnell@arm.com 14332107SN/A} 14342107SN/A 14352292SN/Atemplate <class Impl> 14362107SN/Avoid 14372292SN/ADefaultIEW<Impl>::writebackInsts() 14382107SN/A{ 14392326SN/A // Loop through the head of the time buffer and wake any 14402326SN/A // dependents. These instructions are about to write back. Also 14412326SN/A // mark scoreboard that this instruction is finally complete. 14422326SN/A // Either have IEW have direct access to scoreboard, or have this 14432326SN/A // as part of backwards communication. 14443958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14452292SN/A toCommit->insts[inst_num]; inst_num++) { 14462107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14476221Snate@binkert.org ThreadID tid = inst->threadNumber; 14482107SN/A 14497720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14507720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14512107SN/A 14522301SN/A iewInstsToCommit[tid]++; 14532301SN/A 14542292SN/A // Some instructions will be sent to commit without having 14552292SN/A // executed because they need commit to handle them. 14562292SN/A // E.g. Uncached loads have not actually executed when they 14572292SN/A // are first sent to commit. Instead commit must tell the LSQ 14582292SN/A // when it's ready to execute the uncached load. 14592367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14602301SN/A int dependents = instQueue.wakeDependents(inst); 14612107SN/A 14622292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14632292SN/A //mark as Ready 14642292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14652292SN/A inst->renamedDestRegIdx(i)); 14662292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14672107SN/A } 14682301SN/A 14692348SN/A if (dependents) { 14702348SN/A producerInst[tid]++; 14712348SN/A consumerInst[tid]+= dependents; 14722348SN/A } 14732326SN/A writebackCount[tid]++; 14742107SN/A } 14752820Sktlim@umich.edu 14762820Sktlim@umich.edu decrWb(inst->seqNum); 14772107SN/A } 14781060SN/A} 14791060SN/A 14801681SN/Atemplate<class Impl> 14811060SN/Avoid 14822292SN/ADefaultIEW<Impl>::tick() 14831060SN/A{ 14842292SN/A wbNumInst = 0; 14852292SN/A wbCycle = 0; 14861060SN/A 14872292SN/A wroteToTimeBuffer = false; 14882292SN/A updatedQueues = false; 14891060SN/A 14902292SN/A sortInsts(); 14911060SN/A 14922326SN/A // Free function units marked as being freed this cycle. 14932326SN/A fuPool->processFreeUnits(); 14941062SN/A 14956221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14966221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14971060SN/A 14982326SN/A // Check stall and squash signals, dispatch any instructions. 14993867Sbinkertn@umich.edu while (threads != end) { 15006221Snate@binkert.org ThreadID tid = *threads++; 15011060SN/A 15022292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15031060SN/A 15042292SN/A checkSignalsAndUpdate(tid); 15052292SN/A dispatch(tid); 15061060SN/A } 15071060SN/A 15082292SN/A if (exeStatus != Squashing) { 15092292SN/A executeInsts(); 15101060SN/A 15112292SN/A writebackInsts(); 15122292SN/A 15132292SN/A // Have the instruction queue try to schedule any ready instructions. 15142292SN/A // (In actuality, this scheduling is for instructions that will 15152292SN/A // be executed next cycle.) 15162292SN/A instQueue.scheduleReadyInsts(); 15172292SN/A 15182292SN/A // Also should advance its own time buffers if the stage ran. 15192292SN/A // Not the best place for it, but this works (hopefully). 15202292SN/A issueToExecQueue.advance(); 15212292SN/A } 15222292SN/A 15232292SN/A bool broadcast_free_entries = false; 15242292SN/A 15252292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15262292SN/A exeStatus = Idle; 15272292SN/A updateLSQNextCycle = false; 15282292SN/A 15292292SN/A broadcast_free_entries = true; 15302292SN/A } 15312292SN/A 15322292SN/A // Writeback any stores using any leftover bandwidth. 15331681SN/A ldstQueue.writebackStores(); 15341681SN/A 15351061SN/A // Check the committed load/store signals to see if there's a load 15361061SN/A // or store to commit. Also check if it's being told to execute a 15371061SN/A // nonspeculative instruction. 15381681SN/A // This is pretty inefficient... 15392292SN/A 15403867Sbinkertn@umich.edu threads = activeThreads->begin(); 15413867Sbinkertn@umich.edu while (threads != end) { 15426221Snate@binkert.org ThreadID tid = (*threads++); 15432292SN/A 15442292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15452292SN/A 15462348SN/A // Update structures based on instructions committed. 15472292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15482292SN/A !fromCommit->commitInfo[tid].squash && 15492292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15502292SN/A 15512292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15522292SN/A 15532292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15542292SN/A 15552292SN/A updateLSQNextCycle = true; 15562292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15572292SN/A } 15582292SN/A 15592292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15602292SN/A 15612292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15622292SN/A if (fromCommit->commitInfo[tid].uncached) { 15632292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15644033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15652292SN/A } else { 15662292SN/A instQueue.scheduleNonSpec( 15672292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15682292SN/A } 15692292SN/A } 15702292SN/A 15712292SN/A if (broadcast_free_entries) { 15722292SN/A toFetch->iewInfo[tid].iqCount = 15732292SN/A instQueue.getCount(tid); 15742292SN/A toFetch->iewInfo[tid].ldstqCount = 15752292SN/A ldstQueue.getCount(tid); 15762292SN/A 15772292SN/A toRename->iewInfo[tid].usedIQ = true; 15782292SN/A toRename->iewInfo[tid].freeIQEntries = 15792292SN/A instQueue.numFreeEntries(); 15802292SN/A toRename->iewInfo[tid].usedLSQ = true; 15812292SN/A toRename->iewInfo[tid].freeLSQEntries = 15822292SN/A ldstQueue.numFreeEntries(tid); 15832292SN/A 15842292SN/A wroteToTimeBuffer = true; 15852292SN/A } 15862292SN/A 15872292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15882292SN/A tid, toRename->iewInfo[tid].dispatched); 15891061SN/A } 15901061SN/A 15912292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15922292SN/A "LSQ has %i free entries.\n", 15932292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15942292SN/A ldstQueue.numFreeEntries()); 15952292SN/A 15962292SN/A updateStatus(); 15972292SN/A 15982292SN/A if (wroteToTimeBuffer) { 15992292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16002292SN/A cpu->activityThisCycle(); 16011061SN/A } 16021060SN/A} 16031060SN/A 16042301SN/Atemplate <class Impl> 16051060SN/Avoid 16062301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16071060SN/A{ 16086221Snate@binkert.org ThreadID tid = inst->threadNumber; 16091060SN/A 16102301SN/A // 16112301SN/A // Pick off the software prefetches 16122301SN/A // 16132301SN/A#ifdef TARGET_ALPHA 16142301SN/A if (inst->isDataPrefetch()) 16156221Snate@binkert.org iewExecutedSwp[tid]++; 16162301SN/A else 16172727Sktlim@umich.edu iewIewExecutedcutedInsts++; 16182301SN/A#else 16192669Sktlim@umich.edu iewExecutedInsts++; 16202301SN/A#endif 16211060SN/A 16222301SN/A // 16232301SN/A // Control operations 16242301SN/A // 16252301SN/A if (inst->isControl()) 16266221Snate@binkert.org iewExecutedBranches[tid]++; 16271060SN/A 16282301SN/A // 16292301SN/A // Memory operations 16302301SN/A // 16312301SN/A if (inst->isMemRef()) { 16326221Snate@binkert.org iewExecutedRefs[tid]++; 16331060SN/A 16342301SN/A if (inst->isLoad()) { 16356221Snate@binkert.org iewExecLoadInsts[tid]++; 16361060SN/A } 16371060SN/A } 16381060SN/A} 16397598Sminkyu.jeong@arm.com 16407598Sminkyu.jeong@arm.comtemplate <class Impl> 16417598Sminkyu.jeong@arm.comvoid 16427598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16437598Sminkyu.jeong@arm.com{ 16447598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16457598Sminkyu.jeong@arm.com 16467598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16477852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16487598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16497598Sminkyu.jeong@arm.com 16507598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16517598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16527598Sminkyu.jeong@arm.com 16537598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16547598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16557720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16567598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16577720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16587720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16597598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16607598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16617598Sminkyu.jeong@arm.com 16627598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16637598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16647598Sminkyu.jeong@arm.com } else { 16657598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16667598Sminkyu.jeong@arm.com } 16677598Sminkyu.jeong@arm.com } 16687598Sminkyu.jeong@arm.com } 16697598Sminkyu.jeong@arm.com} 1670