iew_impl.hh revision 8232
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010 ARM Limited 39913Ssteve.reinhardt@amd.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 147854SAli.Saidi@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 152329SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412665Ssaidi@eecs.umich.edu */ 422935Sksewell@umich.edu 431689SN/A// @todo: Fix the instantaneous communication among all the stages within 441689SN/A// iew. There's a clear delay between issue and execute, yet backwards 459944Smatt.horsnell@ARM.com// communication happens simultaneously. 469944Smatt.horsnell@ARM.com 479944Smatt.horsnell@ARM.com#include <queue> 481060SN/A 491060SN/A#include "arch/utility.hh" 503773Sgblack@eecs.umich.edu#include "config/the_isa.hh" 516329Sgblack@eecs.umich.edu#include "cpu/o3/fu_pool.hh" 526658Snate@binkert.org#include "cpu/o3/iew.hh" 531717SN/A#include "cpu/timebuf.hh" 549913Ssteve.reinhardt@amd.com#include "debug/Activity.hh" 558232Snate@binkert.org#include "debug/Decode.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 579527SMatt.Horsnell@arm.com#include "params/DerivO3CPU.hh" 585529Snate@binkert.org 591060SN/Ausing namespace std; 606221Snate@binkert.org 616221Snate@binkert.orgtemplate<class Impl> 621061SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 635529Snate@binkert.org : issueToExecQueue(params->backComSize, params->forwardComSize), 644329Sktlim@umich.edu cpu(_cpu), 654329Sktlim@umich.edu instQueue(_cpu, this, params), 662292SN/A ldstQueue(_cpu, this, params), 672292SN/A fuPool(params->fuPool), 682292SN/A commitToIEWDelay(params->commitToIEWDelay), 692292SN/A renameToIEWDelay(params->renameToIEWDelay), 7012109SRekai.GonzalezAlberquilla@arm.com issueToExecuteDelay(params->issueToExecuteDelay), 711060SN/A dispatchWidth(params->dispatchWidth), 7210172Sdam.sunwoo@arm.com issueWidth(params->issueWidth), 7310172Sdam.sunwoo@arm.com wbOutstanding(0), 7410172Sdam.sunwoo@arm.com wbWidth(params->wbWidth), 7510172Sdam.sunwoo@arm.com numThreads(params->numThreads), 7610172Sdam.sunwoo@arm.com switchedOut(false) 772292SN/A{ 7810328Smitch.hayenga@arm.com _status = Active; 792292SN/A exeStatus = Running; 802292SN/A wbStatus = Idle; 812292SN/A 822292SN/A // Setup wire to read instructions coming from issue. 832292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 842292SN/A 852292SN/A // Instruction queue needs the queue between issue and execute. 861060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 871060SN/A 881061SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 891060SN/A dispatchStatus[tid] = Running; 902292SN/A stalls[tid].commit = false; 911062SN/A fetchRedirect[tid] = false; 921062SN/A } 938240Snate@binkert.org 941062SN/A wbMax = wbWidth * params->wbDepth; 951062SN/A 961062SN/A updateLSQNextCycle = false; 978240Snate@binkert.org 981062SN/A ableToIssue = true; 991062SN/A 1001062SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1018240Snate@binkert.org} 1021062SN/A 1031062SN/Atemplate <class Impl> 1042301SN/Astd::string 1058240Snate@binkert.orgDefaultIEW<Impl>::name() const 1062301SN/A{ 1072301SN/A return cpu->name() + ".iew"; 1082292SN/A} 1098240Snate@binkert.org 1102292SN/Atemplate <class Impl> 1112292SN/Avoid 1121062SN/ADefaultIEW<Impl>::regStats() 1138240Snate@binkert.org{ 1141062SN/A using namespace Stats; 1151062SN/A 1161062SN/A instQueue.regStats(); 1178240Snate@binkert.org ldstQueue.regStats(); 1181062SN/A 1191062SN/A iewIdleCycles 1201062SN/A .name(name() + ".iewIdleCycles") 1218240Snate@binkert.org .desc("Number of cycles IEW is idle"); 1221062SN/A 1231062SN/A iewSquashCycles 1241062SN/A .name(name() + ".iewSquashCycles") 1258240Snate@binkert.org .desc("Number of cycles IEW is squashing"); 1262292SN/A 1271062SN/A iewBlockCycles 1281062SN/A .name(name() + ".iewBlockCycles") 1298240Snate@binkert.org .desc("Number of cycles IEW is blocking"); 1302292SN/A 1311062SN/A iewUnblockCycles 13210239Sbinhpham@cs.rutgers.edu .name(name() + ".iewUnblockCycles") 13310239Sbinhpham@cs.rutgers.edu .desc("Number of cycles IEW is unblocking"); 13410239Sbinhpham@cs.rutgers.edu 13510239Sbinhpham@cs.rutgers.edu iewDispatchedInsts 13610239Sbinhpham@cs.rutgers.edu .name(name() + ".iewDispatchedInsts") 13710239Sbinhpham@cs.rutgers.edu .desc("Number of instructions dispatched to IQ"); 13810239Sbinhpham@cs.rutgers.edu 13910239Sbinhpham@cs.rutgers.edu iewDispSquashedInsts 1401062SN/A .name(name() + ".iewDispSquashedInsts") 1418240Snate@binkert.org .desc("Number of squashed instructions skipped by dispatch"); 1421062SN/A 1431062SN/A iewDispLoadInsts 1441062SN/A .name(name() + ".iewDispLoadInsts") 1458240Snate@binkert.org .desc("Number of dispatched load instructions"); 1461062SN/A 1471062SN/A iewDispStoreInsts 1481062SN/A .name(name() + ".iewDispStoreInsts") 1498240Snate@binkert.org .desc("Number of dispatched store instructions"); 1501062SN/A 1511062SN/A iewDispNonSpecInsts 1521062SN/A .name(name() + ".iewDispNonSpecInsts") 1538240Snate@binkert.org .desc("Number of dispatched non-speculative instructions"); 1541062SN/A 1551062SN/A iewIQFullEvents 1561062SN/A .name(name() + ".iewIQFullEvents") 1578240Snate@binkert.org .desc("Number of times the IQ has become full, causing a stall"); 1581062SN/A 1591062SN/A iewLSQFullEvents 1602301SN/A .name(name() + ".iewLSQFullEvents") 1618240Snate@binkert.org .desc("Number of times the LSQ has become full, causing a stall"); 1622301SN/A 1632301SN/A memOrderViolationEvents 1642301SN/A .name(name() + ".memOrderViolationEvents") 1652301SN/A .desc("Number of memory order violations"); 1668240Snate@binkert.org 1672301SN/A predictedTakenIncorrect 1682301SN/A .name(name() + ".predictedTakenIncorrect") 1692301SN/A .desc("Number of branches that were predicted taken incorrectly"); 1702307SN/A 1718240Snate@binkert.org predictedNotTakenIncorrect 1722307SN/A .name(name() + ".predictedNotTakenIncorrect") 1732307SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1742307SN/A 1757897Shestness@cs.utexas.edu branchMispredicts 1768240Snate@binkert.org .name(name() + ".branchMispredicts") 1777897Shestness@cs.utexas.edu .desc("Number of branch mispredicts detected at execute"); 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1808240Snate@binkert.org 1817897Shestness@cs.utexas.edu iewExecutedInsts 1827897Shestness@cs.utexas.edu .name(name() + ".iewExecutedInsts") 18312109SRekai.GonzalezAlberquilla@arm.com .desc("Number of executed instructions"); 18412109SRekai.GonzalezAlberquilla@arm.com 18512109SRekai.GonzalezAlberquilla@arm.com iewExecLoadInsts 18612109SRekai.GonzalezAlberquilla@arm.com .init(cpu->numThreads) 1871062SN/A .name(name() + ".iewExecLoadInsts") 1881062SN/A .desc("Number of load instructions executed") 1891062SN/A .flags(total); 1901062SN/A 19111246Sradhika.jagtap@ARM.com iewExecSquashedInsts 19211246Sradhika.jagtap@ARM.com .name(name() + ".iewExecSquashedInsts") 19311246Sradhika.jagtap@ARM.com .desc("Number of squashed instructions skipped in execute"); 19411246Sradhika.jagtap@ARM.com 19511246Sradhika.jagtap@ARM.com iewExecutedSwp 19611246Sradhika.jagtap@ARM.com .init(cpu->numThreads) 19711246Sradhika.jagtap@ARM.com .name(name() + ".EXEC:swp") 19811246Sradhika.jagtap@ARM.com .desc("number of swp insts executed") 19911246Sradhika.jagtap@ARM.com .flags(total); 2002292SN/A 2011060SN/A iewExecutedNop 2021060SN/A .init(cpu->numThreads) 2031060SN/A .name(name() + ".EXEC:nop") 2041060SN/A .desc("number of nop insts executed") 2051060SN/A .flags(total); 2061060SN/A 2071060SN/A iewExecutedRefs 2081060SN/A .init(cpu->numThreads) 2091060SN/A .name(name() + ".EXEC:refs") 2101060SN/A .desc("number of memory reference insts executed") 2111060SN/A .flags(total); 2121060SN/A 2131060SN/A iewExecutedBranches 2141061SN/A .init(cpu->numThreads) 2151060SN/A .name(name() + ".EXEC:branches") 2162292SN/A .desc("Number of branches executed") 2171060SN/A .flags(total); 2181060SN/A 2191060SN/A iewExecStoreInsts 2201060SN/A .name(name() + ".EXEC:stores") 2211060SN/A .desc("Number of stores executed") 2221060SN/A .flags(total); 2231060SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2241061SN/A 2251060SN/A iewExecRate 2262292SN/A .name(name() + ".EXEC:rate") 2271060SN/A .desc("Inst execution rate") 2281060SN/A .flags(total); 2291060SN/A 2301060SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2311060SN/A 2321060SN/A iewInstsToCommit 2331060SN/A .init(cpu->numThreads) 2341061SN/A .name(name() + ".WB:sent") 2351060SN/A .desc("cumulative count of insts sent to commit") 2369427SAndreas.Sandberg@ARM.com .flags(total); 2371060SN/A 2389444SAndreas.Sandberg@ARM.com writebackCount 2399444SAndreas.Sandberg@ARM.com .init(cpu->numThreads) 2409444SAndreas.Sandberg@ARM.com .name(name() + ".WB:count") 2419444SAndreas.Sandberg@ARM.com .desc("cumulative count of insts written-back") 2429444SAndreas.Sandberg@ARM.com .flags(total); 2439444SAndreas.Sandberg@ARM.com 2449444SAndreas.Sandberg@ARM.com producerInst 2459444SAndreas.Sandberg@ARM.com .init(cpu->numThreads) 2469444SAndreas.Sandberg@ARM.com .name(name() + ".WB:producers") 2479444SAndreas.Sandberg@ARM.com .desc("num instructions producing a value") 2489444SAndreas.Sandberg@ARM.com .flags(total); 2499444SAndreas.Sandberg@ARM.com 2502329SN/A consumerInst 2516221Snate@binkert.org .init(cpu->numThreads) 2529444SAndreas.Sandberg@ARM.com .name(name() + ".WB:consumers") 2539444SAndreas.Sandberg@ARM.com .desc("num instructions consuming a value") 2542292SN/A .flags(total); 25510239Sbinhpham@cs.rutgers.edu 25610239Sbinhpham@cs.rutgers.edu wbPenalized 2572292SN/A .init(cpu->numThreads) 2582292SN/A .name(name() + ".WB:penalized") 2599444SAndreas.Sandberg@ARM.com .desc("number of instrctions required to write to 'other' IQ") 2609444SAndreas.Sandberg@ARM.com .flags(total); 2619444SAndreas.Sandberg@ARM.com 2629444SAndreas.Sandberg@ARM.com wbPenalizedRate 2639444SAndreas.Sandberg@ARM.com .name(name() + ".WB:penalized_rate") 26410239Sbinhpham@cs.rutgers.edu .desc ("fraction of instructions written-back that wrote to 'other' IQ") 26510239Sbinhpham@cs.rutgers.edu .flags(total); 2669444SAndreas.Sandberg@ARM.com 2679444SAndreas.Sandberg@ARM.com wbPenalizedRate = wbPenalized / writebackCount; 2682292SN/A 2691060SN/A wbFanout 2701060SN/A .name(name() + ".WB:fanout") 2712292SN/A .desc("average fanout of values written-back") 2722292SN/A .flags(total); 2736221Snate@binkert.org 2742292SN/A wbFanout = producerInst / consumerInst; 2752292SN/A 2762292SN/A wbRate 2772292SN/A .name(name() + ".WB:rate") 2782292SN/A .desc("insts written-back per cycle") 2791061SN/A .flags(total); 2801060SN/A wbRate = writebackCount / cpu->numCycles; 2812292SN/A} 2821060SN/A 2836221Snate@binkert.orgtemplate<class Impl> 2846221Snate@binkert.orgvoid 2851060SN/ADefaultIEW<Impl>::initStage() 2861060SN/A{ 2871061SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2881060SN/A toRename->iewInfo[tid].usedIQ = true; 2892292SN/A toRename->iewInfo[tid].freeIQEntries = 2901060SN/A instQueue.numFreeEntries(tid); 2912292SN/A 2922292SN/A toRename->iewInfo[tid].usedLSQ = true; 2931060SN/A toRename->iewInfo[tid].freeLSQEntries = 2942292SN/A ldstQueue.numFreeEntries(tid); 2952292SN/A } 2962292SN/A 2972292SN/A cpu->activateStage(O3CPU::IEWIdx); 2982292SN/A} 2991060SN/A 3001060SN/Atemplate<class Impl> 3011061SN/Avoid 3022863Sktlim@umich.eduDefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3039444SAndreas.Sandberg@ARM.com{ 3041060SN/A timeBuffer = tb_ptr; 3059444SAndreas.Sandberg@ARM.com 3069444SAndreas.Sandberg@ARM.com // Setup wire to read information from time buffer, from commit. 3079444SAndreas.Sandberg@ARM.com fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3089444SAndreas.Sandberg@ARM.com 30911650Srekai.gonzalezalberquilla@arm.com // Setup wire to write information back to previous stages. 31011650Srekai.gonzalezalberquilla@arm.com toRename = timeBuffer->getWire(0); 3119444SAndreas.Sandberg@ARM.com 3129444SAndreas.Sandberg@ARM.com toFetch = timeBuffer->getWire(0); 3132863Sktlim@umich.edu 3142316SN/A // Instruction queue also needs main time buffer. 3151060SN/A instQueue.setTimeBuffer(tb_ptr); 3162316SN/A} 3172316SN/A 3182307SN/Atemplate<class Impl> 3191060SN/Avoid 3209444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3219444SAndreas.Sandberg@ARM.com{ 3221060SN/A renameQueue = rq_ptr; 3239444SAndreas.Sandberg@ARM.com 3249444SAndreas.Sandberg@ARM.com // Setup wire to read information from rename queue. 3259444SAndreas.Sandberg@ARM.com fromRename = renameQueue->getWire(-renameToIEWDelay); 3269444SAndreas.Sandberg@ARM.com} 3276221Snate@binkert.org 3289444SAndreas.Sandberg@ARM.comtemplate<class Impl> 3299444SAndreas.Sandberg@ARM.comvoid 3309444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3319444SAndreas.Sandberg@ARM.com{ 3322307SN/A iewQueue = iq_ptr; 3332307SN/A 3342307SN/A // Setup wire to write instructions to commit. 3352307SN/A toCommit = iewQueue->getWire(0); 3362307SN/A} 3376221Snate@binkert.org 3381858SN/Atemplate<class Impl> 3392292SN/Avoid 3401858SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3412292SN/A{ 3422292SN/A activeThreads = at_ptr; 3432292SN/A 3442292SN/A ldstQueue.setActiveThreads(at_ptr); 3453788Sgblack@eecs.umich.edu instQueue.setActiveThreads(at_ptr); 3462292SN/A} 3472698Sktlim@umich.edu 3483788Sgblack@eecs.umich.edutemplate<class Impl> 3492301SN/Avoid 3503788Sgblack@eecs.umich.eduDefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3513788Sgblack@eecs.umich.edu{ 3523788Sgblack@eecs.umich.edu scoreboard = sb_ptr; 3533788Sgblack@eecs.umich.edu} 3543788Sgblack@eecs.umich.edu 3553788Sgblack@eecs.umich.edutemplate <class Impl> 3563788Sgblack@eecs.umich.edubool 3573788Sgblack@eecs.umich.eduDefaultIEW<Impl>::drain() 3583788Sgblack@eecs.umich.edu{ 3593788Sgblack@eecs.umich.edu // IEW is ready to drain at any time. 3603788Sgblack@eecs.umich.edu cpu->signalDrained(); 3612292SN/A return true; 3622292SN/A} 3632292SN/A 3642292SN/Atemplate <class Impl> 3652292SN/Avoid 3662329SN/ADefaultIEW<Impl>::resume() 3672292SN/A{ 3682935Sksewell@umich.edu} 3692935Sksewell@umich.edu 3702731Sktlim@umich.edutemplate <class Impl> 3712292SN/Avoid 3722292SN/ADefaultIEW<Impl>::switchOut() 3732935Sksewell@umich.edu{ 3742292SN/A // Clear any state. 3752292SN/A switchedOut = true; 3762935Sksewell@umich.edu assert(insts[0].empty()); 3774632Sgblack@eecs.umich.edu assert(skidBuffer[0].empty()); 3783093Sksewell@umich.edu 3792292SN/A instQueue.switchOut(); 3802292SN/A ldstQueue.switchOut(); 3813093Sksewell@umich.edu fuPool->switchOut(); 3824632Sgblack@eecs.umich.edu 3832935Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3842292SN/A while (!insts[tid].empty()) 3852292SN/A insts[tid].pop(); 3862292SN/A while (!skidBuffer[tid].empty()) 3872292SN/A skidBuffer[tid].pop(); 3882292SN/A } 3892292SN/A} 3902292SN/A 3912292SN/Atemplate <class Impl> 3922292SN/Avoid 3932292SN/ADefaultIEW<Impl>::takeOverFrom() 3942292SN/A{ 3952292SN/A // Reset all state. 3962292SN/A _status = Active; 3972292SN/A exeStatus = Running; 3982292SN/A wbStatus = Idle; 3992292SN/A switchedOut = false; 4006221Snate@binkert.org 4016221Snate@binkert.org instQueue.takeOverFrom(); 4022292SN/A ldstQueue.takeOverFrom(); 4032292SN/A fuPool->takeOverFrom(); 4043867Sbinkertn@umich.edu 4056221Snate@binkert.org initStage(); 4062292SN/A cpu->activityThisCycle(); 4072292SN/A 4082292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4092292SN/A dispatchStatus[tid] = Running; 4102292SN/A stalls[tid].commit = false; 4112292SN/A fetchRedirect[tid] = false; 4122292SN/A } 4132292SN/A 4142292SN/A updateLSQNextCycle = false; 4152292SN/A 4162292SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4172292SN/A issueToExecQueue.advance(); 4182292SN/A } 4192292SN/A} 4202292SN/A 4212292SN/Atemplate<class Impl> 4222292SN/Avoid 4233867Sbinkertn@umich.eduDefaultIEW<Impl>::squash(ThreadID tid) 4242292SN/A{ 4253867Sbinkertn@umich.edu DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4266221Snate@binkert.org 4272292SN/A // Tell the IQ to start squashing. 4282292SN/A instQueue.squash(tid); 4292292SN/A 4302292SN/A // Tell the LDSTQ to start squashing. 4312292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4322292SN/A updatedQueues = true; 4332292SN/A 4342292SN/A // Clear the skid buffer in case it has any data in it. 4352292SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4362292SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4372292SN/A 4382292SN/A while (!skidBuffer[tid].empty()) { 4396221Snate@binkert.org if (skidBuffer[tid].front()->isLoad() || 4402292SN/A skidBuffer[tid].front()->isStore() ) { 44110239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLSQ++; 44210239Sbinhpham@cs.rutgers.edu } 44310239Sbinhpham@cs.rutgers.edu 44410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatched++; 4452292SN/A 4462292SN/A skidBuffer[tid].pop(); 4472292SN/A } 4482292SN/A 4492292SN/A emptyRenameInsts(tid); 4502292SN/A} 4512292SN/A 4526221Snate@binkert.orgtemplate<class Impl> 4532292SN/Avoid 4542292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4552292SN/A{ 4562292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4572292SN/A "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4582292SN/A 4592292SN/A if (toCommit->squash[tid] == false || 4602292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4612292SN/A toCommit->squash[tid] = true; 4622292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4632292SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 4642292SN/A 4652301SN/A TheISA::PCState pc = inst->pcState(); 4662301SN/A TheISA::advancePC(pc, inst->staticInst); 4673788Sgblack@eecs.umich.edu 4683788Sgblack@eecs.umich.edu toCommit->pc[tid] = pc; 4693788Sgblack@eecs.umich.edu toCommit->mispredictInst[tid] = inst; 4703788Sgblack@eecs.umich.edu toCommit->includeSquashInst[tid] = false; 4713788Sgblack@eecs.umich.edu 4723788Sgblack@eecs.umich.edu wroteToTimeBuffer = true; 4733788Sgblack@eecs.umich.edu } 4743788Sgblack@eecs.umich.edu 4753798Sgblack@eecs.umich.edu} 4763798Sgblack@eecs.umich.edu 4773798Sgblack@eecs.umich.edutemplate<class Impl> 4783798Sgblack@eecs.umich.eduvoid 4793798Sgblack@eecs.umich.eduDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4803798Sgblack@eecs.umich.edu{ 4812292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4822292SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4832292SN/A 4842292SN/A if (toCommit->squash[tid] == false || 4852292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4862292SN/A toCommit->squash[tid] = true; 4872292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4882292SN/A TheISA::PCState pc = inst->pcState(); 4892292SN/A TheISA::advancePC(pc, inst->staticInst); 4902292SN/A toCommit->pc[tid] = pc; 4912292SN/A toCommit->mispredictInst[tid] = NULL; 4922292SN/A 4932292SN/A toCommit->includeSquashInst[tid] = false; 4942292SN/A 4952292SN/A wroteToTimeBuffer = true; 4962292SN/A } 4972292SN/A} 4982292SN/A 4992292SN/Atemplate<class Impl> 5002292SN/Avoid 5011858SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5021858SN/A{ 5031858SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5041858SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5051858SN/A if (toCommit->squash[tid] == false || 5066221Snate@binkert.org inst->seqNum < toCommit->squashedSeqNum[tid]) { 5071858SN/A toCommit->squash[tid] = true; 5082292SN/A 5092292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5102292SN/A toCommit->pc[tid] = inst->pcState(); 5112292SN/A toCommit->mispredictInst[tid] = NULL; 5121858SN/A 5132292SN/A // Must include the broadcasted SN in the squash. 5142292SN/A toCommit->includeSquashInst[tid] = true; 5152292SN/A 5162292SN/A ldstQueue.setLoadBlockedHandled(tid); 5172292SN/A 5182292SN/A wroteToTimeBuffer = true; 5192292SN/A } 5202292SN/A} 5212292SN/A 5222292SN/Atemplate<class Impl> 5232292SN/Avoid 5242292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5252292SN/A{ 5261858SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5272292SN/A 5282292SN/A if (dispatchStatus[tid] != Blocked && 5292292SN/A dispatchStatus[tid] != Unblocking) { 5302292SN/A toRename->iewBlock[tid] = true; 5312292SN/A wroteToTimeBuffer = true; 5322292SN/A } 5332292SN/A 5342292SN/A // Add the current inputs to the skid buffer so they can be 5352292SN/A // reprocessed when this stage unblocks. 5362292SN/A skidInsert(tid); 5372292SN/A 5382292SN/A dispatchStatus[tid] = Blocked; 5392292SN/A} 5402292SN/A 5412292SN/Atemplate<class Impl> 5422292SN/Avoid 5432292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 54410239Sbinhpham@cs.rutgers.edu{ 5452292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5462292SN/A "buffer %u.\n",tid, tid); 54710239Sbinhpham@cs.rutgers.edu 5482292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5492292SN/A // Also switch status to running. 55010239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].empty()) { 5512292SN/A toRename->iewUnblock[tid] = true; 5522292SN/A wroteToTimeBuffer = true; 5532292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5542292SN/A dispatchStatus[tid] = Running; 5552292SN/A } 5562292SN/A} 5572292SN/A 5582292SN/Atemplate<class Impl> 5592292SN/Avoid 5602292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5612292SN/A{ 5622292SN/A instQueue.wakeDependents(inst); 5632292SN/A} 5642292SN/A 5652292SN/Atemplate<class Impl> 5662292SN/Avoid 5672292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5682292SN/A{ 5692292SN/A instQueue.rescheduleMemInst(inst); 5702292SN/A} 5712292SN/A 5722292SN/Atemplate<class Impl> 5732292SN/Avoid 5742292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5752292SN/A{ 5762292SN/A instQueue.replayMemInst(inst); 5772292SN/A} 5782292SN/A 5792292SN/Atemplate<class Impl> 5802292SN/Avoid 5812292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5822292SN/A{ 5832292SN/A // This function should not be called after writebackInsts in a 5842292SN/A // single cycle. That will cause problems with an instruction 5852292SN/A // being added to the queue to commit without being processed by 5862292SN/A // writebackInsts prior to being sent to commit. 5872292SN/A 5882292SN/A // First check the time slot that this instruction will write 5892292SN/A // to. If there are free write ports at the time, then go ahead 5902292SN/A // and write the instruction to that time. If there are not, 5912292SN/A // keep looking back to see where's the first time there's a 5922292SN/A // free slot. 5932292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5942292SN/A ++wbNumInst; 5952292SN/A if (wbNumInst == wbWidth) { 5962292SN/A ++wbCycle; 5972292SN/A wbNumInst = 0; 5982292SN/A } 5992292SN/A 6002292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 60110239Sbinhpham@cs.rutgers.edu } 60210239Sbinhpham@cs.rutgers.edu 60310239Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 60410239Sbinhpham@cs.rutgers.edu wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 60510239Sbinhpham@cs.rutgers.edu // Add finished instruction to queue to commit. 60610933Snilay@cs.wisc.edu (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 60710933Snilay@cs.wisc.edu (*iewQueue)[wbCycle].size++; 60810933Snilay@cs.wisc.edu} 60910933Snilay@cs.wisc.edu 61010933Snilay@cs.wisc.edutemplate <class Impl> 61110933Snilay@cs.wisc.eduunsigned 61210239Sbinhpham@cs.rutgers.eduDefaultIEW<Impl>::validInstsFromRename() 61310239Sbinhpham@cs.rutgers.edu{ 61410239Sbinhpham@cs.rutgers.edu unsigned inst_count = 0; 61510933Snilay@cs.wisc.edu 61610933Snilay@cs.wisc.edu for (int i=0; i<fromRename->size; i++) { 61710933Snilay@cs.wisc.edu if (!fromRename->insts[i]->isSquashed()) 61810933Snilay@cs.wisc.edu inst_count++; 61910933Snilay@cs.wisc.edu } 62010933Snilay@cs.wisc.edu 62110239Sbinhpham@cs.rutgers.edu return inst_count; 62210239Sbinhpham@cs.rutgers.edu} 6232292SN/A 6242292SN/Atemplate<class Impl> 6252292SN/Avoid 6267720Sgblack@eecs.umich.eduDefaultIEW<Impl>::skidInsert(ThreadID tid) 6277720Sgblack@eecs.umich.edu{ 6282292SN/A DynInstPtr inst = NULL; 6292292SN/A 6302292SN/A while (!insts[tid].empty()) { 6317720Sgblack@eecs.umich.edu inst = insts[tid].front(); 6327720Sgblack@eecs.umich.edu 6337720Sgblack@eecs.umich.edu insts[tid].pop(); 6342292SN/A 6352292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6362292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6372292SN/A inst->pcState(),tid); 6382292SN/A 6392292SN/A skidBuffer[tid].push(inst); 6402292SN/A } 6412292SN/A 6422292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6432292SN/A "Skidbuffer Exceeded Max Size"); 6447720Sgblack@eecs.umich.edu} 6452292SN/A 6469531Sgeoffrey.blake@arm.comtemplate<class Impl> 6479531Sgeoffrey.blake@arm.comint 64810715SRekai.GonzalezAlberquilla@arm.comDefaultIEW<Impl>::skidCount() 64910715SRekai.GonzalezAlberquilla@arm.com{ 65012109SRekai.GonzalezAlberquilla@arm.com int max=0; 65112109SRekai.GonzalezAlberquilla@arm.com 65210935Snilay@cs.wisc.edu list<ThreadID>::iterator threads = activeThreads->begin(); 6539531Sgeoffrey.blake@arm.com list<ThreadID>::iterator end = activeThreads->end(); 6549531Sgeoffrey.blake@arm.com 6559531Sgeoffrey.blake@arm.com while (threads != end) { 6569531Sgeoffrey.blake@arm.com ThreadID tid = *threads++; 6579531Sgeoffrey.blake@arm.com unsigned thread_count = skidBuffer[tid].size(); 6589531Sgeoffrey.blake@arm.com if (max < thread_count) 6599531Sgeoffrey.blake@arm.com max = thread_count; 6609531Sgeoffrey.blake@arm.com } 6619531Sgeoffrey.blake@arm.com 6622292SN/A return max; 6632292SN/A} 6642292SN/A 6652292SN/Atemplate<class Impl> 6662336SN/Abool 6672336SN/ADefaultIEW<Impl>::skidsEmpty() 6682336SN/A{ 6692336SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6702336SN/A list<ThreadID>::iterator end = activeThreads->end(); 6712336SN/A 6722336SN/A while (threads != end) { 6732336SN/A ThreadID tid = *threads++; 6742292SN/A 6752292SN/A if (!skidBuffer[tid].empty()) 6762301SN/A return false; 6772301SN/A } 6782292SN/A 6792301SN/A return true; 6802301SN/A} 6812301SN/A 6822292SN/Atemplate <class Impl> 6832301SN/Avoid 6842292SN/ADefaultIEW<Impl>::updateStatus() 6852301SN/A{ 6862292SN/A bool any_unblocking = false; 6872301SN/A 6882292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6892292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6902292SN/A 6912292SN/A while (threads != end) { 6922336SN/A ThreadID tid = *threads++; 6932336SN/A 6942292SN/A if (dispatchStatus[tid] == Unblocking) { 6952292SN/A any_unblocking = true; 6962307SN/A break; 6972307SN/A } 6982292SN/A } 6992292SN/A 7002292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7012292SN/A // and there's no stores waiting to write back, and dispatch is not 7022292SN/A // unblocking, then there is no internal activity for the IEW stage. 7032292SN/A instQueue.intInstQueueReads++; 7042292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7052292SN/A !ldstQueue.willWB() && !any_unblocking) { 7062292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 70710239Sbinhpham@cs.rutgers.edu 70810239Sbinhpham@cs.rutgers.edu deactivateStage(); 70910239Sbinhpham@cs.rutgers.edu 71010239Sbinhpham@cs.rutgers.edu _status = Inactive; 71110239Sbinhpham@cs.rutgers.edu } else if (_status == Inactive && (instQueue.hasReadyInsts() || 71210239Sbinhpham@cs.rutgers.edu ldstQueue.willWB() || 7132292SN/A any_unblocking)) { 71411246Sradhika.jagtap@ARM.com // Otherwise there is internal activity. Set to active. 71511246Sradhika.jagtap@ARM.com DPRINTF(IEW, "IEW switching to active\n"); 71611246Sradhika.jagtap@ARM.com 7178471SGiacomo.Gabrielli@arm.com activateStage(); 7182292SN/A 7192292SN/A _status = Active; 7202292SN/A } 7212292SN/A} 7222292SN/A 7232292SN/Atemplate <class Impl> 7242292SN/Avoid 7252292SN/ADefaultIEW<Impl>::resetEntries() 7262292SN/A{ 7272292SN/A instQueue.resetEntries(); 7282292SN/A ldstQueue.resetEntries(); 7292292SN/A} 7302307SN/A 7312292SN/Atemplate <class Impl> 7322292SN/Avoid 7332292SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7342292SN/A{ 7352292SN/A if (fromCommit->commitBlock[tid]) { 7362292SN/A stalls[tid].commit = true; 7372292SN/A } 7382292SN/A 7392292SN/A if (fromCommit->commitUnblock[tid]) { 7402292SN/A assert(stalls[tid].commit); 7412292SN/A stalls[tid].commit = false; 7422292SN/A } 7432292SN/A} 7442292SN/A 7452292SN/Atemplate <class Impl> 7462292SN/Abool 7472292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7482292SN/A{ 7492292SN/A bool ret_val(false); 7502292SN/A 7516221Snate@binkert.org if (stalls[tid].commit) { 7522292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7532292SN/A ret_val = true; 7542292SN/A } else if (instQueue.isFull(tid)) { 7552292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7562292SN/A ret_val = true; 7572292SN/A } else if (ldstQueue.isFull(tid)) { 7582292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7592292SN/A 7602292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7612292SN/A 7627720Sgblack@eecs.umich.edu DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7637720Sgblack@eecs.umich.edu tid,ldstQueue.getLoadHeadSeqNum(tid)); 7642292SN/A } 7652307SN/A 7662307SN/A if (ldstQueue.numStores(tid) > 0) { 7672292SN/A 7682292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7692292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7702292SN/A } 7713798Sgblack@eecs.umich.edu 7723798Sgblack@eecs.umich.edu ret_val = true; 7733798Sgblack@eecs.umich.edu } else if (ldstQueue.isStalled(tid)) { 77411321Ssteve.reinhardt@amd.com DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7753798Sgblack@eecs.umich.edu ret_val = true; 7763798Sgblack@eecs.umich.edu } 7777720Sgblack@eecs.umich.edu 7783798Sgblack@eecs.umich.edu return ret_val; 7793798Sgblack@eecs.umich.edu} 7802292SN/A 7813798Sgblack@eecs.umich.edutemplate <class Impl> 7822292SN/Avoid 7832292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7842292SN/A{ 7852292SN/A // Check if there's a squash signal, squash if there is 7862292SN/A // Check stall signals, block if there is. 7872292SN/A // If status was Blocked 7882292SN/A // if so then go to unblocking 7892292SN/A // If status was Squashing 7902292SN/A // check if squashing is not high. Switch to running this cycle. 7912292SN/A 7929527SMatt.Horsnell@arm.com readStallSignals(tid); 7939527SMatt.Horsnell@arm.com 7949527SMatt.Horsnell@arm.com if (fromCommit->commitInfo[tid].squash) { 7959527SMatt.Horsnell@arm.com squash(tid); 7969527SMatt.Horsnell@arm.com 7972292SN/A if (dispatchStatus[tid] == Blocked || 7982292SN/A dispatchStatus[tid] == Unblocking) { 7992292SN/A toRename->iewUnblock[tid] = true; 8002292SN/A wroteToTimeBuffer = true; 8012292SN/A } 8022292SN/A 8032292SN/A dispatchStatus[tid] = Squashing; 8046221Snate@binkert.org fetchRedirect[tid] = false; 8056221Snate@binkert.org return; 8062292SN/A } 8073867Sbinkertn@umich.edu 8086221Snate@binkert.org if (fromCommit->commitInfo[tid].robSquashing) { 8093867Sbinkertn@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8103867Sbinkertn@umich.edu 8112292SN/A dispatchStatus[tid] = Squashing; 8122292SN/A emptyRenameInsts(tid); 8132292SN/A wroteToTimeBuffer = true; 8142292SN/A return; 8152292SN/A } 8162292SN/A 8172292SN/A if (checkStall(tid)) { 8182292SN/A block(tid); 8192292SN/A dispatchStatus[tid] = Blocked; 8202292SN/A return; 8212292SN/A } 8222292SN/A 8236221Snate@binkert.org if (dispatchStatus[tid] == Blocked) { 8246221Snate@binkert.org // Status from previous cycle was blocked, but there are no more stall 8252292SN/A // conditions. Switch over to unblocking. 8263867Sbinkertn@umich.edu DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8276221Snate@binkert.org tid); 8282292SN/A 8292292SN/A dispatchStatus[tid] = Unblocking; 8302292SN/A 8312292SN/A unblock(tid); 8322292SN/A 8332292SN/A return; 8342292SN/A } 8352292SN/A 8362292SN/A if (dispatchStatus[tid] == Squashing) { 8372292SN/A // Switch status to running if rename isn't being told to block or 8382292SN/A // squash this cycle. 8392292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8402292SN/A tid); 8412292SN/A 8422733Sktlim@umich.edu dispatchStatus[tid] = Running; 8432292SN/A 8442292SN/A return; 8452292SN/A } 8462292SN/A} 8472292SN/A 8482292SN/Atemplate <class Impl> 8492292SN/Avoid 8502292SN/ADefaultIEW<Impl>::sortInsts() 8512733Sktlim@umich.edu{ 8522292SN/A int insts_from_rename = fromRename->size; 8532292SN/A#ifdef DEBUG 8542292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8552292SN/A assert(insts[tid].empty()); 8562292SN/A#endif 8572292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8586221Snate@binkert.org insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8592292SN/A } 8602292SN/A} 8612292SN/A 8622292SN/Atemplate <class Impl> 8632292SN/Avoid 8642292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8652292SN/A{ 8662292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8672292SN/A 8682292SN/A while (!insts[tid].empty()) { 8693798Sgblack@eecs.umich.edu 8703798Sgblack@eecs.umich.edu if (insts[tid].front()->isLoad() || 8713798Sgblack@eecs.umich.edu insts[tid].front()->isStore() ) { 8723798Sgblack@eecs.umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8732292SN/A } 8742292SN/A 8752292SN/A toRename->iewInfo[tid].dispatched++; 8762292SN/A 8772292SN/A insts[tid].pop(); 8782329SN/A } 8792329SN/A} 8802301SN/A 8812292SN/Atemplate <class Impl> 8822292SN/Avoid 8832292SN/ADefaultIEW<Impl>::wakeCPU() 8842292SN/A{ 8852292SN/A cpu->wakeCPU(); 8862292SN/A} 8872292SN/A 8882292SN/Atemplate <class Impl> 8892292SN/Avoid 8902292SN/ADefaultIEW<Impl>::activityThisCycle() 8912292SN/A{ 8926221Snate@binkert.org DPRINTF(Activity, "Activity this cycle.\n"); 8932292SN/A cpu->activityThisCycle(); 8942292SN/A} 8952292SN/A 8962292SN/Atemplate <class Impl> 8972301SN/Ainline void 8982292SN/ADefaultIEW<Impl>::activateStage() 8992292SN/A{ 9002292SN/A DPRINTF(Activity, "Activating stage.\n"); 9012292SN/A cpu->activateStage(O3CPU::IEWIdx); 9022292SN/A} 9032292SN/A 9042292SN/Atemplate <class Impl> 9052292SN/Ainline void 9062292SN/ADefaultIEW<Impl>::deactivateStage() 9072292SN/A{ 9082292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9092292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9102292SN/A} 9112292SN/A 9122292SN/Atemplate<class Impl> 9136221Snate@binkert.orgvoid 9142292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9152980Sgblack@eecs.umich.edu{ 9162980Sgblack@eecs.umich.edu // If status is Running or idle, 9172292SN/A // call dispatchInsts() 9181060SN/A // If status is Unblocking, 9191060SN/A // buffer any instructions coming from rename 9202292SN/A // continue trying to empty skid buffer 9211060SN/A // check if stall conditions have passed 9221060SN/A 9231060SN/A if (dispatchStatus[tid] == Blocked) { 9241060SN/A ++iewBlockCycles; 9251060SN/A 9262292SN/A } else if (dispatchStatus[tid] == Squashing) { 9279919Ssteve.reinhardt@amd.com ++iewSquashCycles; 9282292SN/A } 9291062SN/A 9302292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9319919Ssteve.reinhardt@amd.com // will allow, as long as it is not currently blocked. 9321060SN/A if (dispatchStatus[tid] == Running || 9339919Ssteve.reinhardt@amd.com dispatchStatus[tid] == Idle) { 9349919Ssteve.reinhardt@amd.com DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9359919Ssteve.reinhardt@amd.com "dispatch.\n", tid); 9369919Ssteve.reinhardt@amd.com 9379919Ssteve.reinhardt@amd.com dispatchInsts(tid); 9389919Ssteve.reinhardt@amd.com } else if (dispatchStatus[tid] == Unblocking) { 9399919Ssteve.reinhardt@amd.com // Make sure that the skid buffer has something in it if the 9409919Ssteve.reinhardt@amd.com // status is unblocking. 9419919Ssteve.reinhardt@amd.com assert(!skidsEmpty()); 9429919Ssteve.reinhardt@amd.com 9431060SN/A // If the status was unblocking, then instructions from the skid 9449919Ssteve.reinhardt@amd.com // buffer were used. Remove those instructions and handle 9459919Ssteve.reinhardt@amd.com // the rest of unblocking. 9469919Ssteve.reinhardt@amd.com dispatchInsts(tid); 9471062SN/A 94811246Sradhika.jagtap@ARM.com ++iewUnblockCycles; 94911246Sradhika.jagtap@ARM.com 95011246Sradhika.jagtap@ARM.com if (validInstsFromRename()) { 95111246Sradhika.jagtap@ARM.com // Add the current inputs to the skid buffer so they can be 95211246Sradhika.jagtap@ARM.com // reprocessed when this stage unblocks. 95311246Sradhika.jagtap@ARM.com skidInsert(tid); 9542292SN/A } 9551061SN/A 9561062SN/A unblock(tid); 9571060SN/A } 9581060SN/A} 9591060SN/A 9601060SN/Atemplate <class Impl> 9611060SN/Avoid 9626221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9631060SN/A{ 9642292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9652292SN/A // otherwise. 9662292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9672292SN/A dispatchStatus[tid] == Unblocking ? 9682980Sgblack@eecs.umich.edu skidBuffer[tid] : insts[tid]; 9692980Sgblack@eecs.umich.edu 9701060SN/A int insts_to_add = insts_to_dispatch.size(); 9711061SN/A 9721060SN/A DynInstPtr inst; 9732292SN/A bool add_to_iq = false; 9742292SN/A int dis_num_inst = 0; 9752292SN/A 9762292SN/A // Loop through the instructions, putting them in the instruction 9772292SN/A // queue. 9782292SN/A for ( ; dis_num_inst < insts_to_add && 9791060SN/A dis_num_inst < dispatchWidth; 9801060SN/A ++dis_num_inst) 9811060SN/A { 9822292SN/A inst = insts_to_dispatch.front(); 9832292SN/A 9842292SN/A if (dispatchStatus[tid] == Unblocking) { 9852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9862292SN/A "buffer\n", tid); 9872292SN/A } 9889919Ssteve.reinhardt@amd.com 9891060SN/A // Make sure there's a valid instruction there. 99012105Snathanael.premillieu@arm.com assert(inst); 9912329SN/A 99212106SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 99312106SRekai.GonzalezAlberquilla@arm.com "IQ.\n", 99412105Snathanael.premillieu@arm.com tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9951061SN/A 9969919Ssteve.reinhardt@amd.com // Be sure to mark these instructions as ready so that the 9979919Ssteve.reinhardt@amd.com // commit stage can go ahead and execute them, and mark 9989919Ssteve.reinhardt@amd.com // them as issued so the IQ doesn't reprocess them. 9999919Ssteve.reinhardt@amd.com 10009919Ssteve.reinhardt@amd.com // Check for squashed instructions. 10019919Ssteve.reinhardt@amd.com if (inst->isSquashed()) { 10029919Ssteve.reinhardt@amd.com DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10032292SN/A "not adding to IQ.\n", tid); 10041061SN/A 10052292SN/A ++iewDispSquashedInsts; 10061060SN/A 10071060SN/A insts_to_dispatch.pop(); 10081060SN/A 10091061SN/A //Tell Rename That An Instruction has been processed 10101061SN/A if (inst->isLoad() || inst->isStore()) { 10116221Snate@binkert.org toRename->iewInfo[tid].dispatchedToLSQ++; 10121061SN/A } 10139919Ssteve.reinhardt@amd.com toRename->iewInfo[tid].dispatched++; 10149919Ssteve.reinhardt@amd.com 10151061SN/A continue; 10161061SN/A } 10171061SN/A 10189919Ssteve.reinhardt@amd.com // Check for full conditions. 10192292SN/A if (instQueue.isFull(tid)) { 102012106SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 102112105Snathanael.premillieu@arm.com 10229919Ssteve.reinhardt@amd.com // Call function to start blocking. 102312106SRekai.GonzalezAlberquilla@arm.com block(tid); 102412106SRekai.GonzalezAlberquilla@arm.com 10259913Ssteve.reinhardt@amd.com // Set unblock to false. Special case where we are using 10269919Ssteve.reinhardt@amd.com // skidbuffer (unblocking) instructions but then we still 10279913Ssteve.reinhardt@amd.com // get full in the IQ. 10289913Ssteve.reinhardt@amd.com toRename->iewUnblock[tid] = false; 10299919Ssteve.reinhardt@amd.com 10309913Ssteve.reinhardt@amd.com ++iewIQFullEvents; 103112144Srekai.gonzalezalberquilla@arm.com break; 103212144Srekai.gonzalezalberquilla@arm.com } else if (ldstQueue.isFull(tid)) { 103312144Srekai.gonzalezalberquilla@arm.com DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10349920Syasuko.eckert@amd.com 10359913Ssteve.reinhardt@amd.com // Call function to start blocking. 10369913Ssteve.reinhardt@amd.com block(tid); 10379913Ssteve.reinhardt@amd.com 10389913Ssteve.reinhardt@amd.com // Set unblock to false. Special case where we are using 103912106SRekai.GonzalezAlberquilla@arm.com // skidbuffer (unblocking) instructions but then we still 10403773Sgblack@eecs.umich.edu // get full in the IQ. 10414352Sgblack@eecs.umich.edu toRename->iewUnblock[tid] = false; 104212105Snathanael.premillieu@arm.com 104312106SRekai.GonzalezAlberquilla@arm.com ++iewLSQFullEvents; 104412106SRekai.GonzalezAlberquilla@arm.com break; 104512106SRekai.GonzalezAlberquilla@arm.com } 104612106SRekai.GonzalezAlberquilla@arm.com 10471061SN/A // Otherwise issue the instruction just fine. 10481061SN/A if (inst->isLoad()) { 10491061SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10502292SN/A "encountered, adding to LSQ.\n", tid); 10519919Ssteve.reinhardt@amd.com 105212105Snathanael.premillieu@arm.com // Reserve a spot in the load store queue for this 105312106SRekai.GonzalezAlberquilla@arm.com // memory access. 105412106SRekai.GonzalezAlberquilla@arm.com ldstQueue.insertLoad(inst); 105512106SRekai.GonzalezAlberquilla@arm.com 10561061SN/A ++iewDispLoadInsts; 10571061SN/A 10584636Sgblack@eecs.umich.edu add_to_iq = true; 105912105Snathanael.premillieu@arm.com 106012106SRekai.GonzalezAlberquilla@arm.com toRename->iewInfo[tid].dispatchedToLSQ++; 106112106SRekai.GonzalezAlberquilla@arm.com } else if (inst->isStore()) { 106212106SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10631061SN/A "encountered, adding to LSQ.\n", tid); 10641062SN/A 10651062SN/A ldstQueue.insertStore(inst); 10661061SN/A 10671061SN/A ++iewDispStoreInsts; 10681061SN/A 10691061SN/A if (inst->isStoreConditional()) { 10701061SN/A // Store conditionals need to be set as "canCommit()" 10716221Snate@binkert.org // so that commit can process them when they reach the 10721061SN/A // head of commit. 10739919Ssteve.reinhardt@amd.com // @todo: This is somewhat specific to Alpha. 10749919Ssteve.reinhardt@amd.com inst->setCanCommit(); 10751061SN/A instQueue.insertNonSpec(inst); 10761061SN/A add_to_iq = false; 10772292SN/A 10782292SN/A ++iewDispNonSpecInsts; 107912106SRekai.GonzalezAlberquilla@arm.com } else { 10809919Ssteve.reinhardt@amd.com add_to_iq = true; 10819919Ssteve.reinhardt@amd.com } 108212106SRekai.GonzalezAlberquilla@arm.com 10839913Ssteve.reinhardt@amd.com toRename->iewInfo[tid].dispatchedToLSQ++; 108412106SRekai.GonzalezAlberquilla@arm.com } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10859913Ssteve.reinhardt@amd.com // Same as non-speculative stores. 108612106SRekai.GonzalezAlberquilla@arm.com inst->setCanCommit(); 10871061SN/A instQueue.insertBarrier(inst); 10889919Ssteve.reinhardt@amd.com add_to_iq = false; 10899916Ssteve.reinhardt@amd.com } else if (inst->isNop()) { 10901062SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 109112105Snathanael.premillieu@arm.com "skipping.\n", tid); 109212106SRekai.GonzalezAlberquilla@arm.com 109312106SRekai.GonzalezAlberquilla@arm.com inst->setIssued(); 109412106SRekai.GonzalezAlberquilla@arm.com inst->setExecuted(); 109512106SRekai.GonzalezAlberquilla@arm.com inst->setCanCommit(); 10961062SN/A 10972292SN/A instQueue.recordProducer(inst); 109812106SRekai.GonzalezAlberquilla@arm.com 10992292SN/A iewExecutedNop[tid]++; 11002292SN/A 11011062SN/A add_to_iq = false; 11022292SN/A } else if (inst->isExecuted()) { 11031062SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11042935Sksewell@umich.edu DPRINTF(IEW, "Issue: Executed branch encountered, " 11052935Sksewell@umich.edu "skipping.\n"); 11062935Sksewell@umich.edu 11072292SN/A inst->setIssued(); 11081062SN/A inst->setCanCommit(); 11092292SN/A 11102292SN/A instQueue.recordProducer(inst); 11112292SN/A 11122292SN/A add_to_iq = false; 11132292SN/A } else { 11142292SN/A add_to_iq = true; 11152292SN/A } 11162292SN/A if (inst->isNonSpeculative()) { 11171062SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11182292SN/A "encountered, skipping.\n", tid); 11191061SN/A 11201061SN/A // Same as non-speculative stores. 11211061SN/A inst->setCanCommit(); 11221061SN/A 11231061SN/A // Specifically insert it as nonspeculative. 11246221Snate@binkert.org instQueue.insertNonSpec(inst); 11251061SN/A 11262292SN/A ++iewDispNonSpecInsts; 11272292SN/A 11282292SN/A add_to_iq = false; 11292292SN/A } 11302292SN/A 11312292SN/A // If the instruction queue is not full, then add the 11321061SN/A // instruction. 11331061SN/A if (add_to_iq) { 11341061SN/A instQueue.insert(inst); 11351061SN/A } 11366221Snate@binkert.org 11371061SN/A insts_to_dispatch.pop(); 11382292SN/A 11392292SN/A toRename->iewInfo[tid].dispatched++; 11402292SN/A 11412292SN/A ++iewDispatchedInsts; 11422292SN/A } 11432292SN/A 11442292SN/A if (!insts_to_dispatch.empty()) { 11452292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11462292SN/A block(tid); 11472292SN/A toRename->iewUnblock[tid] = false; 114810239Sbinhpham@cs.rutgers.edu } 11492292SN/A 115010239Sbinhpham@cs.rutgers.edu if (dispatchStatus[tid] == Idle && dis_num_inst) { 115110935Snilay@cs.wisc.edu dispatchStatus[tid] = Running; 115210239Sbinhpham@cs.rutgers.edu 115310239Sbinhpham@cs.rutgers.edu updatedQueues = true; 115410239Sbinhpham@cs.rutgers.edu } 115510239Sbinhpham@cs.rutgers.edu 115610239Sbinhpham@cs.rutgers.edu dis_num_inst = 0; 11572292SN/A} 115810239Sbinhpham@cs.rutgers.edu 115910239Sbinhpham@cs.rutgers.edutemplate <class Impl> 116010239Sbinhpham@cs.rutgers.eduvoid 116110239Sbinhpham@cs.rutgers.eduDefaultIEW<Impl>::printAvailableInsts() 116210239Sbinhpham@cs.rutgers.edu{ 116310935Snilay@cs.wisc.edu int inst = 0; 116410239Sbinhpham@cs.rutgers.edu 116510239Sbinhpham@cs.rutgers.edu std::cout << "Available Instructions: "; 116610239Sbinhpham@cs.rutgers.edu 116710239Sbinhpham@cs.rutgers.edu while (fromIssue->insts[inst]) { 11682292SN/A 11692292SN/A if (inst%3==0) std::cout << "\n\t"; 11702292SN/A 11712292SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11722292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11732292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11742292SN/A 11752292SN/A inst++; 11762292SN/A 11772731Sktlim@umich.edu } 11782292SN/A 11792292SN/A std::cout << "\n"; 11802292SN/A} 11812292SN/A 11822292SN/Atemplate <class Impl> 11832292SN/Avoid 11842292SN/ADefaultIEW<Impl>::executeInsts() 11852292SN/A{ 11866221Snate@binkert.org wbNumInst = 0; 11872292SN/A wbCycle = 0; 11882292SN/A 11892292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 11902292SN/A list<ThreadID>::iterator end = activeThreads->end(); 11912292SN/A 11922292SN/A while (threads != end) { 11932292SN/A ThreadID tid = *threads++; 11942292SN/A fetchRedirect[tid] = false; 11952292SN/A } 11962292SN/A 11972292SN/A // Uncomment this if you want to see all available instructions. 11982292SN/A // @todo This doesn't actually work anymore, we should fix it. 11992292SN/A// printAvailableInsts(); 12006221Snate@binkert.org 12012292SN/A // Execute/writeback any instructions that are available. 12022292SN/A int insts_to_execute = fromIssue->size; 12032292SN/A int inst_num = 0; 12042292SN/A for (; inst_num < insts_to_execute; 12052292SN/A ++inst_num) { 12062292SN/A 12072292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12082292SN/A 12092292SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12102292SN/A 12112292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12122292SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 121310239Sbinhpham@cs.rutgers.edu 12142292SN/A // Check if the instruction is squashed; if so then skip it 12152292SN/A if (inst->isSquashed()) { 12162292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12172292SN/A 12182292SN/A // Consider this instruction executed so that commit can go 12192301SN/A // ahead and retire the instruction. 12202292SN/A inst->setExecuted(); 12212301SN/A 12222292SN/A // Not sure if I should set this here or just let commit try to 12232292SN/A // commit any squashed instructions. I like the latter a bit more. 12242292SN/A inst->setCanCommit(); 12252292SN/A 12262292SN/A ++iewExecSquashedInsts; 12272292SN/A 12282292SN/A decrWb(inst->seqNum); 12292292SN/A continue; 12302292SN/A } 12312292SN/A 12326221Snate@binkert.org Fault fault = NoFault; 12332292SN/A 12348607Sgblack@eecs.umich.edu // Execute instruction. 12358607Sgblack@eecs.umich.edu // Note that if the instruction faults, it will be handled 12362292SN/A // at the commit stage. 123710239Sbinhpham@cs.rutgers.edu if (inst->isMemRef()) { 123810239Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "Execute: Calculating address for memory " 123910239Sbinhpham@cs.rutgers.edu "reference.\n"); 124010239Sbinhpham@cs.rutgers.edu 12412292SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12422292SN/A if (inst->isLoad()) { 12432292SN/A // Loads will mark themselves as executed, and their writeback 12442292SN/A // event adds the instruction to the queue to commit 12452292SN/A fault = ldstQueue.executeLoad(inst); 12462292SN/A 12472292SN/A if (inst->isTranslationDelayed() && 124810239Sbinhpham@cs.rutgers.edu fault == NoFault) { 124912109SRekai.GonzalezAlberquilla@arm.com // A hw page table walk is currently going on; the 12502292SN/A // instruction must be deferred. 12512292SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12522292SN/A "load.\n"); 125310239Sbinhpham@cs.rutgers.edu instQueue.deferMemInst(inst); 125412109SRekai.GonzalezAlberquilla@arm.com continue; 125512109SRekai.GonzalezAlberquilla@arm.com } 125612109SRekai.GonzalezAlberquilla@arm.com 125712109SRekai.GonzalezAlberquilla@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 125812109SRekai.GonzalezAlberquilla@arm.com inst->fault = NoFault; 125912109SRekai.GonzalezAlberquilla@arm.com } 12602292SN/A } else if (inst->isStore()) { 12612292SN/A fault = ldstQueue.executeStore(inst); 12622292SN/A 12632292SN/A if (inst->isTranslationDelayed() && 12642292SN/A fault == NoFault) { 12652292SN/A // A hw page table walk is currently going on; the 12662292SN/A // instruction must be deferred. 12676221Snate@binkert.org DPRINTF(IEW, "Execute: Delayed translation, deferring " 12682292SN/A "store.\n"); 12692292SN/A instQueue.deferMemInst(inst); 12702292SN/A continue; 12712292SN/A } 12722292SN/A 12732292SN/A // If the store had a fault then it may not have a mem req 12742292SN/A if (fault != NoFault || inst->readPredicate() == false || 12752292SN/A !inst->isStoreConditional()) { 12762301SN/A // If the instruction faulted, then we need to send it along 12772292SN/A // to commit without the instruction completing. 12782292SN/A // Send this instruction to commit, also make sure iew stage 12792292SN/A // realizes there is activity. 12802292SN/A inst->setExecuted(); 12812292SN/A instToCommit(inst); 12822292SN/A activityThisCycle(); 12832292SN/A } 12842292SN/A 12852292SN/A // Store conditionals will mark themselves as 12864632Sgblack@eecs.umich.edu // executed, and their writeback event will add the 12872292SN/A // instruction to the queue to commit. 12882292SN/A } else { 12892292SN/A panic("Unexpected memory type!\n"); 12902292SN/A } 12912292SN/A 12922292SN/A } else { 12932292SN/A // If the instruction has already faulted, then skip executing it. 12942292SN/A // Such case can happen when it faulted during ITLB translation. 12952292SN/A // If we execute the instruction (even if it's a nop) the fault 12962292SN/A // will be replaced and we will lose it. 12972292SN/A if (inst->getFault() == NoFault) { 12982292SN/A inst->execute(); 12992292SN/A if (inst->readPredicate() == false) 13002292SN/A inst->forwardOldRegs(); 13012292SN/A } 13022292SN/A 13032292SN/A inst->setExecuted(); 13042292SN/A 13052292SN/A instToCommit(inst); 13062292SN/A } 13072292SN/A 13082292SN/A updateExeInstStats(inst); 13093798Sgblack@eecs.umich.edu 13103798Sgblack@eecs.umich.edu // Check if branch prediction was correct, if not then we need 13113798Sgblack@eecs.umich.edu // to tell commit to squash in flight instructions. Only 13122292SN/A // handle this if there hasn't already been something that 13133798Sgblack@eecs.umich.edu // redirects fetch in this group of instructions. 13143798Sgblack@eecs.umich.edu 13153798Sgblack@eecs.umich.edu // This probably needs to prioritize the redirects if a different 13163798Sgblack@eecs.umich.edu // scheduler is used. Currently the scheduler schedules the oldest 13173798Sgblack@eecs.umich.edu // instruction first, so the branch resolution order will be correct. 13183798Sgblack@eecs.umich.edu ThreadID tid = inst->threadNumber; 13193798Sgblack@eecs.umich.edu 13203798Sgblack@eecs.umich.edu if (!fetchRedirect[tid] || 13213788Sgblack@eecs.umich.edu !toCommit->squash[tid] || 13223788Sgblack@eecs.umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13232292SN/A 13243788Sgblack@eecs.umich.edu // Prevent testing for misprediction on load instructions, 13253788Sgblack@eecs.umich.edu // that have not been executed. 13263788Sgblack@eecs.umich.edu bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13272292SN/A 13282292SN/A if (inst->mispredicted() && !loadNotExecuted) { 13292301SN/A fetchRedirect[tid] = true; 13302292SN/A 13312301SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13322292SN/A DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13332292SN/A inst->predInstAddr(), inst->predNextInstAddr()); 13342301SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13352292SN/A inst->pcState(), inst->nextInstAddr()); 13362292SN/A // If incorrect, then signal the ROB that it must be squashed. 13372292SN/A squashDueToBranch(inst, tid); 13382292SN/A 13392292SN/A if (inst->readPredTaken()) { 13402292SN/A predictedTakenIncorrect++; 13417720Sgblack@eecs.umich.edu } else { 13422292SN/A predictedNotTakenIncorrect++; 13432292SN/A } 13442301SN/A } else if (ldstQueue.violation(tid)) { 13452292SN/A assert(inst->isMemRef()); 13462292SN/A // If there was an ordering violation, then get the 13472301SN/A // DynInst that caused the violation. Note that this 13482292SN/A // clears the violation signal. 13492301SN/A DynInstPtr violator; 13502292SN/A violator = ldstQueue.getMemDepViolator(tid); 13512292SN/A 13522292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13532703Sktlim@umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13542292SN/A violator->pcState(), violator->seqNum, 13552301SN/A inst->pcState(), inst->seqNum, inst->physEffAddr); 13562292SN/A 13572292SN/A fetchRedirect[tid] = true; 13582292SN/A 13592292SN/A // Tell the instruction queue that a violation has occured. 13602292SN/A instQueue.violation(inst, violator); 13612292SN/A 13622292SN/A // Squash. 13631061SN/A squashDueToMemOrder(inst,tid); 13641061SN/A 13651060SN/A ++memOrderViolationEvents; 13661060SN/A } else if (ldstQueue.loadBlocked(tid) && 13676221Snate@binkert.org !ldstQueue.isLoadBlockedHandled(tid)) { 13681060SN/A fetchRedirect[tid] = true; 13692292SN/A 13702292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13712292SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 13721060SN/A inst->pcState(), inst->seqNum); 13731060SN/A 13741060SN/A squashDueToMemBlocked(inst, tid); 13752292SN/A } 13762292SN/A } else { 13772292SN/A // Reset any state associated with redirects that will not 13782292SN/A // be used. 13792292SN/A if (ldstQueue.violation(tid)) { 13802292SN/A assert(inst->isMemRef()); 13812292SN/A 13822292SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13832292SN/A 13842292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13852292SN/A "%s, inst PC: %s. Addr is: %#x.\n", 13862292SN/A violator->pcState(), inst->pcState(), 13872292SN/A inst->physEffAddr); 13882292SN/A DPRINTF(IEW, "Violation will not be handled because " 13892292SN/A "already squashing\n"); 139010239Sbinhpham@cs.rutgers.edu 139110239Sbinhpham@cs.rutgers.edu ++memOrderViolationEvents; 139210239Sbinhpham@cs.rutgers.edu } 139310239Sbinhpham@cs.rutgers.edu if (ldstQueue.loadBlocked(tid) && 139410239Sbinhpham@cs.rutgers.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13952292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13962292SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 13972292SN/A inst->pcState(), inst->seqNum); 13982292SN/A DPRINTF(IEW, "Blocked load will not be handled because " 13991060SN/A "already squashing\n"); 14002292SN/A 14011060SN/A ldstQueue.setLoadBlockedHandled(tid); 14022292SN/A } 14032292SN/A 14042292SN/A } 14052292SN/A } 14062980Sgblack@eecs.umich.edu 14071060SN/A // Update and record activity if we processed any instructions. 14086221Snate@binkert.org if (inst_num) { 14091060SN/A if (exeStatus == Idle) { 14106221Snate@binkert.org exeStatus = Running; 14111060SN/A } 14126221Snate@binkert.org 141312105Snathanael.premillieu@arm.com updatedQueues = true; 141412105Snathanael.premillieu@arm.com 141512105Snathanael.premillieu@arm.com cpu->activityThisCycle(); 141612106SRekai.GonzalezAlberquilla@arm.com } 141712106SRekai.GonzalezAlberquilla@arm.com 141812106SRekai.GonzalezAlberquilla@arm.com // Need to reset this in case a writeback event needs to write into the 141912106SRekai.GonzalezAlberquilla@arm.com // iew queue. That way the writeback event will write into the correct 142012106SRekai.GonzalezAlberquilla@arm.com // spot in the queue. 142112106SRekai.GonzalezAlberquilla@arm.com wbNumInst = 0; 14221060SN/A 14232292SN/A} 14241062SN/A 14251060SN/Atemplate <class Impl> 14261060SN/Avoid 14279944Smatt.horsnell@ARM.comDefaultIEW<Impl>::writebackInsts() 14289944Smatt.horsnell@ARM.com{ 1429 // Loop through the head of the time buffer and wake any 1430 // dependents. These instructions are about to write back. Also 1431 // mark scoreboard that this instruction is finally complete. 1432 // Either have IEW have direct access to scoreboard, or have this 1433 // as part of backwards communication. 1434 for (int inst_num = 0; inst_num < wbWidth && 1435 toCommit->insts[inst_num]; inst_num++) { 1436 DynInstPtr inst = toCommit->insts[inst_num]; 1437 ThreadID tid = inst->threadNumber; 1438 1439 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1440 inst->seqNum, inst->pcState()); 1441 1442 iewInstsToCommit[tid]++; 1443 1444 // Some instructions will be sent to commit without having 1445 // executed because they need commit to handle them. 1446 // E.g. Uncached loads have not actually executed when they 1447 // are first sent to commit. Instead commit must tell the LSQ 1448 // when it's ready to execute the uncached load. 1449 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1450 int dependents = instQueue.wakeDependents(inst); 1451 1452 for (int i = 0; i < inst->numDestRegs(); i++) { 1453 //mark as Ready 1454 DPRINTF(IEW,"Setting Destination Register %i\n", 1455 inst->renamedDestRegIdx(i)); 1456 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1457 } 1458 1459 if (dependents) { 1460 producerInst[tid]++; 1461 consumerInst[tid]+= dependents; 1462 } 1463 writebackCount[tid]++; 1464 } 1465 1466 decrWb(inst->seqNum); 1467 } 1468} 1469 1470template<class Impl> 1471void 1472DefaultIEW<Impl>::tick() 1473{ 1474 wbNumInst = 0; 1475 wbCycle = 0; 1476 1477 wroteToTimeBuffer = false; 1478 updatedQueues = false; 1479 1480 sortInsts(); 1481 1482 // Free function units marked as being freed this cycle. 1483 fuPool->processFreeUnits(); 1484 1485 list<ThreadID>::iterator threads = activeThreads->begin(); 1486 list<ThreadID>::iterator end = activeThreads->end(); 1487 1488 // Check stall and squash signals, dispatch any instructions. 1489 while (threads != end) { 1490 ThreadID tid = *threads++; 1491 1492 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1493 1494 checkSignalsAndUpdate(tid); 1495 dispatch(tid); 1496 } 1497 1498 if (exeStatus != Squashing) { 1499 executeInsts(); 1500 1501 writebackInsts(); 1502 1503 // Have the instruction queue try to schedule any ready instructions. 1504 // (In actuality, this scheduling is for instructions that will 1505 // be executed next cycle.) 1506 instQueue.scheduleReadyInsts(); 1507 1508 // Also should advance its own time buffers if the stage ran. 1509 // Not the best place for it, but this works (hopefully). 1510 issueToExecQueue.advance(); 1511 } 1512 1513 bool broadcast_free_entries = false; 1514 1515 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1516 exeStatus = Idle; 1517 updateLSQNextCycle = false; 1518 1519 broadcast_free_entries = true; 1520 } 1521 1522 // Writeback any stores using any leftover bandwidth. 1523 ldstQueue.writebackStores(); 1524 1525 // Check the committed load/store signals to see if there's a load 1526 // or store to commit. Also check if it's being told to execute a 1527 // nonspeculative instruction. 1528 // This is pretty inefficient... 1529 1530 threads = activeThreads->begin(); 1531 while (threads != end) { 1532 ThreadID tid = (*threads++); 1533 1534 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1535 1536 // Update structures based on instructions committed. 1537 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1538 !fromCommit->commitInfo[tid].squash && 1539 !fromCommit->commitInfo[tid].robSquashing) { 1540 1541 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1542 1543 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1544 1545 updateLSQNextCycle = true; 1546 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1547 } 1548 1549 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1550 1551 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1552 if (fromCommit->commitInfo[tid].uncached) { 1553 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1554 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1555 } else { 1556 instQueue.scheduleNonSpec( 1557 fromCommit->commitInfo[tid].nonSpecSeqNum); 1558 } 1559 } 1560 1561 if (broadcast_free_entries) { 1562 toFetch->iewInfo[tid].iqCount = 1563 instQueue.getCount(tid); 1564 toFetch->iewInfo[tid].ldstqCount = 1565 ldstQueue.getCount(tid); 1566 1567 toRename->iewInfo[tid].usedIQ = true; 1568 toRename->iewInfo[tid].freeIQEntries = 1569 instQueue.numFreeEntries(); 1570 toRename->iewInfo[tid].usedLSQ = true; 1571 toRename->iewInfo[tid].freeLSQEntries = 1572 ldstQueue.numFreeEntries(tid); 1573 1574 wroteToTimeBuffer = true; 1575 } 1576 1577 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1578 tid, toRename->iewInfo[tid].dispatched); 1579 } 1580 1581 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1582 "LSQ has %i free entries.\n", 1583 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1584 ldstQueue.numFreeEntries()); 1585 1586 updateStatus(); 1587 1588 if (wroteToTimeBuffer) { 1589 DPRINTF(Activity, "Activity this cycle.\n"); 1590 cpu->activityThisCycle(); 1591 } 1592} 1593 1594template <class Impl> 1595void 1596DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1597{ 1598 ThreadID tid = inst->threadNumber; 1599 1600 // 1601 // Pick off the software prefetches 1602 // 1603#ifdef TARGET_ALPHA 1604 if (inst->isDataPrefetch()) 1605 iewExecutedSwp[tid]++; 1606 else 1607 iewIewExecutedcutedInsts++; 1608#else 1609 iewExecutedInsts++; 1610#endif 1611 1612 // 1613 // Control operations 1614 // 1615 if (inst->isControl()) 1616 iewExecutedBranches[tid]++; 1617 1618 // 1619 // Memory operations 1620 // 1621 if (inst->isMemRef()) { 1622 iewExecutedRefs[tid]++; 1623 1624 if (inst->isLoad()) { 1625 iewExecLoadInsts[tid]++; 1626 } 1627 } 1628} 1629 1630template <class Impl> 1631void 1632DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1633{ 1634 ThreadID tid = inst->threadNumber; 1635 1636 if (!fetchRedirect[tid] || 1637 !toCommit->squash[tid] || 1638 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1639 1640 if (inst->mispredicted()) { 1641 fetchRedirect[tid] = true; 1642 1643 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1644 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1645 inst->predInstAddr(), inst->predNextInstAddr()); 1646 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1647 " NPC: %#x.\n", inst->nextInstAddr(), 1648 inst->nextInstAddr()); 1649 // If incorrect, then signal the ROB that it must be squashed. 1650 squashDueToBranch(inst, tid); 1651 1652 if (inst->readPredTaken()) { 1653 predictedTakenIncorrect++; 1654 } else { 1655 predictedNotTakenIncorrect++; 1656 } 1657 } 1658 } 1659} 1660