iew_impl.hh revision 8230
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 431060SN/A// @todo: Fix the instantaneous communication among all the stages within 441060SN/A// iew. There's a clear delay between issue and execute, yet backwards 451689SN/A// communication happens simultaneously. 461060SN/A 471060SN/A#include <queue> 481060SN/A 498230Snate@binkert.org#include "arch/utility.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/iew.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 545529Snate@binkert.org#include "params/DerivO3CPU.hh" 551060SN/A 566221Snate@binkert.orgusing namespace std; 576221Snate@binkert.org 581681SN/Atemplate<class Impl> 595529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 602873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 614329Sktlim@umich.edu cpu(_cpu), 624329Sktlim@umich.edu instQueue(_cpu, this, params), 634329Sktlim@umich.edu ldstQueue(_cpu, this, params), 642292SN/A fuPool(params->fuPool), 652292SN/A commitToIEWDelay(params->commitToIEWDelay), 662292SN/A renameToIEWDelay(params->renameToIEWDelay), 672292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 682820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 692292SN/A issueWidth(params->issueWidth), 702820Sktlim@umich.edu wbOutstanding(0), 712820Sktlim@umich.edu wbWidth(params->wbWidth), 725529Snate@binkert.org numThreads(params->numThreads), 732307SN/A switchedOut(false) 741060SN/A{ 752292SN/A _status = Active; 762292SN/A exeStatus = Running; 772292SN/A wbStatus = Idle; 781060SN/A 791060SN/A // Setup wire to read instructions coming from issue. 801060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 811060SN/A 821060SN/A // Instruction queue needs the queue between issue and execute. 831060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 841681SN/A 856221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 866221Snate@binkert.org dispatchStatus[tid] = Running; 876221Snate@binkert.org stalls[tid].commit = false; 886221Snate@binkert.org fetchRedirect[tid] = false; 892292SN/A } 902292SN/A 912820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 922820Sktlim@umich.edu 932292SN/A updateLSQNextCycle = false; 942292SN/A 952820Sktlim@umich.edu ableToIssue = true; 962820Sktlim@umich.edu 972292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 982292SN/A} 992292SN/A 1002292SN/Atemplate <class Impl> 1012292SN/Astd::string 1022292SN/ADefaultIEW<Impl>::name() const 1032292SN/A{ 1042292SN/A return cpu->name() + ".iew"; 1051060SN/A} 1061060SN/A 1071681SN/Atemplate <class Impl> 1081062SN/Avoid 1092292SN/ADefaultIEW<Impl>::regStats() 1101062SN/A{ 1112301SN/A using namespace Stats; 1122301SN/A 1131062SN/A instQueue.regStats(); 1142727Sktlim@umich.edu ldstQueue.regStats(); 1151062SN/A 1161062SN/A iewIdleCycles 1171062SN/A .name(name() + ".iewIdleCycles") 1181062SN/A .desc("Number of cycles IEW is idle"); 1191062SN/A 1201062SN/A iewSquashCycles 1211062SN/A .name(name() + ".iewSquashCycles") 1221062SN/A .desc("Number of cycles IEW is squashing"); 1231062SN/A 1241062SN/A iewBlockCycles 1251062SN/A .name(name() + ".iewBlockCycles") 1261062SN/A .desc("Number of cycles IEW is blocking"); 1271062SN/A 1281062SN/A iewUnblockCycles 1291062SN/A .name(name() + ".iewUnblockCycles") 1301062SN/A .desc("Number of cycles IEW is unblocking"); 1311062SN/A 1321062SN/A iewDispatchedInsts 1331062SN/A .name(name() + ".iewDispatchedInsts") 1341062SN/A .desc("Number of instructions dispatched to IQ"); 1351062SN/A 1361062SN/A iewDispSquashedInsts 1371062SN/A .name(name() + ".iewDispSquashedInsts") 1381062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1391062SN/A 1401062SN/A iewDispLoadInsts 1411062SN/A .name(name() + ".iewDispLoadInsts") 1421062SN/A .desc("Number of dispatched load instructions"); 1431062SN/A 1441062SN/A iewDispStoreInsts 1451062SN/A .name(name() + ".iewDispStoreInsts") 1461062SN/A .desc("Number of dispatched store instructions"); 1471062SN/A 1481062SN/A iewDispNonSpecInsts 1491062SN/A .name(name() + ".iewDispNonSpecInsts") 1501062SN/A .desc("Number of dispatched non-speculative instructions"); 1511062SN/A 1521062SN/A iewIQFullEvents 1531062SN/A .name(name() + ".iewIQFullEvents") 1541062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1551062SN/A 1562292SN/A iewLSQFullEvents 1572292SN/A .name(name() + ".iewLSQFullEvents") 1582292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1592292SN/A 1601062SN/A memOrderViolationEvents 1611062SN/A .name(name() + ".memOrderViolationEvents") 1621062SN/A .desc("Number of memory order violations"); 1631062SN/A 1641062SN/A predictedTakenIncorrect 1651062SN/A .name(name() + ".predictedTakenIncorrect") 1661062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1672292SN/A 1682292SN/A predictedNotTakenIncorrect 1692292SN/A .name(name() + ".predictedNotTakenIncorrect") 1702292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1712292SN/A 1722292SN/A branchMispredicts 1732292SN/A .name(name() + ".branchMispredicts") 1742292SN/A .desc("Number of branch mispredicts detected at execute"); 1752292SN/A 1762292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1772301SN/A 1782727Sktlim@umich.edu iewExecutedInsts 1792353SN/A .name(name() + ".iewExecutedInsts") 1802727Sktlim@umich.edu .desc("Number of executed instructions"); 1812727Sktlim@umich.edu 1822727Sktlim@umich.edu iewExecLoadInsts 1836221Snate@binkert.org .init(cpu->numThreads) 1842353SN/A .name(name() + ".iewExecLoadInsts") 1852727Sktlim@umich.edu .desc("Number of load instructions executed") 1862727Sktlim@umich.edu .flags(total); 1872727Sktlim@umich.edu 1882727Sktlim@umich.edu iewExecSquashedInsts 1892353SN/A .name(name() + ".iewExecSquashedInsts") 1902727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1912727Sktlim@umich.edu 1922727Sktlim@umich.edu iewExecutedSwp 1936221Snate@binkert.org .init(cpu->numThreads) 1942301SN/A .name(name() + ".EXEC:swp") 1952301SN/A .desc("number of swp insts executed") 1962727Sktlim@umich.edu .flags(total); 1972301SN/A 1982727Sktlim@umich.edu iewExecutedNop 1996221Snate@binkert.org .init(cpu->numThreads) 2002301SN/A .name(name() + ".EXEC:nop") 2012301SN/A .desc("number of nop insts executed") 2022727Sktlim@umich.edu .flags(total); 2032301SN/A 2042727Sktlim@umich.edu iewExecutedRefs 2056221Snate@binkert.org .init(cpu->numThreads) 2062301SN/A .name(name() + ".EXEC:refs") 2072301SN/A .desc("number of memory reference insts executed") 2082727Sktlim@umich.edu .flags(total); 2092301SN/A 2102727Sktlim@umich.edu iewExecutedBranches 2116221Snate@binkert.org .init(cpu->numThreads) 2122301SN/A .name(name() + ".EXEC:branches") 2132301SN/A .desc("Number of branches executed") 2142727Sktlim@umich.edu .flags(total); 2152301SN/A 2162301SN/A iewExecStoreInsts 2172301SN/A .name(name() + ".EXEC:stores") 2182301SN/A .desc("Number of stores executed") 2192727Sktlim@umich.edu .flags(total); 2202727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2212727Sktlim@umich.edu 2222727Sktlim@umich.edu iewExecRate 2232727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2242727Sktlim@umich.edu .desc("Inst execution rate") 2252727Sktlim@umich.edu .flags(total); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2282301SN/A 2292301SN/A iewInstsToCommit 2306221Snate@binkert.org .init(cpu->numThreads) 2312301SN/A .name(name() + ".WB:sent") 2322301SN/A .desc("cumulative count of insts sent to commit") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352326SN/A writebackCount 2366221Snate@binkert.org .init(cpu->numThreads) 2372301SN/A .name(name() + ".WB:count") 2382301SN/A .desc("cumulative count of insts written-back") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412326SN/A producerInst 2426221Snate@binkert.org .init(cpu->numThreads) 2432301SN/A .name(name() + ".WB:producers") 2442301SN/A .desc("num instructions producing a value") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472326SN/A consumerInst 2486221Snate@binkert.org .init(cpu->numThreads) 2492301SN/A .name(name() + ".WB:consumers") 2502301SN/A .desc("num instructions consuming a value") 2512727Sktlim@umich.edu .flags(total); 2522301SN/A 2532326SN/A wbPenalized 2546221Snate@binkert.org .init(cpu->numThreads) 2552301SN/A .name(name() + ".WB:penalized") 2562301SN/A .desc("number of instrctions required to write to 'other' IQ") 2572727Sktlim@umich.edu .flags(total); 2582301SN/A 2592326SN/A wbPenalizedRate 2602301SN/A .name(name() + ".WB:penalized_rate") 2612301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2622727Sktlim@umich.edu .flags(total); 2632301SN/A 2642326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2652301SN/A 2662326SN/A wbFanout 2672301SN/A .name(name() + ".WB:fanout") 2682301SN/A .desc("average fanout of values written-back") 2692727Sktlim@umich.edu .flags(total); 2702301SN/A 2712326SN/A wbFanout = producerInst / consumerInst; 2722301SN/A 2732326SN/A wbRate 2742301SN/A .name(name() + ".WB:rate") 2752301SN/A .desc("insts written-back per cycle") 2762727Sktlim@umich.edu .flags(total); 2772326SN/A wbRate = writebackCount / cpu->numCycles; 2781062SN/A} 2791062SN/A 2801681SN/Atemplate<class Impl> 2811060SN/Avoid 2822292SN/ADefaultIEW<Impl>::initStage() 2831060SN/A{ 2846221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2852292SN/A toRename->iewInfo[tid].usedIQ = true; 2862292SN/A toRename->iewInfo[tid].freeIQEntries = 2872292SN/A instQueue.numFreeEntries(tid); 2882292SN/A 2892292SN/A toRename->iewInfo[tid].usedLSQ = true; 2902292SN/A toRename->iewInfo[tid].freeLSQEntries = 2912292SN/A ldstQueue.numFreeEntries(tid); 2922292SN/A } 2932292SN/A 2942733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2951060SN/A} 2961060SN/A 2971681SN/Atemplate<class Impl> 2981060SN/Avoid 2992292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3001060SN/A{ 3011060SN/A timeBuffer = tb_ptr; 3021060SN/A 3031060SN/A // Setup wire to read information from time buffer, from commit. 3041060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3051060SN/A 3061060SN/A // Setup wire to write information back to previous stages. 3071060SN/A toRename = timeBuffer->getWire(0); 3081060SN/A 3092292SN/A toFetch = timeBuffer->getWire(0); 3102292SN/A 3111060SN/A // Instruction queue also needs main time buffer. 3121060SN/A instQueue.setTimeBuffer(tb_ptr); 3131060SN/A} 3141060SN/A 3151681SN/Atemplate<class Impl> 3161060SN/Avoid 3172292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3181060SN/A{ 3191060SN/A renameQueue = rq_ptr; 3201060SN/A 3211060SN/A // Setup wire to read information from rename queue. 3221060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3231060SN/A} 3241060SN/A 3251681SN/Atemplate<class Impl> 3261060SN/Avoid 3272292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3281060SN/A{ 3291060SN/A iewQueue = iq_ptr; 3301060SN/A 3311060SN/A // Setup wire to write instructions to commit. 3321060SN/A toCommit = iewQueue->getWire(0); 3331060SN/A} 3341060SN/A 3351681SN/Atemplate<class Impl> 3361060SN/Avoid 3376221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3381060SN/A{ 3392292SN/A activeThreads = at_ptr; 3402292SN/A 3412292SN/A ldstQueue.setActiveThreads(at_ptr); 3422292SN/A instQueue.setActiveThreads(at_ptr); 3431060SN/A} 3441060SN/A 3451681SN/Atemplate<class Impl> 3461060SN/Avoid 3472292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3481060SN/A{ 3492292SN/A scoreboard = sb_ptr; 3501060SN/A} 3511060SN/A 3522307SN/Atemplate <class Impl> 3532863Sktlim@umich.edubool 3542843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3552307SN/A{ 3562843Sktlim@umich.edu // IEW is ready to drain at any time. 3572843Sktlim@umich.edu cpu->signalDrained(); 3582863Sktlim@umich.edu return true; 3591681SN/A} 3601681SN/A 3612316SN/Atemplate <class Impl> 3621681SN/Avoid 3632843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3642843Sktlim@umich.edu{ 3652843Sktlim@umich.edu} 3662843Sktlim@umich.edu 3672843Sktlim@umich.edutemplate <class Impl> 3682843Sktlim@umich.eduvoid 3692843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3701681SN/A{ 3712348SN/A // Clear any state. 3722307SN/A switchedOut = true; 3732367SN/A assert(insts[0].empty()); 3742367SN/A assert(skidBuffer[0].empty()); 3751681SN/A 3762307SN/A instQueue.switchOut(); 3772307SN/A ldstQueue.switchOut(); 3782307SN/A fuPool->switchOut(); 3792307SN/A 3806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3816221Snate@binkert.org while (!insts[tid].empty()) 3826221Snate@binkert.org insts[tid].pop(); 3836221Snate@binkert.org while (!skidBuffer[tid].empty()) 3846221Snate@binkert.org skidBuffer[tid].pop(); 3852307SN/A } 3861681SN/A} 3871681SN/A 3882307SN/Atemplate <class Impl> 3891681SN/Avoid 3902307SN/ADefaultIEW<Impl>::takeOverFrom() 3911060SN/A{ 3922348SN/A // Reset all state. 3932307SN/A _status = Active; 3942307SN/A exeStatus = Running; 3952307SN/A wbStatus = Idle; 3962307SN/A switchedOut = false; 3971060SN/A 3982307SN/A instQueue.takeOverFrom(); 3992307SN/A ldstQueue.takeOverFrom(); 4002307SN/A fuPool->takeOverFrom(); 4011060SN/A 4022307SN/A initStage(); 4032307SN/A cpu->activityThisCycle(); 4041060SN/A 4056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4066221Snate@binkert.org dispatchStatus[tid] = Running; 4076221Snate@binkert.org stalls[tid].commit = false; 4086221Snate@binkert.org fetchRedirect[tid] = false; 4092307SN/A } 4101060SN/A 4112307SN/A updateLSQNextCycle = false; 4122307SN/A 4132873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4142307SN/A issueToExecQueue.advance(); 4151060SN/A } 4161060SN/A} 4171060SN/A 4181681SN/Atemplate<class Impl> 4191060SN/Avoid 4206221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4212107SN/A{ 4226221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4232107SN/A 4242292SN/A // Tell the IQ to start squashing. 4252292SN/A instQueue.squash(tid); 4262107SN/A 4272292SN/A // Tell the LDSTQ to start squashing. 4282326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4292292SN/A updatedQueues = true; 4302107SN/A 4312292SN/A // Clear the skid buffer in case it has any data in it. 4322935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4334632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4342935Sksewell@umich.edu 4352292SN/A while (!skidBuffer[tid].empty()) { 4362292SN/A if (skidBuffer[tid].front()->isLoad() || 4372292SN/A skidBuffer[tid].front()->isStore() ) { 4382292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4392292SN/A } 4402107SN/A 4412292SN/A toRename->iewInfo[tid].dispatched++; 4422107SN/A 4432292SN/A skidBuffer[tid].pop(); 4442292SN/A } 4452107SN/A 4462702Sktlim@umich.edu emptyRenameInsts(tid); 4472107SN/A} 4482107SN/A 4492107SN/Atemplate<class Impl> 4502107SN/Avoid 4516221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4522292SN/A{ 4537720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4547720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4552292SN/A 4567852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4577852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4587852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4597852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4607852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4612935Sksewell@umich.edu 4627852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4637852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4642292SN/A 4657852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4667852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4677852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4682292SN/A 4697852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4707852SMatt.Horsnell@arm.com } 4717852SMatt.Horsnell@arm.com 4722292SN/A} 4732292SN/A 4742292SN/Atemplate<class Impl> 4752292SN/Avoid 4766221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4772292SN/A{ 4782292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4797720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4802292SN/A 4817852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4827852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4837852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4847852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4857852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4867852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4877852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4888137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 4892292SN/A 4907852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4912292SN/A 4927852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4937852SMatt.Horsnell@arm.com } 4942292SN/A} 4952292SN/A 4962292SN/Atemplate<class Impl> 4972292SN/Avoid 4986221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 4992292SN/A{ 5002292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5017720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5027852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5037852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5047852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5052292SN/A 5067852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5077852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5088137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5092292SN/A 5107852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5117852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5122292SN/A 5137852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5142292SN/A 5157852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5167852SMatt.Horsnell@arm.com } 5172292SN/A} 5182292SN/A 5192292SN/Atemplate<class Impl> 5202292SN/Avoid 5216221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5222292SN/A{ 5232292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5242292SN/A 5252292SN/A if (dispatchStatus[tid] != Blocked && 5262292SN/A dispatchStatus[tid] != Unblocking) { 5272292SN/A toRename->iewBlock[tid] = true; 5282292SN/A wroteToTimeBuffer = true; 5292292SN/A } 5302292SN/A 5312292SN/A // Add the current inputs to the skid buffer so they can be 5322292SN/A // reprocessed when this stage unblocks. 5332292SN/A skidInsert(tid); 5342292SN/A 5352292SN/A dispatchStatus[tid] = Blocked; 5362292SN/A} 5372292SN/A 5382292SN/Atemplate<class Impl> 5392292SN/Avoid 5406221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5412292SN/A{ 5422292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5432292SN/A "buffer %u.\n",tid, tid); 5442292SN/A 5452292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5462292SN/A // Also switch status to running. 5472292SN/A if (skidBuffer[tid].empty()) { 5482292SN/A toRename->iewUnblock[tid] = true; 5492292SN/A wroteToTimeBuffer = true; 5502292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5512292SN/A dispatchStatus[tid] = Running; 5522292SN/A } 5532292SN/A} 5542292SN/A 5552292SN/Atemplate<class Impl> 5562292SN/Avoid 5572292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5581060SN/A{ 5591681SN/A instQueue.wakeDependents(inst); 5601060SN/A} 5611060SN/A 5622292SN/Atemplate<class Impl> 5632292SN/Avoid 5642292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5652292SN/A{ 5662292SN/A instQueue.rescheduleMemInst(inst); 5672292SN/A} 5681681SN/A 5691681SN/Atemplate<class Impl> 5701060SN/Avoid 5712292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5721060SN/A{ 5732292SN/A instQueue.replayMemInst(inst); 5742292SN/A} 5751060SN/A 5762292SN/Atemplate<class Impl> 5772292SN/Avoid 5782292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5792292SN/A{ 5803221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5813221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5823221Sktlim@umich.edu // being added to the queue to commit without being processed by 5833221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5843221Sktlim@umich.edu 5852292SN/A // First check the time slot that this instruction will write 5862292SN/A // to. If there are free write ports at the time, then go ahead 5872292SN/A // and write the instruction to that time. If there are not, 5882292SN/A // keep looking back to see where's the first time there's a 5892326SN/A // free slot. 5902292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5912292SN/A ++wbNumInst; 5922820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5932292SN/A ++wbCycle; 5942292SN/A wbNumInst = 0; 5952292SN/A } 5962292SN/A 5972353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5982292SN/A } 5992292SN/A 6002353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6012353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6022292SN/A // Add finished instruction to queue to commit. 6032292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6042292SN/A (*iewQueue)[wbCycle].size++; 6052292SN/A} 6062292SN/A 6072292SN/Atemplate <class Impl> 6082292SN/Aunsigned 6092292SN/ADefaultIEW<Impl>::validInstsFromRename() 6102292SN/A{ 6112292SN/A unsigned inst_count = 0; 6122292SN/A 6132292SN/A for (int i=0; i<fromRename->size; i++) { 6142731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6152292SN/A inst_count++; 6162292SN/A } 6172292SN/A 6182292SN/A return inst_count; 6192292SN/A} 6202292SN/A 6212292SN/Atemplate<class Impl> 6222292SN/Avoid 6236221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6242292SN/A{ 6252292SN/A DynInstPtr inst = NULL; 6262292SN/A 6272292SN/A while (!insts[tid].empty()) { 6282292SN/A inst = insts[tid].front(); 6292292SN/A 6302292SN/A insts[tid].pop(); 6312292SN/A 6327720Sgblack@eecs.umich.edu DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6332292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6347720Sgblack@eecs.umich.edu inst->pcState(),tid); 6352292SN/A 6362292SN/A skidBuffer[tid].push(inst); 6372292SN/A } 6382292SN/A 6392292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6402292SN/A "Skidbuffer Exceeded Max Size"); 6412292SN/A} 6422292SN/A 6432292SN/Atemplate<class Impl> 6442292SN/Aint 6452292SN/ADefaultIEW<Impl>::skidCount() 6462292SN/A{ 6472292SN/A int max=0; 6482292SN/A 6496221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6506221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6512292SN/A 6523867Sbinkertn@umich.edu while (threads != end) { 6536221Snate@binkert.org ThreadID tid = *threads++; 6543867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6552292SN/A if (max < thread_count) 6562292SN/A max = thread_count; 6572292SN/A } 6582292SN/A 6592292SN/A return max; 6602292SN/A} 6612292SN/A 6622292SN/Atemplate<class Impl> 6632292SN/Abool 6642292SN/ADefaultIEW<Impl>::skidsEmpty() 6652292SN/A{ 6666221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6676221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6682292SN/A 6693867Sbinkertn@umich.edu while (threads != end) { 6706221Snate@binkert.org ThreadID tid = *threads++; 6713867Sbinkertn@umich.edu 6723867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6732292SN/A return false; 6742292SN/A } 6752292SN/A 6762292SN/A return true; 6771062SN/A} 6781062SN/A 6791681SN/Atemplate <class Impl> 6801062SN/Avoid 6812292SN/ADefaultIEW<Impl>::updateStatus() 6821062SN/A{ 6832292SN/A bool any_unblocking = false; 6841062SN/A 6856221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6866221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6871062SN/A 6883867Sbinkertn@umich.edu while (threads != end) { 6896221Snate@binkert.org ThreadID tid = *threads++; 6901062SN/A 6912292SN/A if (dispatchStatus[tid] == Unblocking) { 6922292SN/A any_unblocking = true; 6932292SN/A break; 6942292SN/A } 6952292SN/A } 6961062SN/A 6972292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6982292SN/A // and there's no stores waiting to write back, and dispatch is not 6992292SN/A // unblocking, then there is no internal activity for the IEW stage. 7007897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7012292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7022292SN/A !ldstQueue.willWB() && !any_unblocking) { 7032292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7041062SN/A 7052292SN/A deactivateStage(); 7061062SN/A 7072292SN/A _status = Inactive; 7082292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7092292SN/A ldstQueue.willWB() || 7102292SN/A any_unblocking)) { 7112292SN/A // Otherwise there is internal activity. Set to active. 7122292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7131062SN/A 7142292SN/A activateStage(); 7151062SN/A 7162292SN/A _status = Active; 7171062SN/A } 7181062SN/A} 7191062SN/A 7201681SN/Atemplate <class Impl> 7211062SN/Avoid 7222292SN/ADefaultIEW<Impl>::resetEntries() 7231062SN/A{ 7242292SN/A instQueue.resetEntries(); 7252292SN/A ldstQueue.resetEntries(); 7262292SN/A} 7271062SN/A 7282292SN/Atemplate <class Impl> 7292292SN/Avoid 7306221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7312292SN/A{ 7322292SN/A if (fromCommit->commitBlock[tid]) { 7332292SN/A stalls[tid].commit = true; 7342292SN/A } 7351062SN/A 7362292SN/A if (fromCommit->commitUnblock[tid]) { 7372292SN/A assert(stalls[tid].commit); 7382292SN/A stalls[tid].commit = false; 7392292SN/A } 7402292SN/A} 7412292SN/A 7422292SN/Atemplate <class Impl> 7432292SN/Abool 7446221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7452292SN/A{ 7462292SN/A bool ret_val(false); 7472292SN/A 7482292SN/A if (stalls[tid].commit) { 7492292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7502292SN/A ret_val = true; 7512292SN/A } else if (instQueue.isFull(tid)) { 7522292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7532292SN/A ret_val = true; 7542292SN/A } else if (ldstQueue.isFull(tid)) { 7552292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7562292SN/A 7572292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7582292SN/A 7592292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7602292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7612292SN/A } 7622292SN/A 7632292SN/A if (ldstQueue.numStores(tid) > 0) { 7642292SN/A 7652292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7662292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7672292SN/A } 7682292SN/A 7692292SN/A ret_val = true; 7702292SN/A } else if (ldstQueue.isStalled(tid)) { 7712292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7722292SN/A ret_val = true; 7732292SN/A } 7742292SN/A 7752292SN/A return ret_val; 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7806221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7812292SN/A{ 7822292SN/A // Check if there's a squash signal, squash if there is 7832292SN/A // Check stall signals, block if there is. 7842292SN/A // If status was Blocked 7852292SN/A // if so then go to unblocking 7862292SN/A // If status was Squashing 7872292SN/A // check if squashing is not high. Switch to running this cycle. 7882292SN/A 7892292SN/A readStallSignals(tid); 7902292SN/A 7912292SN/A if (fromCommit->commitInfo[tid].squash) { 7922292SN/A squash(tid); 7932292SN/A 7942292SN/A if (dispatchStatus[tid] == Blocked || 7952292SN/A dispatchStatus[tid] == Unblocking) { 7962292SN/A toRename->iewUnblock[tid] = true; 7972292SN/A wroteToTimeBuffer = true; 7982292SN/A } 7992292SN/A 8002292SN/A dispatchStatus[tid] = Squashing; 8012292SN/A fetchRedirect[tid] = false; 8022292SN/A return; 8032292SN/A } 8042292SN/A 8052292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8062702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8072292SN/A 8082292SN/A dispatchStatus[tid] = Squashing; 8092702Sktlim@umich.edu emptyRenameInsts(tid); 8102702Sktlim@umich.edu wroteToTimeBuffer = true; 8112292SN/A return; 8122292SN/A } 8132292SN/A 8142292SN/A if (checkStall(tid)) { 8152292SN/A block(tid); 8162292SN/A dispatchStatus[tid] = Blocked; 8172292SN/A return; 8182292SN/A } 8192292SN/A 8202292SN/A if (dispatchStatus[tid] == Blocked) { 8212292SN/A // Status from previous cycle was blocked, but there are no more stall 8222292SN/A // conditions. Switch over to unblocking. 8232292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8242292SN/A tid); 8252292SN/A 8262292SN/A dispatchStatus[tid] = Unblocking; 8272292SN/A 8282292SN/A unblock(tid); 8292292SN/A 8302292SN/A return; 8312292SN/A } 8322292SN/A 8332292SN/A if (dispatchStatus[tid] == Squashing) { 8342292SN/A // Switch status to running if rename isn't being told to block or 8352292SN/A // squash this cycle. 8362292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8372292SN/A tid); 8382292SN/A 8392292SN/A dispatchStatus[tid] = Running; 8402292SN/A 8412292SN/A return; 8422292SN/A } 8432292SN/A} 8442292SN/A 8452292SN/Atemplate <class Impl> 8462292SN/Avoid 8472292SN/ADefaultIEW<Impl>::sortInsts() 8482292SN/A{ 8492292SN/A int insts_from_rename = fromRename->size; 8502326SN/A#ifdef DEBUG 8516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8526221Snate@binkert.org assert(insts[tid].empty()); 8532326SN/A#endif 8542292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8552292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8562292SN/A } 8572292SN/A} 8582292SN/A 8592292SN/Atemplate <class Impl> 8602292SN/Avoid 8616221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8622702Sktlim@umich.edu{ 8634632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8642935Sksewell@umich.edu 8652702Sktlim@umich.edu while (!insts[tid].empty()) { 8662935Sksewell@umich.edu 8672702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8682702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8692702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8702702Sktlim@umich.edu } 8712702Sktlim@umich.edu 8722702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8732702Sktlim@umich.edu 8742702Sktlim@umich.edu insts[tid].pop(); 8752702Sktlim@umich.edu } 8762702Sktlim@umich.edu} 8772702Sktlim@umich.edu 8782702Sktlim@umich.edutemplate <class Impl> 8792702Sktlim@umich.eduvoid 8802292SN/ADefaultIEW<Impl>::wakeCPU() 8812292SN/A{ 8822292SN/A cpu->wakeCPU(); 8832292SN/A} 8842292SN/A 8852292SN/Atemplate <class Impl> 8862292SN/Avoid 8872292SN/ADefaultIEW<Impl>::activityThisCycle() 8882292SN/A{ 8892292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8902292SN/A cpu->activityThisCycle(); 8912292SN/A} 8922292SN/A 8932292SN/Atemplate <class Impl> 8942292SN/Ainline void 8952292SN/ADefaultIEW<Impl>::activateStage() 8962292SN/A{ 8972292SN/A DPRINTF(Activity, "Activating stage.\n"); 8982733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8992292SN/A} 9002292SN/A 9012292SN/Atemplate <class Impl> 9022292SN/Ainline void 9032292SN/ADefaultIEW<Impl>::deactivateStage() 9042292SN/A{ 9052292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9062733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9072292SN/A} 9082292SN/A 9092292SN/Atemplate<class Impl> 9102292SN/Avoid 9116221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9122292SN/A{ 9132292SN/A // If status is Running or idle, 9142292SN/A // call dispatchInsts() 9152292SN/A // If status is Unblocking, 9162292SN/A // buffer any instructions coming from rename 9172292SN/A // continue trying to empty skid buffer 9182292SN/A // check if stall conditions have passed 9192292SN/A 9202292SN/A if (dispatchStatus[tid] == Blocked) { 9212292SN/A ++iewBlockCycles; 9222292SN/A 9232292SN/A } else if (dispatchStatus[tid] == Squashing) { 9242292SN/A ++iewSquashCycles; 9252292SN/A } 9262292SN/A 9272292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9282292SN/A // will allow, as long as it is not currently blocked. 9292292SN/A if (dispatchStatus[tid] == Running || 9302292SN/A dispatchStatus[tid] == Idle) { 9312292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9322292SN/A "dispatch.\n", tid); 9332292SN/A 9342292SN/A dispatchInsts(tid); 9352292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9362292SN/A // Make sure that the skid buffer has something in it if the 9372292SN/A // status is unblocking. 9382292SN/A assert(!skidsEmpty()); 9392292SN/A 9402292SN/A // If the status was unblocking, then instructions from the skid 9412292SN/A // buffer were used. Remove those instructions and handle 9422292SN/A // the rest of unblocking. 9432292SN/A dispatchInsts(tid); 9442292SN/A 9452292SN/A ++iewUnblockCycles; 9462292SN/A 9475215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9482292SN/A // Add the current inputs to the skid buffer so they can be 9492292SN/A // reprocessed when this stage unblocks. 9502292SN/A skidInsert(tid); 9512292SN/A } 9522292SN/A 9532292SN/A unblock(tid); 9542292SN/A } 9552292SN/A} 9562292SN/A 9572292SN/Atemplate <class Impl> 9582292SN/Avoid 9596221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9602292SN/A{ 9612292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9622292SN/A // otherwise. 9632292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9642292SN/A dispatchStatus[tid] == Unblocking ? 9652292SN/A skidBuffer[tid] : insts[tid]; 9662292SN/A 9672292SN/A int insts_to_add = insts_to_dispatch.size(); 9682292SN/A 9692292SN/A DynInstPtr inst; 9702292SN/A bool add_to_iq = false; 9712292SN/A int dis_num_inst = 0; 9722292SN/A 9732292SN/A // Loop through the instructions, putting them in the instruction 9742292SN/A // queue. 9752292SN/A for ( ; dis_num_inst < insts_to_add && 9762820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9772292SN/A ++dis_num_inst) 9782292SN/A { 9792292SN/A inst = insts_to_dispatch.front(); 9802292SN/A 9812292SN/A if (dispatchStatus[tid] == Unblocking) { 9822292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9832292SN/A "buffer\n", tid); 9842292SN/A } 9852292SN/A 9862292SN/A // Make sure there's a valid instruction there. 9872292SN/A assert(inst); 9882292SN/A 9897720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9902292SN/A "IQ.\n", 9917720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9922292SN/A 9932292SN/A // Be sure to mark these instructions as ready so that the 9942292SN/A // commit stage can go ahead and execute them, and mark 9952292SN/A // them as issued so the IQ doesn't reprocess them. 9962292SN/A 9972292SN/A // Check for squashed instructions. 9982292SN/A if (inst->isSquashed()) { 9992292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10002292SN/A "not adding to IQ.\n", tid); 10012292SN/A 10022292SN/A ++iewDispSquashedInsts; 10032292SN/A 10042292SN/A insts_to_dispatch.pop(); 10052292SN/A 10062292SN/A //Tell Rename That An Instruction has been processed 10072292SN/A if (inst->isLoad() || inst->isStore()) { 10082292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10092292SN/A } 10102292SN/A toRename->iewInfo[tid].dispatched++; 10112292SN/A 10122292SN/A continue; 10132292SN/A } 10142292SN/A 10152292SN/A // Check for full conditions. 10162292SN/A if (instQueue.isFull(tid)) { 10172292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10182292SN/A 10192292SN/A // Call function to start blocking. 10202292SN/A block(tid); 10212292SN/A 10222292SN/A // Set unblock to false. Special case where we are using 10232292SN/A // skidbuffer (unblocking) instructions but then we still 10242292SN/A // get full in the IQ. 10252292SN/A toRename->iewUnblock[tid] = false; 10262292SN/A 10272292SN/A ++iewIQFullEvents; 10282292SN/A break; 10292292SN/A } else if (ldstQueue.isFull(tid)) { 10302292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10312292SN/A 10322292SN/A // Call function to start blocking. 10332292SN/A block(tid); 10342292SN/A 10352292SN/A // Set unblock to false. Special case where we are using 10362292SN/A // skidbuffer (unblocking) instructions but then we still 10372292SN/A // get full in the IQ. 10382292SN/A toRename->iewUnblock[tid] = false; 10392292SN/A 10402292SN/A ++iewLSQFullEvents; 10412292SN/A break; 10422292SN/A } 10432292SN/A 10442292SN/A // Otherwise issue the instruction just fine. 10452292SN/A if (inst->isLoad()) { 10462292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10472292SN/A "encountered, adding to LSQ.\n", tid); 10482292SN/A 10492292SN/A // Reserve a spot in the load store queue for this 10502292SN/A // memory access. 10512292SN/A ldstQueue.insertLoad(inst); 10522292SN/A 10532292SN/A ++iewDispLoadInsts; 10542292SN/A 10552292SN/A add_to_iq = true; 10562292SN/A 10572292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10582292SN/A } else if (inst->isStore()) { 10592292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10602292SN/A "encountered, adding to LSQ.\n", tid); 10612292SN/A 10622292SN/A ldstQueue.insertStore(inst); 10632292SN/A 10642292SN/A ++iewDispStoreInsts; 10652292SN/A 10662336SN/A if (inst->isStoreConditional()) { 10672336SN/A // Store conditionals need to be set as "canCommit()" 10682336SN/A // so that commit can process them when they reach the 10692336SN/A // head of commit. 10702348SN/A // @todo: This is somewhat specific to Alpha. 10712292SN/A inst->setCanCommit(); 10722292SN/A instQueue.insertNonSpec(inst); 10732292SN/A add_to_iq = false; 10742292SN/A 10752292SN/A ++iewDispNonSpecInsts; 10762292SN/A } else { 10772292SN/A add_to_iq = true; 10782292SN/A } 10792292SN/A 10802292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10812292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10822326SN/A // Same as non-speculative stores. 10832292SN/A inst->setCanCommit(); 10842292SN/A instQueue.insertBarrier(inst); 10852292SN/A add_to_iq = false; 10862292SN/A } else if (inst->isNop()) { 10872292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10882292SN/A "skipping.\n", tid); 10892292SN/A 10902292SN/A inst->setIssued(); 10912292SN/A inst->setExecuted(); 10922292SN/A inst->setCanCommit(); 10932292SN/A 10942326SN/A instQueue.recordProducer(inst); 10952292SN/A 10962727Sktlim@umich.edu iewExecutedNop[tid]++; 10972301SN/A 10982292SN/A add_to_iq = false; 10992292SN/A } else if (inst->isExecuted()) { 11002292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11012292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11022292SN/A "skipping.\n"); 11032292SN/A 11042292SN/A inst->setIssued(); 11052292SN/A inst->setCanCommit(); 11062292SN/A 11072326SN/A instQueue.recordProducer(inst); 11082292SN/A 11092292SN/A add_to_iq = false; 11102292SN/A } else { 11112292SN/A add_to_iq = true; 11122292SN/A } 11134033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11144033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11154033Sktlim@umich.edu "encountered, skipping.\n", tid); 11164033Sktlim@umich.edu 11174033Sktlim@umich.edu // Same as non-speculative stores. 11184033Sktlim@umich.edu inst->setCanCommit(); 11194033Sktlim@umich.edu 11204033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11214033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11224033Sktlim@umich.edu 11234033Sktlim@umich.edu ++iewDispNonSpecInsts; 11244033Sktlim@umich.edu 11254033Sktlim@umich.edu add_to_iq = false; 11264033Sktlim@umich.edu } 11272292SN/A 11282292SN/A // If the instruction queue is not full, then add the 11292292SN/A // instruction. 11302292SN/A if (add_to_iq) { 11312292SN/A instQueue.insert(inst); 11322292SN/A } 11332292SN/A 11342292SN/A insts_to_dispatch.pop(); 11352292SN/A 11362292SN/A toRename->iewInfo[tid].dispatched++; 11372292SN/A 11382292SN/A ++iewDispatchedInsts; 11392292SN/A } 11402292SN/A 11412292SN/A if (!insts_to_dispatch.empty()) { 11422935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11432292SN/A block(tid); 11442292SN/A toRename->iewUnblock[tid] = false; 11452292SN/A } 11462292SN/A 11472292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11482292SN/A dispatchStatus[tid] = Running; 11492292SN/A 11502292SN/A updatedQueues = true; 11512292SN/A } 11522292SN/A 11532292SN/A dis_num_inst = 0; 11542292SN/A} 11552292SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Avoid 11582292SN/ADefaultIEW<Impl>::printAvailableInsts() 11592292SN/A{ 11602292SN/A int inst = 0; 11612292SN/A 11622980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11632292SN/A 11642292SN/A while (fromIssue->insts[inst]) { 11652292SN/A 11662980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11672292SN/A 11687720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11692292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11702292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11712292SN/A 11722292SN/A inst++; 11732292SN/A 11742292SN/A } 11752292SN/A 11762980Sgblack@eecs.umich.edu std::cout << "\n"; 11772292SN/A} 11782292SN/A 11792292SN/Atemplate <class Impl> 11802292SN/Avoid 11812292SN/ADefaultIEW<Impl>::executeInsts() 11822292SN/A{ 11832292SN/A wbNumInst = 0; 11842292SN/A wbCycle = 0; 11852292SN/A 11866221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11876221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11882292SN/A 11893867Sbinkertn@umich.edu while (threads != end) { 11906221Snate@binkert.org ThreadID tid = *threads++; 11912292SN/A fetchRedirect[tid] = false; 11922292SN/A } 11932292SN/A 11942698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11957599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 11962698Sktlim@umich.edu// printAvailableInsts(); 11971062SN/A 11981062SN/A // Execute/writeback any instructions that are available. 11992333SN/A int insts_to_execute = fromIssue->size; 12002292SN/A int inst_num = 0; 12012333SN/A for (; inst_num < insts_to_execute; 12022326SN/A ++inst_num) { 12031062SN/A 12042292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12051062SN/A 12062333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12071062SN/A 12087720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12097720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12101062SN/A 12111062SN/A // Check if the instruction is squashed; if so then skip it 12121062SN/A if (inst->isSquashed()) { 12132292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12141062SN/A 12151062SN/A // Consider this instruction executed so that commit can go 12161062SN/A // ahead and retire the instruction. 12171062SN/A inst->setExecuted(); 12181062SN/A 12192292SN/A // Not sure if I should set this here or just let commit try to 12202292SN/A // commit any squashed instructions. I like the latter a bit more. 12212292SN/A inst->setCanCommit(); 12221062SN/A 12231062SN/A ++iewExecSquashedInsts; 12241062SN/A 12252820Sktlim@umich.edu decrWb(inst->seqNum); 12261062SN/A continue; 12271062SN/A } 12281062SN/A 12292292SN/A Fault fault = NoFault; 12301062SN/A 12311062SN/A // Execute instruction. 12321062SN/A // Note that if the instruction faults, it will be handled 12331062SN/A // at the commit stage. 12347850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12352292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12361062SN/A "reference.\n"); 12371062SN/A 12381062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12391062SN/A if (inst->isLoad()) { 12402292SN/A // Loads will mark themselves as executed, and their writeback 12412292SN/A // event adds the instruction to the queue to commit 12422292SN/A fault = ldstQueue.executeLoad(inst); 12437944SGiacomo.Gabrielli@arm.com 12447944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12457944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12467944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12477944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12487944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12497944SGiacomo.Gabrielli@arm.com "load.\n"); 12507944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12517944SGiacomo.Gabrielli@arm.com continue; 12527944SGiacomo.Gabrielli@arm.com } 12537944SGiacomo.Gabrielli@arm.com 12547850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12558073SAli.Saidi@ARM.com inst->fault = NoFault; 12567850SMatt.Horsnell@arm.com } 12571062SN/A } else if (inst->isStore()) { 12582367SN/A fault = ldstQueue.executeStore(inst); 12591062SN/A 12607944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12617944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12627944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12637944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12647944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12657944SGiacomo.Gabrielli@arm.com "store.\n"); 12667944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12677944SGiacomo.Gabrielli@arm.com continue; 12687944SGiacomo.Gabrielli@arm.com } 12697944SGiacomo.Gabrielli@arm.com 12702292SN/A // If the store had a fault then it may not have a mem req 12717782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12727782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12737782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12747782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12752367SN/A // Send this instruction to commit, also make sure iew stage 12762367SN/A // realizes there is activity. 12772367SN/A inst->setExecuted(); 12782367SN/A instToCommit(inst); 12792367SN/A activityThisCycle(); 12802292SN/A } 12812326SN/A 12822326SN/A // Store conditionals will mark themselves as 12832326SN/A // executed, and their writeback event will add the 12842326SN/A // instruction to the queue to commit. 12851062SN/A } else { 12862292SN/A panic("Unexpected memory type!\n"); 12871062SN/A } 12881062SN/A 12891062SN/A } else { 12907847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 12917847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 12927847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 12937847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 12947847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 12957847Sminkyu.jeong@arm.com inst->execute(); 12967848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 12977848SAli.Saidi@ARM.com inst->forwardOldRegs(); 12987847Sminkyu.jeong@arm.com } 12991062SN/A 13002292SN/A inst->setExecuted(); 13012292SN/A 13022292SN/A instToCommit(inst); 13031062SN/A } 13041062SN/A 13052301SN/A updateExeInstStats(inst); 13061681SN/A 13072326SN/A // Check if branch prediction was correct, if not then we need 13082326SN/A // to tell commit to squash in flight instructions. Only 13092326SN/A // handle this if there hasn't already been something that 13102107SN/A // redirects fetch in this group of instructions. 13111681SN/A 13122292SN/A // This probably needs to prioritize the redirects if a different 13132292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13142292SN/A // instruction first, so the branch resolution order will be correct. 13156221Snate@binkert.org ThreadID tid = inst->threadNumber; 13161062SN/A 13173732Sktlim@umich.edu if (!fetchRedirect[tid] || 13187852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13193732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13201062SN/A 13217856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13227856SMatt.Horsnell@arm.com // that have not been executed. 13237856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13247856SMatt.Horsnell@arm.com 13257856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13262292SN/A fetchRedirect[tid] = true; 13271062SN/A 13282292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13296036Sksewell@umich.edu DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13307720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 13317720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13327720Sgblack@eecs.umich.edu inst->pcState(), inst->nextInstAddr()); 13331062SN/A // If incorrect, then signal the ROB that it must be squashed. 13342292SN/A squashDueToBranch(inst, tid); 13351062SN/A 13363795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13371062SN/A predictedTakenIncorrect++; 13382292SN/A } else { 13392292SN/A predictedNotTakenIncorrect++; 13401062SN/A } 13412292SN/A } else if (ldstQueue.violation(tid)) { 13424033Sktlim@umich.edu assert(inst->isMemRef()); 13432326SN/A // If there was an ordering violation, then get the 13442326SN/A // DynInst that caused the violation. Note that this 13452292SN/A // clears the violation signal. 13462292SN/A DynInstPtr violator; 13472292SN/A violator = ldstQueue.getMemDepViolator(tid); 13481062SN/A 13497720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13507720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13517720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13527720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13537720Sgblack@eecs.umich.edu 13543732Sktlim@umich.edu fetchRedirect[tid] = true; 13553732Sktlim@umich.edu 13561062SN/A // Tell the instruction queue that a violation has occured. 13571062SN/A instQueue.violation(inst, violator); 13581062SN/A 13591062SN/A // Squash. 13602292SN/A squashDueToMemOrder(inst,tid); 13611062SN/A 13621062SN/A ++memOrderViolationEvents; 13632292SN/A } else if (ldstQueue.loadBlocked(tid) && 13642292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13652292SN/A fetchRedirect[tid] = true; 13662292SN/A 13672292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13687720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13697720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13702292SN/A 13712292SN/A squashDueToMemBlocked(inst, tid); 13721062SN/A } 13734033Sktlim@umich.edu } else { 13744033Sktlim@umich.edu // Reset any state associated with redirects that will not 13754033Sktlim@umich.edu // be used. 13764033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13774033Sktlim@umich.edu assert(inst->isMemRef()); 13784033Sktlim@umich.edu 13794033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13804033Sktlim@umich.edu 13814033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13827720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13837720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 13847720Sgblack@eecs.umich.edu inst->physEffAddr); 13854033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13864033Sktlim@umich.edu "already squashing\n"); 13874033Sktlim@umich.edu 13884033Sktlim@umich.edu ++memOrderViolationEvents; 13894033Sktlim@umich.edu } 13904033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 13914033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13924033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13937720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13947720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13954033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 13964033Sktlim@umich.edu "already squashing\n"); 13974033Sktlim@umich.edu 13984033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 13994033Sktlim@umich.edu } 14004033Sktlim@umich.edu 14011062SN/A } 14021062SN/A } 14032292SN/A 14042348SN/A // Update and record activity if we processed any instructions. 14052292SN/A if (inst_num) { 14062292SN/A if (exeStatus == Idle) { 14072292SN/A exeStatus = Running; 14082292SN/A } 14092292SN/A 14102292SN/A updatedQueues = true; 14112292SN/A 14122292SN/A cpu->activityThisCycle(); 14132292SN/A } 14142292SN/A 14152292SN/A // Need to reset this in case a writeback event needs to write into the 14162292SN/A // iew queue. That way the writeback event will write into the correct 14172292SN/A // spot in the queue. 14182292SN/A wbNumInst = 0; 14197852SMatt.Horsnell@arm.com 14202107SN/A} 14212107SN/A 14222292SN/Atemplate <class Impl> 14232107SN/Avoid 14242292SN/ADefaultIEW<Impl>::writebackInsts() 14252107SN/A{ 14262326SN/A // Loop through the head of the time buffer and wake any 14272326SN/A // dependents. These instructions are about to write back. Also 14282326SN/A // mark scoreboard that this instruction is finally complete. 14292326SN/A // Either have IEW have direct access to scoreboard, or have this 14302326SN/A // as part of backwards communication. 14313958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14322292SN/A toCommit->insts[inst_num]; inst_num++) { 14332107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14346221Snate@binkert.org ThreadID tid = inst->threadNumber; 14352107SN/A 14367720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14377720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14382107SN/A 14392301SN/A iewInstsToCommit[tid]++; 14402301SN/A 14412292SN/A // Some instructions will be sent to commit without having 14422292SN/A // executed because they need commit to handle them. 14432292SN/A // E.g. Uncached loads have not actually executed when they 14442292SN/A // are first sent to commit. Instead commit must tell the LSQ 14452292SN/A // when it's ready to execute the uncached load. 14462367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14472301SN/A int dependents = instQueue.wakeDependents(inst); 14482107SN/A 14492292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14502292SN/A //mark as Ready 14512292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14522292SN/A inst->renamedDestRegIdx(i)); 14532292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14542107SN/A } 14552301SN/A 14562348SN/A if (dependents) { 14572348SN/A producerInst[tid]++; 14582348SN/A consumerInst[tid]+= dependents; 14592348SN/A } 14602326SN/A writebackCount[tid]++; 14612107SN/A } 14622820Sktlim@umich.edu 14632820Sktlim@umich.edu decrWb(inst->seqNum); 14642107SN/A } 14651060SN/A} 14661060SN/A 14671681SN/Atemplate<class Impl> 14681060SN/Avoid 14692292SN/ADefaultIEW<Impl>::tick() 14701060SN/A{ 14712292SN/A wbNumInst = 0; 14722292SN/A wbCycle = 0; 14731060SN/A 14742292SN/A wroteToTimeBuffer = false; 14752292SN/A updatedQueues = false; 14761060SN/A 14772292SN/A sortInsts(); 14781060SN/A 14792326SN/A // Free function units marked as being freed this cycle. 14802326SN/A fuPool->processFreeUnits(); 14811062SN/A 14826221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14836221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14841060SN/A 14852326SN/A // Check stall and squash signals, dispatch any instructions. 14863867Sbinkertn@umich.edu while (threads != end) { 14876221Snate@binkert.org ThreadID tid = *threads++; 14881060SN/A 14892292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14901060SN/A 14912292SN/A checkSignalsAndUpdate(tid); 14922292SN/A dispatch(tid); 14931060SN/A } 14941060SN/A 14952292SN/A if (exeStatus != Squashing) { 14962292SN/A executeInsts(); 14971060SN/A 14982292SN/A writebackInsts(); 14992292SN/A 15002292SN/A // Have the instruction queue try to schedule any ready instructions. 15012292SN/A // (In actuality, this scheduling is for instructions that will 15022292SN/A // be executed next cycle.) 15032292SN/A instQueue.scheduleReadyInsts(); 15042292SN/A 15052292SN/A // Also should advance its own time buffers if the stage ran. 15062292SN/A // Not the best place for it, but this works (hopefully). 15072292SN/A issueToExecQueue.advance(); 15082292SN/A } 15092292SN/A 15102292SN/A bool broadcast_free_entries = false; 15112292SN/A 15122292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15132292SN/A exeStatus = Idle; 15142292SN/A updateLSQNextCycle = false; 15152292SN/A 15162292SN/A broadcast_free_entries = true; 15172292SN/A } 15182292SN/A 15192292SN/A // Writeback any stores using any leftover bandwidth. 15201681SN/A ldstQueue.writebackStores(); 15211681SN/A 15221061SN/A // Check the committed load/store signals to see if there's a load 15231061SN/A // or store to commit. Also check if it's being told to execute a 15241061SN/A // nonspeculative instruction. 15251681SN/A // This is pretty inefficient... 15262292SN/A 15273867Sbinkertn@umich.edu threads = activeThreads->begin(); 15283867Sbinkertn@umich.edu while (threads != end) { 15296221Snate@binkert.org ThreadID tid = (*threads++); 15302292SN/A 15312292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15322292SN/A 15332348SN/A // Update structures based on instructions committed. 15342292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15352292SN/A !fromCommit->commitInfo[tid].squash && 15362292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15372292SN/A 15382292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15392292SN/A 15402292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15412292SN/A 15422292SN/A updateLSQNextCycle = true; 15432292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15442292SN/A } 15452292SN/A 15462292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15472292SN/A 15482292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15492292SN/A if (fromCommit->commitInfo[tid].uncached) { 15502292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15514033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15522292SN/A } else { 15532292SN/A instQueue.scheduleNonSpec( 15542292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15552292SN/A } 15562292SN/A } 15572292SN/A 15582292SN/A if (broadcast_free_entries) { 15592292SN/A toFetch->iewInfo[tid].iqCount = 15602292SN/A instQueue.getCount(tid); 15612292SN/A toFetch->iewInfo[tid].ldstqCount = 15622292SN/A ldstQueue.getCount(tid); 15632292SN/A 15642292SN/A toRename->iewInfo[tid].usedIQ = true; 15652292SN/A toRename->iewInfo[tid].freeIQEntries = 15662292SN/A instQueue.numFreeEntries(); 15672292SN/A toRename->iewInfo[tid].usedLSQ = true; 15682292SN/A toRename->iewInfo[tid].freeLSQEntries = 15692292SN/A ldstQueue.numFreeEntries(tid); 15702292SN/A 15712292SN/A wroteToTimeBuffer = true; 15722292SN/A } 15732292SN/A 15742292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15752292SN/A tid, toRename->iewInfo[tid].dispatched); 15761061SN/A } 15771061SN/A 15782292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15792292SN/A "LSQ has %i free entries.\n", 15802292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15812292SN/A ldstQueue.numFreeEntries()); 15822292SN/A 15832292SN/A updateStatus(); 15842292SN/A 15852292SN/A if (wroteToTimeBuffer) { 15862292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15872292SN/A cpu->activityThisCycle(); 15881061SN/A } 15891060SN/A} 15901060SN/A 15912301SN/Atemplate <class Impl> 15921060SN/Avoid 15932301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15941060SN/A{ 15956221Snate@binkert.org ThreadID tid = inst->threadNumber; 15961060SN/A 15972301SN/A // 15982301SN/A // Pick off the software prefetches 15992301SN/A // 16002301SN/A#ifdef TARGET_ALPHA 16012301SN/A if (inst->isDataPrefetch()) 16026221Snate@binkert.org iewExecutedSwp[tid]++; 16032301SN/A else 16042727Sktlim@umich.edu iewIewExecutedcutedInsts++; 16052301SN/A#else 16062669Sktlim@umich.edu iewExecutedInsts++; 16072301SN/A#endif 16081060SN/A 16092301SN/A // 16102301SN/A // Control operations 16112301SN/A // 16122301SN/A if (inst->isControl()) 16136221Snate@binkert.org iewExecutedBranches[tid]++; 16141060SN/A 16152301SN/A // 16162301SN/A // Memory operations 16172301SN/A // 16182301SN/A if (inst->isMemRef()) { 16196221Snate@binkert.org iewExecutedRefs[tid]++; 16201060SN/A 16212301SN/A if (inst->isLoad()) { 16226221Snate@binkert.org iewExecLoadInsts[tid]++; 16231060SN/A } 16241060SN/A } 16251060SN/A} 16267598Sminkyu.jeong@arm.com 16277598Sminkyu.jeong@arm.comtemplate <class Impl> 16287598Sminkyu.jeong@arm.comvoid 16297598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16307598Sminkyu.jeong@arm.com{ 16317598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16327598Sminkyu.jeong@arm.com 16337598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16347852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16357598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16367598Sminkyu.jeong@arm.com 16377598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16387598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16397598Sminkyu.jeong@arm.com 16407598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16417598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16427720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16437598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16447720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16457720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16467598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16477598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16487598Sminkyu.jeong@arm.com 16497598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16507598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16517598Sminkyu.jeong@arm.com } else { 16527598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16537598Sminkyu.jeong@arm.com } 16547598Sminkyu.jeong@arm.com } 16557598Sminkyu.jeong@arm.com } 16567598Sminkyu.jeong@arm.com} 1657