iew_impl.hh revision 8229
11689SN/A/* 22326SN/A * Copyright (c) 2010 ARM Limited 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * The license below extends only to copyright in the software and shall 61689SN/A * not be construed as granting a license to any other intellectual 71689SN/A * property including but not limited to intellectual property relating 81689SN/A * to a hardware implementation of the functionality of the software 91689SN/A * licensed hereunder. You may use the software subject to the license 101689SN/A * terms below provided that you ensure that this notice is replicated 111689SN/A * unmodified and in its entirety in all distributions of the software, 121689SN/A * modified or unmodified, in source code or in binary form. 131689SN/A * 141689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386658Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392292SN/A * 401717SN/A * Authors: Kevin Lim 415529Snate@binkert.org */ 421060SN/A 436221Snate@binkert.org// @todo: Fix the instantaneous communication among all the stages within 446221Snate@binkert.org// iew. There's a clear delay between issue and execute, yet backwards 451681SN/A// communication happens simultaneously. 465529Snate@binkert.org 472873Sktlim@umich.edu#include <queue> 484329Sktlim@umich.edu 494329Sktlim@umich.edu#include "config/the_isa.hh" 504329Sktlim@umich.edu#include "cpu/o3/fu_pool.hh" 512292SN/A#include "cpu/o3/iew.hh" 522292SN/A#include "cpu/timebuf.hh" 532292SN/A#include "params/DerivO3CPU.hh" 542292SN/A 552820Sktlim@umich.eduusing namespace std; 562292SN/A 572820Sktlim@umich.edutemplate<class Impl> 582820Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 595529Snate@binkert.org : issueToExecQueue(params->backComSize, params->forwardComSize), 602307SN/A cpu(_cpu), 611060SN/A instQueue(_cpu, this, params), 622292SN/A ldstQueue(_cpu, this, params), 632292SN/A fuPool(params->fuPool), 642292SN/A commitToIEWDelay(params->commitToIEWDelay), 651060SN/A renameToIEWDelay(params->renameToIEWDelay), 661060SN/A issueToExecuteDelay(params->issueToExecuteDelay), 671060SN/A dispatchWidth(params->dispatchWidth), 681060SN/A issueWidth(params->issueWidth), 691060SN/A wbOutstanding(0), 701060SN/A wbWidth(params->wbWidth), 711681SN/A numThreads(params->numThreads), 726221Snate@binkert.org switchedOut(false) 736221Snate@binkert.org{ 746221Snate@binkert.org _status = Active; 756221Snate@binkert.org exeStatus = Running; 762292SN/A wbStatus = Idle; 772292SN/A 782820Sktlim@umich.edu // Setup wire to read instructions coming from issue. 792820Sktlim@umich.edu fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 802292SN/A 812292SN/A // Instruction queue needs the queue between issue and execute. 822820Sktlim@umich.edu instQueue.setIssueToExecuteQueue(&issueToExecQueue); 832820Sktlim@umich.edu 842292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 852292SN/A dispatchStatus[tid] = Running; 862292SN/A stalls[tid].commit = false; 872292SN/A fetchRedirect[tid] = false; 882292SN/A } 892292SN/A 902292SN/A wbMax = wbWidth * params->wbDepth; 912292SN/A 921060SN/A updateLSQNextCycle = false; 931060SN/A 941681SN/A ableToIssue = true; 951062SN/A 962292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 971062SN/A} 982301SN/A 992301SN/Atemplate <class Impl> 1001062SN/Astd::string 1012727Sktlim@umich.eduDefaultIEW<Impl>::name() const 1021062SN/A{ 1031062SN/A return cpu->name() + ".iew"; 1041062SN/A} 1051062SN/A 1061062SN/Atemplate <class Impl> 1071062SN/Avoid 1081062SN/ADefaultIEW<Impl>::regStats() 1091062SN/A{ 1101062SN/A using namespace Stats; 1111062SN/A 1121062SN/A instQueue.regStats(); 1131062SN/A ldstQueue.regStats(); 1141062SN/A 1151062SN/A iewIdleCycles 1161062SN/A .name(name() + ".iewIdleCycles") 1171062SN/A .desc("Number of cycles IEW is idle"); 1181062SN/A 1191062SN/A iewSquashCycles 1201062SN/A .name(name() + ".iewSquashCycles") 1211062SN/A .desc("Number of cycles IEW is squashing"); 1221062SN/A 1231062SN/A iewBlockCycles 1241062SN/A .name(name() + ".iewBlockCycles") 1251062SN/A .desc("Number of cycles IEW is blocking"); 1261062SN/A 1271062SN/A iewUnblockCycles 1281062SN/A .name(name() + ".iewUnblockCycles") 1291062SN/A .desc("Number of cycles IEW is unblocking"); 1301062SN/A 1311062SN/A iewDispatchedInsts 1321062SN/A .name(name() + ".iewDispatchedInsts") 1331062SN/A .desc("Number of instructions dispatched to IQ"); 1341062SN/A 1351062SN/A iewDispSquashedInsts 1361062SN/A .name(name() + ".iewDispSquashedInsts") 1371062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1381062SN/A 1391062SN/A iewDispLoadInsts 1401062SN/A .name(name() + ".iewDispLoadInsts") 1411062SN/A .desc("Number of dispatched load instructions"); 1421062SN/A 1432292SN/A iewDispStoreInsts 1442292SN/A .name(name() + ".iewDispStoreInsts") 1452292SN/A .desc("Number of dispatched store instructions"); 1462292SN/A 1471062SN/A iewDispNonSpecInsts 1481062SN/A .name(name() + ".iewDispNonSpecInsts") 1491062SN/A .desc("Number of dispatched non-speculative instructions"); 1501062SN/A 1511062SN/A iewIQFullEvents 1521062SN/A .name(name() + ".iewIQFullEvents") 1531062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1542292SN/A 1552292SN/A iewLSQFullEvents 1562292SN/A .name(name() + ".iewLSQFullEvents") 1572292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1582292SN/A 1592292SN/A memOrderViolationEvents 1602292SN/A .name(name() + ".memOrderViolationEvents") 1612292SN/A .desc("Number of memory order violations"); 1622292SN/A 1632292SN/A predictedTakenIncorrect 1642301SN/A .name(name() + ".predictedTakenIncorrect") 1652727Sktlim@umich.edu .desc("Number of branches that were predicted taken incorrectly"); 1662353SN/A 1672727Sktlim@umich.edu predictedNotTakenIncorrect 1682727Sktlim@umich.edu .name(name() + ".predictedNotTakenIncorrect") 1692727Sktlim@umich.edu .desc("Number of branches that were predicted not taken incorrectly"); 1706221Snate@binkert.org 1712353SN/A branchMispredicts 1722727Sktlim@umich.edu .name(name() + ".branchMispredicts") 1732727Sktlim@umich.edu .desc("Number of branch mispredicts detected at execute"); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1762353SN/A 1772727Sktlim@umich.edu iewExecutedInsts 1782727Sktlim@umich.edu .name(name() + ".iewExecutedInsts") 1792727Sktlim@umich.edu .desc("Number of executed instructions"); 1806221Snate@binkert.org 1812301SN/A iewExecLoadInsts 1822301SN/A .init(cpu->numThreads) 1832727Sktlim@umich.edu .name(name() + ".iewExecLoadInsts") 1842301SN/A .desc("Number of load instructions executed") 1852727Sktlim@umich.edu .flags(total); 1866221Snate@binkert.org 1872301SN/A iewExecSquashedInsts 1882301SN/A .name(name() + ".iewExecSquashedInsts") 1892727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1902301SN/A 1912727Sktlim@umich.edu iewExecutedSwp 1926221Snate@binkert.org .init(cpu->numThreads) 1932301SN/A .name(name() + ".EXEC:swp") 1942301SN/A .desc("number of swp insts executed") 1952727Sktlim@umich.edu .flags(total); 1962301SN/A 1972727Sktlim@umich.edu iewExecutedNop 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".EXEC:nop") 2002301SN/A .desc("number of nop insts executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032301SN/A iewExecutedRefs 2042301SN/A .init(cpu->numThreads) 2052301SN/A .name(name() + ".EXEC:refs") 2062727Sktlim@umich.edu .desc("number of memory reference insts executed") 2072727Sktlim@umich.edu .flags(total); 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu iewExecutedBranches 2102727Sktlim@umich.edu .init(cpu->numThreads) 2112727Sktlim@umich.edu .name(name() + ".EXEC:branches") 2122727Sktlim@umich.edu .desc("Number of branches executed") 2132727Sktlim@umich.edu .flags(total); 2142727Sktlim@umich.edu 2152301SN/A iewExecStoreInsts 2162301SN/A .name(name() + ".EXEC:stores") 2176221Snate@binkert.org .desc("Number of stores executed") 2182301SN/A .flags(total); 2192301SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2202727Sktlim@umich.edu 2212301SN/A iewExecRate 2222326SN/A .name(name() + ".EXEC:rate") 2236221Snate@binkert.org .desc("Inst execution rate") 2242301SN/A .flags(total); 2252301SN/A 2262727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2272301SN/A 2282326SN/A iewInstsToCommit 2296221Snate@binkert.org .init(cpu->numThreads) 2302301SN/A .name(name() + ".WB:sent") 2312301SN/A .desc("cumulative count of insts sent to commit") 2322727Sktlim@umich.edu .flags(total); 2332301SN/A 2342326SN/A writebackCount 2356221Snate@binkert.org .init(cpu->numThreads) 2362301SN/A .name(name() + ".WB:count") 2372301SN/A .desc("cumulative count of insts written-back") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A producerInst 2416221Snate@binkert.org .init(cpu->numThreads) 2422301SN/A .name(name() + ".WB:producers") 2432301SN/A .desc("num instructions producing a value") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A consumerInst 2472301SN/A .init(cpu->numThreads) 2482301SN/A .name(name() + ".WB:consumers") 2492727Sktlim@umich.edu .desc("num instructions consuming a value") 2502301SN/A .flags(total); 2512326SN/A 2522301SN/A wbPenalized 2532326SN/A .init(cpu->numThreads) 2542301SN/A .name(name() + ".WB:penalized") 2552301SN/A .desc("number of instrctions required to write to 'other' IQ") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbPenalizedRate 2592301SN/A .name(name() + ".WB:penalized_rate") 2602326SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2612301SN/A .flags(total); 2622301SN/A 2632727Sktlim@umich.edu wbPenalizedRate = wbPenalized / writebackCount; 2642326SN/A 2651062SN/A wbFanout 2661062SN/A .name(name() + ".WB:fanout") 2671681SN/A .desc("average fanout of values written-back") 2681060SN/A .flags(total); 2692292SN/A 2701060SN/A wbFanout = producerInst / consumerInst; 2716221Snate@binkert.org 2722292SN/A wbRate 2732292SN/A .name(name() + ".WB:rate") 2742292SN/A .desc("insts written-back per cycle") 2752292SN/A .flags(total); 2762292SN/A wbRate = writebackCount / cpu->numCycles; 2772292SN/A} 2782292SN/A 2792292SN/Atemplate<class Impl> 2802292SN/Avoid 2812733Sktlim@umich.eduDefaultIEW<Impl>::initStage() 2821060SN/A{ 2831060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2841681SN/A toRename->iewInfo[tid].usedIQ = true; 2851060SN/A toRename->iewInfo[tid].freeIQEntries = 2862292SN/A instQueue.numFreeEntries(tid); 2871060SN/A 2881060SN/A toRename->iewInfo[tid].usedLSQ = true; 2891060SN/A toRename->iewInfo[tid].freeLSQEntries = 2901060SN/A ldstQueue.numFreeEntries(tid); 2911060SN/A } 2921060SN/A 2931060SN/A cpu->activateStage(O3CPU::IEWIdx); 2941060SN/A} 2951060SN/A 2962292SN/Atemplate<class Impl> 2972292SN/Avoid 2981060SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2991060SN/A{ 3001060SN/A timeBuffer = tb_ptr; 3011060SN/A 3021681SN/A // Setup wire to read information from time buffer, from commit. 3031060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3042292SN/A 3051060SN/A // Setup wire to write information back to previous stages. 3061060SN/A toRename = timeBuffer->getWire(0); 3071060SN/A 3081060SN/A toFetch = timeBuffer->getWire(0); 3091060SN/A 3101060SN/A // Instruction queue also needs main time buffer. 3111060SN/A instQueue.setTimeBuffer(tb_ptr); 3121681SN/A} 3131060SN/A 3142292SN/Atemplate<class Impl> 3151060SN/Avoid 3161060SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3171060SN/A{ 3181060SN/A renameQueue = rq_ptr; 3191060SN/A 3201060SN/A // Setup wire to read information from rename queue. 3211060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3221681SN/A} 3231060SN/A 3246221Snate@binkert.orgtemplate<class Impl> 3251060SN/Avoid 3262292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3272292SN/A{ 3282292SN/A iewQueue = iq_ptr; 3292292SN/A 3301060SN/A // Setup wire to write instructions to commit. 3311060SN/A toCommit = iewQueue->getWire(0); 3321681SN/A} 3331060SN/A 3342292SN/Atemplate<class Impl> 3351060SN/Avoid 3362292SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3371060SN/A{ 3381060SN/A activeThreads = at_ptr; 3392307SN/A 3402863Sktlim@umich.edu ldstQueue.setActiveThreads(at_ptr); 3412843Sktlim@umich.edu instQueue.setActiveThreads(at_ptr); 3422307SN/A} 3432843Sktlim@umich.edu 3442843Sktlim@umich.edutemplate<class Impl> 3452863Sktlim@umich.eduvoid 3461681SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3471681SN/A{ 3482316SN/A scoreboard = sb_ptr; 3491681SN/A} 3502843Sktlim@umich.edu 3512843Sktlim@umich.edutemplate <class Impl> 3522843Sktlim@umich.edubool 3532843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3542843Sktlim@umich.edu{ 3552843Sktlim@umich.edu // IEW is ready to drain at any time. 3562843Sktlim@umich.edu cpu->signalDrained(); 3571681SN/A return true; 3582348SN/A} 3592307SN/A 3602367SN/Atemplate <class Impl> 3612367SN/Avoid 3621681SN/ADefaultIEW<Impl>::resume() 3632307SN/A{ 3642307SN/A} 3652307SN/A 3662307SN/Atemplate <class Impl> 3676221Snate@binkert.orgvoid 3686221Snate@binkert.orgDefaultIEW<Impl>::switchOut() 3696221Snate@binkert.org{ 3706221Snate@binkert.org // Clear any state. 3716221Snate@binkert.org switchedOut = true; 3722307SN/A assert(insts[0].empty()); 3731681SN/A assert(skidBuffer[0].empty()); 3741681SN/A 3752307SN/A instQueue.switchOut(); 3761681SN/A ldstQueue.switchOut(); 3772307SN/A fuPool->switchOut(); 3781060SN/A 3792348SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3802307SN/A while (!insts[tid].empty()) 3812307SN/A insts[tid].pop(); 3822307SN/A while (!skidBuffer[tid].empty()) 3832307SN/A skidBuffer[tid].pop(); 3841060SN/A } 3852307SN/A} 3862307SN/A 3872307SN/Atemplate <class Impl> 3881060SN/Avoid 3892307SN/ADefaultIEW<Impl>::takeOverFrom() 3902307SN/A{ 3911060SN/A // Reset all state. 3926221Snate@binkert.org _status = Active; 3936221Snate@binkert.org exeStatus = Running; 3946221Snate@binkert.org wbStatus = Idle; 3956221Snate@binkert.org switchedOut = false; 3962307SN/A 3971060SN/A instQueue.takeOverFrom(); 3982307SN/A ldstQueue.takeOverFrom(); 3992307SN/A fuPool->takeOverFrom(); 4002873Sktlim@umich.edu 4012307SN/A initStage(); 4021060SN/A cpu->activityThisCycle(); 4031060SN/A 4041060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4051681SN/A dispatchStatus[tid] = Running; 4061060SN/A stalls[tid].commit = false; 4076221Snate@binkert.org fetchRedirect[tid] = false; 4082107SN/A } 4096221Snate@binkert.org 4102107SN/A updateLSQNextCycle = false; 4112292SN/A 4122292SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4132107SN/A issueToExecQueue.advance(); 4142292SN/A } 4152326SN/A} 4162292SN/A 4172107SN/Atemplate<class Impl> 4182292SN/Avoid 4192935Sksewell@umich.eduDefaultIEW<Impl>::squash(ThreadID tid) 4204632Sgblack@eecs.umich.edu{ 4212935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4222292SN/A 4232292SN/A // Tell the IQ to start squashing. 4242292SN/A instQueue.squash(tid); 4252292SN/A 4262292SN/A // Tell the LDSTQ to start squashing. 4272107SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4282292SN/A updatedQueues = true; 4292107SN/A 4302292SN/A // Clear the skid buffer in case it has any data in it. 4312292SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4322107SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4332702Sktlim@umich.edu 4342107SN/A while (!skidBuffer[tid].empty()) { 4352107SN/A if (skidBuffer[tid].front()->isLoad() || 4362107SN/A skidBuffer[tid].front()->isStore() ) { 4372107SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4386221Snate@binkert.org } 4392292SN/A 4402292SN/A toRename->iewInfo[tid].dispatched++; 4412292SN/A 4422292SN/A skidBuffer[tid].pop(); 4432292SN/A } 4442292SN/A 4452292SN/A emptyRenameInsts(tid); 4462292SN/A} 4472935Sksewell@umich.edu 4484632Sgblack@eecs.umich.edutemplate<class Impl> 4493969Sgblack@eecs.umich.eduvoid 4504632Sgblack@eecs.umich.eduDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4513795Sgblack@eecs.umich.edu{ 4523795Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4533795Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4543093Sksewell@umich.edu 4553093Sksewell@umich.edu if (toCommit->squash[tid] == false || 4563093Sksewell@umich.edu inst->seqNum < toCommit->squashedSeqNum[tid]) { 4574632Sgblack@eecs.umich.edu toCommit->squash[tid] = true; 4583093Sksewell@umich.edu toCommit->squashedSeqNum[tid] = inst->seqNum; 4594632Sgblack@eecs.umich.edu toCommit->branchTaken[tid] = inst->pcState().branching(); 4604636Sgblack@eecs.umich.edu 4612292SN/A TheISA::PCState pc = inst->pcState(); 4622292SN/A TheISA::advancePC(pc, inst->staticInst); 4632292SN/A 4642292SN/A toCommit->pc[tid] = pc; 4652292SN/A toCommit->mispredictInst[tid] = inst; 4662292SN/A toCommit->includeSquashInst[tid] = false; 4672292SN/A 4682292SN/A wroteToTimeBuffer = true; 4696221Snate@binkert.org } 4702292SN/A 4712292SN/A} 4722292SN/A 4732292SN/Atemplate<class Impl> 4742292SN/Avoid 4752292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4762292SN/A{ 4773795Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4783732Sktlim@umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4792292SN/A 4802292SN/A if (toCommit->squash[tid] == false || 4812292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4822292SN/A toCommit->squash[tid] = true; 4832292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4842292SN/A TheISA::PCState pc = inst->pcState(); 4852292SN/A TheISA::advancePC(pc, inst->staticInst); 4862292SN/A toCommit->pc[tid] = pc; 4876221Snate@binkert.org toCommit->mispredictInst[tid] = NULL; 4882292SN/A 4892292SN/A toCommit->includeSquashInst[tid] = false; 4902292SN/A 4912292SN/A wroteToTimeBuffer = true; 4922292SN/A } 4932292SN/A} 4942292SN/A 4953958Sgblack@eecs.umich.edutemplate<class Impl> 4963732Sktlim@umich.eduvoid 4972292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 4982348SN/A{ 4992292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5002292SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5012292SN/A if (toCommit->squash[tid] == false || 5022292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 5032292SN/A toCommit->squash[tid] = true; 5042292SN/A 5052292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5062292SN/A toCommit->pc[tid] = inst->pcState(); 5072292SN/A toCommit->mispredictInst[tid] = NULL; 5086221Snate@binkert.org 5092292SN/A // Must include the broadcasted SN in the squash. 5102292SN/A toCommit->includeSquashInst[tid] = true; 5112292SN/A 5122292SN/A ldstQueue.setLoadBlockedHandled(tid); 5132292SN/A 5142292SN/A wroteToTimeBuffer = true; 5152292SN/A } 5162292SN/A} 5172292SN/A 5182292SN/Atemplate<class Impl> 5192292SN/Avoid 5202292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5212292SN/A{ 5222292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5232292SN/A 5242292SN/A if (dispatchStatus[tid] != Blocked && 5252292SN/A dispatchStatus[tid] != Unblocking) { 5262292SN/A toRename->iewBlock[tid] = true; 5276221Snate@binkert.org wroteToTimeBuffer = true; 5282292SN/A } 5292292SN/A 5302292SN/A // Add the current inputs to the skid buffer so they can be 5312292SN/A // reprocessed when this stage unblocks. 5322292SN/A skidInsert(tid); 5332292SN/A 5342292SN/A dispatchStatus[tid] = Blocked; 5352292SN/A} 5362292SN/A 5372292SN/Atemplate<class Impl> 5382292SN/Avoid 5392292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5402292SN/A{ 5412292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5422292SN/A "buffer %u.\n",tid, tid); 5432292SN/A 5442292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5451060SN/A // Also switch status to running. 5461681SN/A if (skidBuffer[tid].empty()) { 5471060SN/A toRename->iewUnblock[tid] = true; 5481060SN/A wroteToTimeBuffer = true; 5492292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5502292SN/A dispatchStatus[tid] = Running; 5512292SN/A } 5522292SN/A} 5532292SN/A 5542292SN/Atemplate<class Impl> 5551681SN/Avoid 5561681SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5571060SN/A{ 5582292SN/A instQueue.wakeDependents(inst); 5591060SN/A} 5602292SN/A 5612292SN/Atemplate<class Impl> 5621060SN/Avoid 5632292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5642292SN/A{ 5652292SN/A instQueue.rescheduleMemInst(inst); 5662292SN/A} 5673221Sktlim@umich.edu 5683221Sktlim@umich.edutemplate<class Impl> 5693221Sktlim@umich.eduvoid 5703221Sktlim@umich.eduDefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5713221Sktlim@umich.edu{ 5722292SN/A instQueue.replayMemInst(inst); 5732292SN/A} 5742292SN/A 5752292SN/Atemplate<class Impl> 5762326SN/Avoid 5772292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5782292SN/A{ 5792820Sktlim@umich.edu // This function should not be called after writebackInsts in a 5802292SN/A // single cycle. That will cause problems with an instruction 5812292SN/A // being added to the queue to commit without being processed by 5822292SN/A // writebackInsts prior to being sent to commit. 5832292SN/A 5842353SN/A // First check the time slot that this instruction will write 5852292SN/A // to. If there are free write ports at the time, then go ahead 5862292SN/A // and write the instruction to that time. If there are not, 5872353SN/A // keep looking back to see where's the first time there's a 5882353SN/A // free slot. 5892292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5902292SN/A ++wbNumInst; 5912292SN/A if (wbNumInst == wbWidth) { 5922292SN/A ++wbCycle; 5932292SN/A wbNumInst = 0; 5942292SN/A } 5952292SN/A 5962292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5972292SN/A } 5982292SN/A 5992292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6002292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6012731Sktlim@umich.edu // Add finished instruction to queue to commit. 6022292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6032292SN/A (*iewQueue)[wbCycle].size++; 6042292SN/A} 6052292SN/A 6062292SN/Atemplate <class Impl> 6072292SN/Aunsigned 6082292SN/ADefaultIEW<Impl>::validInstsFromRename() 6092292SN/A{ 6106221Snate@binkert.org unsigned inst_count = 0; 6112292SN/A 6122292SN/A for (int i=0; i<fromRename->size; i++) { 6132292SN/A if (!fromRename->insts[i]->isSquashed()) 6142292SN/A inst_count++; 6152292SN/A } 6162292SN/A 6172292SN/A return inst_count; 6182292SN/A} 6192292SN/A 6202292SN/Atemplate<class Impl> 6212292SN/Avoid 6222292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6232292SN/A{ 6242292SN/A DynInstPtr inst = NULL; 6252292SN/A 6262292SN/A while (!insts[tid].empty()) { 6272292SN/A inst = insts[tid].front(); 6282292SN/A 6292292SN/A insts[tid].pop(); 6302292SN/A 6312292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6322292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6332292SN/A inst->pcState(),tid); 6342292SN/A 6352292SN/A skidBuffer[tid].push(inst); 6366221Snate@binkert.org } 6376221Snate@binkert.org 6382292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6393867Sbinkertn@umich.edu "Skidbuffer Exceeded Max Size"); 6406221Snate@binkert.org} 6413867Sbinkertn@umich.edu 6422292SN/Atemplate<class Impl> 6432292SN/Aint 6442292SN/ADefaultIEW<Impl>::skidCount() 6452292SN/A{ 6462292SN/A int max=0; 6472292SN/A 6482292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6492292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6502292SN/A 6512292SN/A while (threads != end) { 6522292SN/A ThreadID tid = *threads++; 6536221Snate@binkert.org unsigned thread_count = skidBuffer[tid].size(); 6546221Snate@binkert.org if (max < thread_count) 6552292SN/A max = thread_count; 6563867Sbinkertn@umich.edu } 6576221Snate@binkert.org 6583867Sbinkertn@umich.edu return max; 6593867Sbinkertn@umich.edu} 6602292SN/A 6612292SN/Atemplate<class Impl> 6622292SN/Abool 6632292SN/ADefaultIEW<Impl>::skidsEmpty() 6641062SN/A{ 6651062SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6661681SN/A list<ThreadID>::iterator end = activeThreads->end(); 6671062SN/A 6682292SN/A while (threads != end) { 6691062SN/A ThreadID tid = *threads++; 6702292SN/A 6711062SN/A if (!skidBuffer[tid].empty()) 6726221Snate@binkert.org return false; 6736221Snate@binkert.org } 6741062SN/A 6753867Sbinkertn@umich.edu return true; 6766221Snate@binkert.org} 6771062SN/A 6782292SN/Atemplate <class Impl> 6792292SN/Avoid 6802292SN/ADefaultIEW<Impl>::updateStatus() 6812292SN/A{ 6822292SN/A bool any_unblocking = false; 6831062SN/A 6842292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6852292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6862292SN/A 6872292SN/A while (threads != end) { 6882292SN/A ThreadID tid = *threads++; 6892292SN/A 6901062SN/A if (dispatchStatus[tid] == Unblocking) { 6912292SN/A any_unblocking = true; 6921062SN/A break; 6932292SN/A } 6942292SN/A } 6952292SN/A 6962292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6972292SN/A // and there's no stores waiting to write back, and dispatch is not 6982292SN/A // unblocking, then there is no internal activity for the IEW stage. 6991062SN/A instQueue.intInstQueueReads++; 7002292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7011062SN/A !ldstQueue.willWB() && !any_unblocking) { 7022292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7031062SN/A 7041062SN/A deactivateStage(); 7051062SN/A 7061681SN/A _status = Inactive; 7071062SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7082292SN/A ldstQueue.willWB() || 7091062SN/A any_unblocking)) { 7102292SN/A // Otherwise there is internal activity. Set to active. 7112292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7122292SN/A 7131062SN/A activateStage(); 7142292SN/A 7152292SN/A _status = Active; 7166221Snate@binkert.org } 7172292SN/A} 7182292SN/A 7192292SN/Atemplate <class Impl> 7202292SN/Avoid 7211062SN/ADefaultIEW<Impl>::resetEntries() 7222292SN/A{ 7232292SN/A instQueue.resetEntries(); 7242292SN/A ldstQueue.resetEntries(); 7252292SN/A} 7262292SN/A 7272292SN/Atemplate <class Impl> 7282292SN/Avoid 7292292SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7306221Snate@binkert.org{ 7312292SN/A if (fromCommit->commitBlock[tid]) { 7322292SN/A stalls[tid].commit = true; 7332292SN/A } 7342292SN/A 7352292SN/A if (fromCommit->commitUnblock[tid]) { 7362292SN/A assert(stalls[tid].commit); 7372292SN/A stalls[tid].commit = false; 7382292SN/A } 7392292SN/A} 7402292SN/A 7412292SN/Atemplate <class Impl> 7422292SN/Abool 7432292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7442292SN/A{ 7452292SN/A bool ret_val(false); 7462292SN/A 7472292SN/A if (stalls[tid].commit) { 7482292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7492292SN/A ret_val = true; 7502292SN/A } else if (instQueue.isFull(tid)) { 7512292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7522292SN/A ret_val = true; 7532292SN/A } else if (ldstQueue.isFull(tid)) { 7542292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7552292SN/A 7562292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7572292SN/A 7582292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7592292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7602292SN/A } 7612292SN/A 7622292SN/A if (ldstQueue.numStores(tid) > 0) { 7632292SN/A 7642292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7652292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7666221Snate@binkert.org } 7672292SN/A 7682292SN/A ret_val = true; 7692292SN/A } else if (ldstQueue.isStalled(tid)) { 7702292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7712292SN/A ret_val = true; 7722292SN/A } 7732292SN/A 7742292SN/A return ret_val; 7752292SN/A} 7762292SN/A 7772292SN/Atemplate <class Impl> 7782292SN/Avoid 7792292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7802292SN/A{ 7812292SN/A // Check if there's a squash signal, squash if there is 7822292SN/A // Check stall signals, block if there is. 7832292SN/A // If status was Blocked 7842292SN/A // if so then go to unblocking 7852292SN/A // If status was Squashing 7862292SN/A // check if squashing is not high. Switch to running this cycle. 7872292SN/A 7882292SN/A readStallSignals(tid); 7892292SN/A 7902292SN/A if (fromCommit->commitInfo[tid].squash) { 7912292SN/A squash(tid); 7922292SN/A 7932702Sktlim@umich.edu if (dispatchStatus[tid] == Blocked || 7942292SN/A dispatchStatus[tid] == Unblocking) { 7952292SN/A toRename->iewUnblock[tid] = true; 7962292SN/A wroteToTimeBuffer = true; 7972702Sktlim@umich.edu } 7982702Sktlim@umich.edu 7992292SN/A dispatchStatus[tid] = Squashing; 8002292SN/A fetchRedirect[tid] = false; 8012292SN/A return; 8022292SN/A } 8032292SN/A 8042292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8052292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8062292SN/A 8072292SN/A dispatchStatus[tid] = Squashing; 8082292SN/A emptyRenameInsts(tid); 8092292SN/A wroteToTimeBuffer = true; 8102292SN/A return; 8112292SN/A } 8122292SN/A 8132292SN/A if (checkStall(tid)) { 8142292SN/A block(tid); 8152292SN/A dispatchStatus[tid] = Blocked; 8162292SN/A return; 8172292SN/A } 8182292SN/A 8192292SN/A if (dispatchStatus[tid] == Blocked) { 8202292SN/A // Status from previous cycle was blocked, but there are no more stall 8212292SN/A // conditions. Switch over to unblocking. 8222292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8232292SN/A tid); 8242292SN/A 8252292SN/A dispatchStatus[tid] = Unblocking; 8262292SN/A 8272292SN/A unblock(tid); 8282292SN/A 8292292SN/A return; 8302292SN/A } 8312292SN/A 8322292SN/A if (dispatchStatus[tid] == Squashing) { 8332292SN/A // Switch status to running if rename isn't being told to block or 8342292SN/A // squash this cycle. 8352292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8362292SN/A tid); 8372292SN/A 8382326SN/A dispatchStatus[tid] = Running; 8396221Snate@binkert.org 8406221Snate@binkert.org return; 8412326SN/A } 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Avoid 8462292SN/ADefaultIEW<Impl>::sortInsts() 8472292SN/A{ 8482292SN/A int insts_from_rename = fromRename->size; 8496221Snate@binkert.org#ifdef DEBUG 8502702Sktlim@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) 8514632Sgblack@eecs.umich.edu assert(insts[tid].empty()); 8522935Sksewell@umich.edu#endif 8532702Sktlim@umich.edu for (int i = 0; i < insts_from_rename; ++i) { 8542935Sksewell@umich.edu insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8552702Sktlim@umich.edu } 8562702Sktlim@umich.edu} 8572702Sktlim@umich.edu 8582702Sktlim@umich.edutemplate <class Impl> 8592702Sktlim@umich.eduvoid 8602702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8612702Sktlim@umich.edu{ 8622702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8632702Sktlim@umich.edu 8642702Sktlim@umich.edu while (!insts[tid].empty()) { 8652702Sktlim@umich.edu 8662702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8672702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8682292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 8692292SN/A } 8702292SN/A 8712292SN/A toRename->iewInfo[tid].dispatched++; 8722292SN/A 8732292SN/A insts[tid].pop(); 8742292SN/A } 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Avoid 8792292SN/ADefaultIEW<Impl>::wakeCPU() 8802292SN/A{ 8812292SN/A cpu->wakeCPU(); 8822292SN/A} 8832292SN/A 8842292SN/Atemplate <class Impl> 8852292SN/Avoid 8862733Sktlim@umich.eduDefaultIEW<Impl>::activityThisCycle() 8872292SN/A{ 8882292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8892292SN/A cpu->activityThisCycle(); 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932292SN/Ainline void 8942733Sktlim@umich.eduDefaultIEW<Impl>::activateStage() 8952292SN/A{ 8962292SN/A DPRINTF(Activity, "Activating stage.\n"); 8972292SN/A cpu->activateStage(O3CPU::IEWIdx); 8982292SN/A} 8996221Snate@binkert.org 9002292SN/Atemplate <class Impl> 9012292SN/Ainline void 9022292SN/ADefaultIEW<Impl>::deactivateStage() 9032292SN/A{ 9042292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9052292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9062292SN/A} 9072292SN/A 9082292SN/Atemplate<class Impl> 9092292SN/Avoid 9102292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9112292SN/A{ 9122292SN/A // If status is Running or idle, 9132292SN/A // call dispatchInsts() 9142292SN/A // If status is Unblocking, 9152292SN/A // buffer any instructions coming from rename 9162292SN/A // continue trying to empty skid buffer 9172292SN/A // check if stall conditions have passed 9182292SN/A 9192292SN/A if (dispatchStatus[tid] == Blocked) { 9202292SN/A ++iewBlockCycles; 9212292SN/A 9222292SN/A } else if (dispatchStatus[tid] == Squashing) { 9232292SN/A ++iewSquashCycles; 9242292SN/A } 9252292SN/A 9262292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9272292SN/A // will allow, as long as it is not currently blocked. 9282292SN/A if (dispatchStatus[tid] == Running || 9292292SN/A dispatchStatus[tid] == Idle) { 9302292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9312292SN/A "dispatch.\n", tid); 9322292SN/A 9332292SN/A dispatchInsts(tid); 9342292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9355215Sgblack@eecs.umich.edu // Make sure that the skid buffer has something in it if the 9362292SN/A // status is unblocking. 9372292SN/A assert(!skidsEmpty()); 9382292SN/A 9392292SN/A // If the status was unblocking, then instructions from the skid 9402292SN/A // buffer were used. Remove those instructions and handle 9412292SN/A // the rest of unblocking. 9422292SN/A dispatchInsts(tid); 9432292SN/A 9442292SN/A ++iewUnblockCycles; 9452292SN/A 9462292SN/A if (validInstsFromRename()) { 9476221Snate@binkert.org // Add the current inputs to the skid buffer so they can be 9482292SN/A // reprocessed when this stage unblocks. 9492292SN/A skidInsert(tid); 9502292SN/A } 9512292SN/A 9522292SN/A unblock(tid); 9532292SN/A } 9542292SN/A} 9552292SN/A 9562292SN/Atemplate <class Impl> 9572292SN/Avoid 9582292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9592292SN/A{ 9602292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9612292SN/A // otherwise. 9622292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9632292SN/A dispatchStatus[tid] == Unblocking ? 9642820Sktlim@umich.edu skidBuffer[tid] : insts[tid]; 9652292SN/A 9662292SN/A int insts_to_add = insts_to_dispatch.size(); 9672292SN/A 9682292SN/A DynInstPtr inst; 9692292SN/A bool add_to_iq = false; 9702292SN/A int dis_num_inst = 0; 9712292SN/A 9722292SN/A // Loop through the instructions, putting them in the instruction 9732292SN/A // queue. 9742292SN/A for ( ; dis_num_inst < insts_to_add && 9752292SN/A dis_num_inst < dispatchWidth; 9762292SN/A ++dis_num_inst) 9772292SN/A { 9782292SN/A inst = insts_to_dispatch.front(); 9792292SN/A 9802292SN/A if (dispatchStatus[tid] == Unblocking) { 9812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9822292SN/A "buffer\n", tid); 9832292SN/A } 9842292SN/A 9852292SN/A // Make sure there's a valid instruction there. 9862292SN/A assert(inst); 9872292SN/A 9882292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9892292SN/A "IQ.\n", 9902292SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9912292SN/A 9922292SN/A // Be sure to mark these instructions as ready so that the 9932292SN/A // commit stage can go ahead and execute them, and mark 9942292SN/A // them as issued so the IQ doesn't reprocess them. 9952292SN/A 9962292SN/A // Check for squashed instructions. 9972292SN/A if (inst->isSquashed()) { 9982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9992292SN/A "not adding to IQ.\n", tid); 10002292SN/A 10012292SN/A ++iewDispSquashedInsts; 10022292SN/A 10032292SN/A insts_to_dispatch.pop(); 10042292SN/A 10052292SN/A //Tell Rename That An Instruction has been processed 10062292SN/A if (inst->isLoad() || inst->isStore()) { 10072292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10082292SN/A } 10092292SN/A toRename->iewInfo[tid].dispatched++; 10102292SN/A 10112292SN/A continue; 10122292SN/A } 10132292SN/A 10142292SN/A // Check for full conditions. 10152292SN/A if (instQueue.isFull(tid)) { 10162292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10172292SN/A 10182292SN/A // Call function to start blocking. 10192292SN/A block(tid); 10202292SN/A 10212292SN/A // Set unblock to false. Special case where we are using 10222292SN/A // skidbuffer (unblocking) instructions but then we still 10232292SN/A // get full in the IQ. 10242292SN/A toRename->iewUnblock[tid] = false; 10252292SN/A 10262292SN/A ++iewIQFullEvents; 10272292SN/A break; 10282292SN/A } else if (ldstQueue.isFull(tid)) { 10292292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10302292SN/A 10312292SN/A // Call function to start blocking. 10322292SN/A block(tid); 10332292SN/A 10342292SN/A // Set unblock to false. Special case where we are using 10352292SN/A // skidbuffer (unblocking) instructions but then we still 10362292SN/A // get full in the IQ. 10372292SN/A toRename->iewUnblock[tid] = false; 10382292SN/A 10392292SN/A ++iewLSQFullEvents; 10402292SN/A break; 10412292SN/A } 10422292SN/A 10432292SN/A // Otherwise issue the instruction just fine. 10442292SN/A if (inst->isLoad()) { 10452292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10462292SN/A "encountered, adding to LSQ.\n", tid); 10472292SN/A 10482292SN/A // Reserve a spot in the load store queue for this 10492292SN/A // memory access. 10502292SN/A ldstQueue.insertLoad(inst); 10512292SN/A 10522292SN/A ++iewDispLoadInsts; 10532292SN/A 10542336SN/A add_to_iq = true; 10552336SN/A 10562336SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10572336SN/A } else if (inst->isStore()) { 10582348SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10592292SN/A "encountered, adding to LSQ.\n", tid); 10602292SN/A 10612292SN/A ldstQueue.insertStore(inst); 10622292SN/A 10632292SN/A ++iewDispStoreInsts; 10642292SN/A 10652292SN/A if (inst->isStoreConditional()) { 10662292SN/A // Store conditionals need to be set as "canCommit()" 10672292SN/A // so that commit can process them when they reach the 10682292SN/A // head of commit. 10692292SN/A // @todo: This is somewhat specific to Alpha. 10702326SN/A inst->setCanCommit(); 10712292SN/A instQueue.insertNonSpec(inst); 10722292SN/A add_to_iq = false; 10732292SN/A 10742292SN/A ++iewDispNonSpecInsts; 10752292SN/A } else { 10762292SN/A add_to_iq = true; 10772292SN/A } 10782292SN/A 10792292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10802292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10812292SN/A // Same as non-speculative stores. 10822326SN/A inst->setCanCommit(); 10832292SN/A instQueue.insertBarrier(inst); 10842727Sktlim@umich.edu add_to_iq = false; 10852301SN/A } else if (inst->isNop()) { 10862292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10872292SN/A "skipping.\n", tid); 10882292SN/A 10892292SN/A inst->setIssued(); 10902292SN/A inst->setExecuted(); 10912292SN/A inst->setCanCommit(); 10922292SN/A 10932292SN/A instQueue.recordProducer(inst); 10942292SN/A 10952326SN/A iewExecutedNop[tid]++; 10962292SN/A 10972292SN/A add_to_iq = false; 10982292SN/A } else if (inst->isExecuted()) { 10992292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11002292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11014033Sktlim@umich.edu "skipping.\n"); 11024033Sktlim@umich.edu 11034033Sktlim@umich.edu inst->setIssued(); 11044033Sktlim@umich.edu inst->setCanCommit(); 11054033Sktlim@umich.edu 11064033Sktlim@umich.edu instQueue.recordProducer(inst); 11074033Sktlim@umich.edu 11084033Sktlim@umich.edu add_to_iq = false; 11094033Sktlim@umich.edu } else { 11104033Sktlim@umich.edu add_to_iq = true; 11114033Sktlim@umich.edu } 11124033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11134033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11144033Sktlim@umich.edu "encountered, skipping.\n", tid); 11152292SN/A 11162292SN/A // Same as non-speculative stores. 11172292SN/A inst->setCanCommit(); 11182292SN/A 11192292SN/A // Specifically insert it as nonspeculative. 11202292SN/A instQueue.insertNonSpec(inst); 11212292SN/A 11222292SN/A ++iewDispNonSpecInsts; 11232292SN/A 11242292SN/A add_to_iq = false; 11252292SN/A } 11262292SN/A 11272292SN/A // If the instruction queue is not full, then add the 11282292SN/A // instruction. 11292292SN/A if (add_to_iq) { 11302935Sksewell@umich.edu instQueue.insert(inst); 11312292SN/A } 11322292SN/A 11332292SN/A insts_to_dispatch.pop(); 11342292SN/A 11352292SN/A toRename->iewInfo[tid].dispatched++; 11362292SN/A 11372292SN/A ++iewDispatchedInsts; 11382292SN/A } 11392292SN/A 11402292SN/A if (!insts_to_dispatch.empty()) { 11412292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11422292SN/A block(tid); 11432292SN/A toRename->iewUnblock[tid] = false; 11442292SN/A } 11452292SN/A 11462292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11472292SN/A dispatchStatus[tid] = Running; 11482292SN/A 11492292SN/A updatedQueues = true; 11502980Sgblack@eecs.umich.edu } 11512292SN/A 11522292SN/A dis_num_inst = 0; 11532292SN/A} 11542980Sgblack@eecs.umich.edu 11552292SN/Atemplate <class Impl> 11562980Sgblack@eecs.umich.eduvoid 11572292SN/ADefaultIEW<Impl>::printAvailableInsts() 11582292SN/A{ 11592292SN/A int inst = 0; 11602292SN/A 11612292SN/A std::cout << "Available Instructions: "; 11622292SN/A 11632292SN/A while (fromIssue->insts[inst]) { 11642980Sgblack@eecs.umich.edu 11652292SN/A if (inst%3==0) std::cout << "\n\t"; 11662292SN/A 11672292SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11682292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11692292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11702292SN/A 11712292SN/A inst++; 11722292SN/A 11732292SN/A } 11746221Snate@binkert.org 11756221Snate@binkert.org std::cout << "\n"; 11762292SN/A} 11773867Sbinkertn@umich.edu 11786221Snate@binkert.orgtemplate <class Impl> 11792292SN/Avoid 11802292SN/ADefaultIEW<Impl>::executeInsts() 11812292SN/A{ 11822698Sktlim@umich.edu wbNumInst = 0; 11832698Sktlim@umich.edu wbCycle = 0; 11841062SN/A 11851062SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 11862333SN/A list<ThreadID>::iterator end = activeThreads->end(); 11872292SN/A 11882333SN/A while (threads != end) { 11892326SN/A ThreadID tid = *threads++; 11901062SN/A fetchRedirect[tid] = false; 11912292SN/A } 11921062SN/A 11932333SN/A // Uncomment this if you want to see all available instructions. 11941062SN/A // @todo This doesn't actually work anymore, we should fix it. 11952292SN/A// printAvailableInsts(); 11962292SN/A 11971062SN/A // Execute/writeback any instructions that are available. 11981062SN/A int insts_to_execute = fromIssue->size; 11991062SN/A int inst_num = 0; 12002292SN/A for (; inst_num < insts_to_execute; 12011062SN/A ++inst_num) { 12021062SN/A 12031062SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12041062SN/A 12051062SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12062292SN/A 12072292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12082292SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12091062SN/A 12101062SN/A // Check if the instruction is squashed; if so then skip it 12111062SN/A if (inst->isSquashed()) { 12122820Sktlim@umich.edu DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12131062SN/A 12141062SN/A // Consider this instruction executed so that commit can go 12151062SN/A // ahead and retire the instruction. 12162292SN/A inst->setExecuted(); 12171062SN/A 12181062SN/A // Not sure if I should set this here or just let commit try to 12191062SN/A // commit any squashed instructions. I like the latter a bit more. 12201062SN/A inst->setCanCommit(); 12212292SN/A 12222292SN/A ++iewExecSquashedInsts; 12232292SN/A 12241062SN/A decrWb(inst->seqNum); 12251062SN/A continue; 12261062SN/A } 12271062SN/A 12282292SN/A Fault fault = NoFault; 12292292SN/A 12302292SN/A // Execute instruction. 12311062SN/A // Note that if the instruction faults, it will be handled 12322367SN/A // at the commit stage. 12331062SN/A if (inst->isMemRef()) { 12342292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12352367SN/A "reference.\n"); 12362292SN/A 12372292SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12382292SN/A if (inst->isLoad()) { 12392367SN/A // Loads will mark themselves as executed, and their writeback 12402367SN/A // event adds the instruction to the queue to commit 12412367SN/A fault = ldstQueue.executeLoad(inst); 12423732Sktlim@umich.edu 12433732Sktlim@umich.edu if (inst->isTranslationDelayed() && 12442367SN/A fault == NoFault) { 12452367SN/A // A hw page table walk is currently going on; the 12462367SN/A // instruction must be deferred. 12472367SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12482367SN/A "load.\n"); 12492367SN/A instQueue.deferMemInst(inst); 12502367SN/A continue; 12512292SN/A } 12522326SN/A 12532326SN/A if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12542326SN/A inst->fault = NoFault; 12552326SN/A } 12561062SN/A } else if (inst->isStore()) { 12572292SN/A fault = ldstQueue.executeStore(inst); 12581062SN/A 12591062SN/A if (inst->isTranslationDelayed() && 12601062SN/A fault == NoFault) { 12611062SN/A // A hw page table walk is currently going on; the 12621062SN/A // instruction must be deferred. 12632292SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12642292SN/A "store.\n"); 12652292SN/A instQueue.deferMemInst(inst); 12661062SN/A continue; 12671062SN/A } 12682301SN/A 12691681SN/A // If the store had a fault then it may not have a mem req 12702326SN/A if (fault != NoFault || inst->readPredicate() == false || 12712326SN/A !inst->isStoreConditional()) { 12722326SN/A // If the instruction faulted, then we need to send it along 12732107SN/A // to commit without the instruction completing. 12741681SN/A // Send this instruction to commit, also make sure iew stage 12752292SN/A // realizes there is activity. 12762292SN/A inst->setExecuted(); 12772292SN/A instToCommit(inst); 12786221Snate@binkert.org activityThisCycle(); 12791062SN/A } 12803732Sktlim@umich.edu 12813732Sktlim@umich.edu // Store conditionals will mark themselves as 12821062SN/A // executed, and their writeback event will add the 12831062SN/A // instruction to the queue to commit. 12842292SN/A } else { 12851062SN/A panic("Unexpected memory type!\n"); 12862292SN/A } 12876036Sksewell@umich.edu 12883969Sgblack@eecs.umich.edu } else { 12893969Sgblack@eecs.umich.edu // If the instruction has already faulted, then skip executing it. 12903969Sgblack@eecs.umich.edu // Such case can happen when it faulted during ITLB translation. 12913969Sgblack@eecs.umich.edu // If we execute the instruction (even if it's a nop) the fault 12921062SN/A // will be replaced and we will lose it. 12932292SN/A if (inst->getFault() == NoFault) { 12941062SN/A inst->execute(); 12953795Sgblack@eecs.umich.edu if (inst->readPredicate() == false) 12961062SN/A inst->forwardOldRegs(); 12972292SN/A } 12982292SN/A 12991062SN/A inst->setExecuted(); 13002292SN/A 13014033Sktlim@umich.edu instToCommit(inst); 13022326SN/A } 13032326SN/A 13042292SN/A updateExeInstStats(inst); 13052292SN/A 13062292SN/A // Check if branch prediction was correct, if not then we need 13071062SN/A // to tell commit to squash in flight instructions. Only 13082292SN/A // handle this if there hasn't already been something that 13091062SN/A // redirects fetch in this group of instructions. 13101062SN/A 13111062SN/A // This probably needs to prioritize the redirects if a different 13123732Sktlim@umich.edu // scheduler is used. Currently the scheduler schedules the oldest 13133732Sktlim@umich.edu // instruction first, so the branch resolution order will be correct. 13144033Sktlim@umich.edu ThreadID tid = inst->threadNumber; 13154033Sktlim@umich.edu 13163732Sktlim@umich.edu if (!fetchRedirect[tid] || 13174033Sktlim@umich.edu !toCommit->squash[tid] || 13183732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13193732Sktlim@umich.edu 13201062SN/A // Prevent testing for misprediction on load instructions, 13211062SN/A // that have not been executed. 13221062SN/A bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13231062SN/A 13242292SN/A if (inst->mispredicted() && !loadNotExecuted) { 13251062SN/A fetchRedirect[tid] = true; 13261062SN/A 13272292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13282292SN/A DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 13292292SN/A inst->predInstAddr(), inst->predNextInstAddr()); 13302292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13312292SN/A inst->pcState(), inst->nextInstAddr()); 13322292SN/A // If incorrect, then signal the ROB that it must be squashed. 13332292SN/A squashDueToBranch(inst, tid); 13342292SN/A 13352292SN/A if (inst->readPredTaken()) { 13361062SN/A predictedTakenIncorrect++; 13374033Sktlim@umich.edu } else { 13384033Sktlim@umich.edu predictedNotTakenIncorrect++; 13394033Sktlim@umich.edu } 13404033Sktlim@umich.edu } else if (ldstQueue.violation(tid)) { 13414033Sktlim@umich.edu assert(inst->isMemRef()); 13424033Sktlim@umich.edu // If there was an ordering violation, then get the 13434033Sktlim@umich.edu // DynInst that caused the violation. Note that this 13444033Sktlim@umich.edu // clears the violation signal. 13454033Sktlim@umich.edu DynInstPtr violator; 13464033Sktlim@umich.edu violator = ldstQueue.getMemDepViolator(tid); 13474033Sktlim@umich.edu 13484033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13494033Sktlim@umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13504033Sktlim@umich.edu violator->pcState(), violator->seqNum, 13514033Sktlim@umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13524033Sktlim@umich.edu 13534033Sktlim@umich.edu fetchRedirect[tid] = true; 13544033Sktlim@umich.edu 13554033Sktlim@umich.edu // Tell the instruction queue that a violation has occured. 13564033Sktlim@umich.edu instQueue.violation(inst, violator); 13574033Sktlim@umich.edu 13584033Sktlim@umich.edu // Squash. 13594033Sktlim@umich.edu squashDueToMemOrder(inst,tid); 13604033Sktlim@umich.edu 13614033Sktlim@umich.edu ++memOrderViolationEvents; 13624033Sktlim@umich.edu } else if (ldstQueue.loadBlocked(tid) && 13634033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13641062SN/A fetchRedirect[tid] = true; 13651062SN/A 13662292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13672348SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 13682292SN/A inst->pcState(), inst->seqNum); 13692292SN/A 13702292SN/A squashDueToMemBlocked(inst, tid); 13712292SN/A } 13722292SN/A } else { 13732292SN/A // Reset any state associated with redirects that will not 13742292SN/A // be used. 13752292SN/A if (ldstQueue.violation(tid)) { 13762292SN/A assert(inst->isMemRef()); 13772292SN/A 13782292SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13792292SN/A 13802292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13812292SN/A "%s, inst PC: %s. Addr is: %#x.\n", 13822107SN/A violator->pcState(), inst->pcState(), 13832107SN/A inst->physEffAddr); 13842292SN/A DPRINTF(IEW, "Violation will not be handled because " 13852107SN/A "already squashing\n"); 13862292SN/A 13872107SN/A ++memOrderViolationEvents; 13882326SN/A } 13892326SN/A if (ldstQueue.loadBlocked(tid) && 13902326SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13912326SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13922326SN/A "memory system is blocked. PC: %s [sn:%lli]\n", 13933958Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13942292SN/A DPRINTF(IEW, "Blocked load will not be handled because " 13952107SN/A "already squashing\n"); 13966221Snate@binkert.org 13972107SN/A ldstQueue.setLoadBlockedHandled(tid); 13982698Sktlim@umich.edu } 13992698Sktlim@umich.edu 14002107SN/A } 14012301SN/A } 14022301SN/A 14032292SN/A // Update and record activity if we processed any instructions. 14042292SN/A if (inst_num) { 14052292SN/A if (exeStatus == Idle) { 14062292SN/A exeStatus = Running; 14072292SN/A } 14082367SN/A 14092301SN/A updatedQueues = true; 14102107SN/A 14112292SN/A cpu->activityThisCycle(); 14122292SN/A } 14132292SN/A 14142292SN/A // Need to reset this in case a writeback event needs to write into the 14152292SN/A // iew queue. That way the writeback event will write into the correct 14162107SN/A // spot in the queue. 14172301SN/A wbNumInst = 0; 14182348SN/A 14192348SN/A} 14202348SN/A 14212348SN/Atemplate <class Impl> 14222326SN/Avoid 14232107SN/ADefaultIEW<Impl>::writebackInsts() 14242820Sktlim@umich.edu{ 14252820Sktlim@umich.edu // Loop through the head of the time buffer and wake any 14262107SN/A // dependents. These instructions are about to write back. Also 14271060SN/A // mark scoreboard that this instruction is finally complete. 14281060SN/A // Either have IEW have direct access to scoreboard, or have this 14291681SN/A // as part of backwards communication. 14301060SN/A for (int inst_num = 0; inst_num < wbWidth && 14312292SN/A toCommit->insts[inst_num]; inst_num++) { 14321060SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14332292SN/A ThreadID tid = inst->threadNumber; 14342292SN/A 14351060SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14362292SN/A inst->seqNum, inst->pcState()); 14372292SN/A 14381060SN/A iewInstsToCommit[tid]++; 14392292SN/A 14401060SN/A // Some instructions will be sent to commit without having 14412326SN/A // executed because they need commit to handle them. 14422326SN/A // E.g. Uncached loads have not actually executed when they 14431062SN/A // are first sent to commit. Instead commit must tell the LSQ 14446221Snate@binkert.org // when it's ready to execute the uncached load. 14456221Snate@binkert.org if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14461060SN/A int dependents = instQueue.wakeDependents(inst); 14472326SN/A 14483867Sbinkertn@umich.edu for (int i = 0; i < inst->numDestRegs(); i++) { 14496221Snate@binkert.org //mark as Ready 14501060SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14512292SN/A inst->renamedDestRegIdx(i)); 14521060SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14532292SN/A } 14542292SN/A 14551060SN/A if (dependents) { 14561060SN/A producerInst[tid]++; 14572292SN/A consumerInst[tid]+= dependents; 14582292SN/A } 14591060SN/A writebackCount[tid]++; 14602292SN/A } 14612292SN/A 14622292SN/A decrWb(inst->seqNum); 14632292SN/A } 14642292SN/A} 14652292SN/A 14662292SN/Atemplate<class Impl> 14672292SN/Avoid 14682292SN/ADefaultIEW<Impl>::tick() 14692292SN/A{ 14702292SN/A wbNumInst = 0; 14712292SN/A wbCycle = 0; 14722292SN/A 14732292SN/A wroteToTimeBuffer = false; 14742292SN/A updatedQueues = false; 14752292SN/A 14762292SN/A sortInsts(); 14772292SN/A 14782292SN/A // Free function units marked as being freed this cycle. 14792292SN/A fuPool->processFreeUnits(); 14802292SN/A 14812292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 14821681SN/A list<ThreadID>::iterator end = activeThreads->end(); 14831681SN/A 14841061SN/A // Check stall and squash signals, dispatch any instructions. 14851061SN/A while (threads != end) { 14861061SN/A ThreadID tid = *threads++; 14871681SN/A 14882292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14893867Sbinkertn@umich.edu 14903867Sbinkertn@umich.edu checkSignalsAndUpdate(tid); 14916221Snate@binkert.org dispatch(tid); 14922292SN/A } 14932292SN/A 14942292SN/A if (exeStatus != Squashing) { 14952348SN/A executeInsts(); 14962292SN/A 14972292SN/A writebackInsts(); 14982292SN/A 14992292SN/A // Have the instruction queue try to schedule any ready instructions. 15002292SN/A // (In actuality, this scheduling is for instructions that will 15012292SN/A // be executed next cycle.) 15022292SN/A instQueue.scheduleReadyInsts(); 15032292SN/A 15042292SN/A // Also should advance its own time buffers if the stage ran. 15052292SN/A // Not the best place for it, but this works (hopefully). 15062292SN/A issueToExecQueue.advance(); 15072292SN/A } 15082292SN/A 15092292SN/A bool broadcast_free_entries = false; 15102292SN/A 15112292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15122292SN/A exeStatus = Idle; 15134033Sktlim@umich.edu updateLSQNextCycle = false; 15142292SN/A 15152292SN/A broadcast_free_entries = true; 15162292SN/A } 15172292SN/A 15182292SN/A // Writeback any stores using any leftover bandwidth. 15192292SN/A ldstQueue.writebackStores(); 15202292SN/A 15212292SN/A // Check the committed load/store signals to see if there's a load 15222292SN/A // or store to commit. Also check if it's being told to execute a 15232292SN/A // nonspeculative instruction. 15242292SN/A // This is pretty inefficient... 15252292SN/A 15262292SN/A threads = activeThreads->begin(); 15272292SN/A while (threads != end) { 15282292SN/A ThreadID tid = (*threads++); 15292292SN/A 15302292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15312292SN/A 15322292SN/A // Update structures based on instructions committed. 15332292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15342292SN/A !fromCommit->commitInfo[tid].squash && 15352292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15362292SN/A 15372292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15381061SN/A 15391061SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15402292SN/A 15412292SN/A updateLSQNextCycle = true; 15422292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15432292SN/A } 15442292SN/A 15452292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15462292SN/A 15472292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15482292SN/A if (fromCommit->commitInfo[tid].uncached) { 15492292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15501061SN/A fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15511060SN/A } else { 15521060SN/A instQueue.scheduleNonSpec( 15532301SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15541060SN/A } 15552301SN/A } 15561060SN/A 15576221Snate@binkert.org if (broadcast_free_entries) { 15581060SN/A toFetch->iewInfo[tid].iqCount = 15592301SN/A instQueue.getCount(tid); 15602301SN/A toFetch->iewInfo[tid].ldstqCount = 15612301SN/A ldstQueue.getCount(tid); 15622301SN/A 15632301SN/A toRename->iewInfo[tid].usedIQ = true; 15646221Snate@binkert.org toRename->iewInfo[tid].freeIQEntries = 15652301SN/A instQueue.numFreeEntries(); 15662727Sktlim@umich.edu toRename->iewInfo[tid].usedLSQ = true; 15672301SN/A toRename->iewInfo[tid].freeLSQEntries = 15682669Sktlim@umich.edu ldstQueue.numFreeEntries(tid); 15692301SN/A 15701060SN/A wroteToTimeBuffer = true; 15712301SN/A } 15722301SN/A 15732301SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15742301SN/A tid, toRename->iewInfo[tid].dispatched); 15756221Snate@binkert.org } 15761060SN/A 15772301SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15782301SN/A "LSQ has %i free entries.\n", 15792301SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15802301SN/A ldstQueue.numFreeEntries()); 15816221Snate@binkert.org 15821060SN/A updateStatus(); 15832301SN/A 15846221Snate@binkert.org if (wroteToTimeBuffer) { 15851060SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15861060SN/A cpu->activityThisCycle(); 15871060SN/A } 1588} 1589 1590template <class Impl> 1591void 1592DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1593{ 1594 ThreadID tid = inst->threadNumber; 1595 1596 // 1597 // Pick off the software prefetches 1598 // 1599#ifdef TARGET_ALPHA 1600 if (inst->isDataPrefetch()) 1601 iewExecutedSwp[tid]++; 1602 else 1603 iewIewExecutedcutedInsts++; 1604#else 1605 iewExecutedInsts++; 1606#endif 1607 1608 // 1609 // Control operations 1610 // 1611 if (inst->isControl()) 1612 iewExecutedBranches[tid]++; 1613 1614 // 1615 // Memory operations 1616 // 1617 if (inst->isMemRef()) { 1618 iewExecutedRefs[tid]++; 1619 1620 if (inst->isLoad()) { 1621 iewExecLoadInsts[tid]++; 1622 } 1623 } 1624} 1625 1626template <class Impl> 1627void 1628DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1629{ 1630 ThreadID tid = inst->threadNumber; 1631 1632 if (!fetchRedirect[tid] || 1633 !toCommit->squash[tid] || 1634 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1635 1636 if (inst->mispredicted()) { 1637 fetchRedirect[tid] = true; 1638 1639 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1640 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1641 inst->predInstAddr(), inst->predNextInstAddr()); 1642 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1643 " NPC: %#x.\n", inst->nextInstAddr(), 1644 inst->nextInstAddr()); 1645 // If incorrect, then signal the ROB that it must be squashed. 1646 squashDueToBranch(inst, tid); 1647 1648 if (inst->readPredTaken()) { 1649 predictedTakenIncorrect++; 1650 } else { 1651 predictedNotTakenIncorrect++; 1652 } 1653 } 1654 } 1655} 1656