iew_impl.hh revision 6658
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 67598Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 77598Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 87598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 97598Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 107598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 117598Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 127598Sminkyu.jeong@arm.com * neither the name of the copyright holders nor the names of its 137598Sminkyu.jeong@arm.com * contributors may be used to endorse or promote products derived from 142326SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A * 281689SN/A * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311689SN/A// @todo: Fix the instantaneous communication among all the stages within 321689SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341689SN/A 351689SN/A#include <queue> 361689SN/A 371689SN/A#include "base/timebuf.hh" 381689SN/A#include "config/the_isa.hh" 392665Ssaidi@eecs.umich.edu#include "cpu/o3/fu_pool.hh" 402665Ssaidi@eecs.umich.edu#include "cpu/o3/iew.hh" 411689SN/A#include "params/DerivO3CPU.hh" 421689SN/A 431060SN/Ausing namespace std; 441060SN/A 451689SN/Atemplate<class Impl> 461060SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 471060SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 481060SN/A cpu(_cpu), 496658Snate@binkert.org instQueue(_cpu, this, params), 502292SN/A ldstQueue(_cpu, this, params), 511717SN/A fuPool(params->fuPool), 528229Snate@binkert.org commitToIEWDelay(params->commitToIEWDelay), 535529Snate@binkert.org renameToIEWDelay(params->renameToIEWDelay), 541060SN/A issueToExecuteDelay(params->issueToExecuteDelay), 556221Snate@binkert.org dispatchWidth(params->dispatchWidth), 566221Snate@binkert.org issueWidth(params->issueWidth), 571681SN/A wbOutstanding(0), 585529Snate@binkert.org wbWidth(params->wbWidth), 592873Sktlim@umich.edu numThreads(params->numThreads), 604329Sktlim@umich.edu switchedOut(false) 614329Sktlim@umich.edu{ 624329Sktlim@umich.edu _status = Active; 632292SN/A exeStatus = Running; 642292SN/A wbStatus = Idle; 652292SN/A 662292SN/A // Setup wire to read instructions coming from issue. 672820Sktlim@umich.edu fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 682292SN/A 692820Sktlim@umich.edu // Instruction queue needs the queue between issue and execute. 702820Sktlim@umich.edu instQueue.setIssueToExecuteQueue(&issueToExecQueue); 715529Snate@binkert.org 722307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 731060SN/A dispatchStatus[tid] = Running; 742292SN/A stalls[tid].commit = false; 752292SN/A fetchRedirect[tid] = false; 762292SN/A } 771060SN/A 781060SN/A wbMax = wbWidth * params->wbDepth; 791060SN/A 801060SN/A updateLSQNextCycle = false; 811060SN/A 821060SN/A ableToIssue = true; 831681SN/A 846221Snate@binkert.org skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 856221Snate@binkert.org} 866221Snate@binkert.org 876221Snate@binkert.orgtemplate <class Impl> 882292SN/Astd::string 892292SN/ADefaultIEW<Impl>::name() const 902820Sktlim@umich.edu{ 912820Sktlim@umich.edu return cpu->name() + ".iew"; 922292SN/A} 932292SN/A 942820Sktlim@umich.edutemplate <class Impl> 952820Sktlim@umich.eduvoid 962292SN/ADefaultIEW<Impl>::regStats() 972292SN/A{ 982292SN/A using namespace Stats; 992292SN/A 1002292SN/A instQueue.regStats(); 1012292SN/A ldstQueue.regStats(); 1022292SN/A 1032292SN/A iewIdleCycles 1041060SN/A .name(name() + ".iewIdleCycles") 1051060SN/A .desc("Number of cycles IEW is idle"); 1061681SN/A 1071062SN/A iewSquashCycles 1082292SN/A .name(name() + ".iewSquashCycles") 1091062SN/A .desc("Number of cycles IEW is squashing"); 1102301SN/A 1112301SN/A iewBlockCycles 1121062SN/A .name(name() + ".iewBlockCycles") 1132727Sktlim@umich.edu .desc("Number of cycles IEW is blocking"); 1141062SN/A 1151062SN/A iewUnblockCycles 1161062SN/A .name(name() + ".iewUnblockCycles") 1171062SN/A .desc("Number of cycles IEW is unblocking"); 1181062SN/A 1191062SN/A iewDispatchedInsts 1201062SN/A .name(name() + ".iewDispatchedInsts") 1211062SN/A .desc("Number of instructions dispatched to IQ"); 1221062SN/A 1231062SN/A iewDispSquashedInsts 1241062SN/A .name(name() + ".iewDispSquashedInsts") 1251062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1261062SN/A 1271062SN/A iewDispLoadInsts 1281062SN/A .name(name() + ".iewDispLoadInsts") 1291062SN/A .desc("Number of dispatched load instructions"); 1301062SN/A 1311062SN/A iewDispStoreInsts 1321062SN/A .name(name() + ".iewDispStoreInsts") 1331062SN/A .desc("Number of dispatched store instructions"); 1341062SN/A 1351062SN/A iewDispNonSpecInsts 1361062SN/A .name(name() + ".iewDispNonSpecInsts") 1371062SN/A .desc("Number of dispatched non-speculative instructions"); 1381062SN/A 1391062SN/A iewIQFullEvents 1401062SN/A .name(name() + ".iewIQFullEvents") 1411062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1421062SN/A 1431062SN/A iewLSQFullEvents 1441062SN/A .name(name() + ".iewLSQFullEvents") 1451062SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1461062SN/A 1471062SN/A memOrderViolationEvents 1481062SN/A .name(name() + ".memOrderViolationEvents") 1491062SN/A .desc("Number of memory order violations"); 1501062SN/A 1511062SN/A predictedTakenIncorrect 1521062SN/A .name(name() + ".predictedTakenIncorrect") 1531062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1541062SN/A 1552292SN/A predictedNotTakenIncorrect 1562292SN/A .name(name() + ".predictedNotTakenIncorrect") 1572292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1582292SN/A 1591062SN/A branchMispredicts 1601062SN/A .name(name() + ".branchMispredicts") 1611062SN/A .desc("Number of branch mispredicts detected at execute"); 1621062SN/A 1631062SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1641062SN/A 1651062SN/A iewExecutedInsts 1662292SN/A .name(name() + ".iewExecutedInsts") 1672292SN/A .desc("Number of executed instructions"); 1682292SN/A 1692292SN/A iewExecLoadInsts 1702292SN/A .init(cpu->numThreads) 1712292SN/A .name(name() + ".iewExecLoadInsts") 1722292SN/A .desc("Number of load instructions executed") 1732292SN/A .flags(total); 1742292SN/A 1752292SN/A iewExecSquashedInsts 1762301SN/A .name(name() + ".iewExecSquashedInsts") 1772727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1782353SN/A 1792727Sktlim@umich.edu iewExecutedSwp 1802727Sktlim@umich.edu .init(cpu->numThreads) 1812727Sktlim@umich.edu .name(name() + ".EXEC:swp") 1826221Snate@binkert.org .desc("number of swp insts executed") 1832353SN/A .flags(total); 1842727Sktlim@umich.edu 1852727Sktlim@umich.edu iewExecutedNop 1862727Sktlim@umich.edu .init(cpu->numThreads) 1872727Sktlim@umich.edu .name(name() + ".EXEC:nop") 1882353SN/A .desc("number of nop insts executed") 1892727Sktlim@umich.edu .flags(total); 1902727Sktlim@umich.edu 1912727Sktlim@umich.edu iewExecutedRefs 1926221Snate@binkert.org .init(cpu->numThreads) 1932301SN/A .name(name() + ".EXEC:refs") 1942301SN/A .desc("number of memory reference insts executed") 1952727Sktlim@umich.edu .flags(total); 1962301SN/A 1972727Sktlim@umich.edu iewExecutedBranches 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".EXEC:branches") 2002301SN/A .desc("Number of branches executed") 2012727Sktlim@umich.edu .flags(total); 2022301SN/A 2032727Sktlim@umich.edu iewExecStoreInsts 2046221Snate@binkert.org .name(name() + ".EXEC:stores") 2052301SN/A .desc("Number of stores executed") 2062301SN/A .flags(total); 2072727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2082301SN/A 2092727Sktlim@umich.edu iewExecRate 2106221Snate@binkert.org .name(name() + ".EXEC:rate") 2112301SN/A .desc("Inst execution rate") 2122301SN/A .flags(total); 2132727Sktlim@umich.edu 2142301SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2152301SN/A 2162301SN/A iewInstsToCommit 2172301SN/A .init(cpu->numThreads) 2182727Sktlim@umich.edu .name(name() + ".WB:sent") 2192727Sktlim@umich.edu .desc("cumulative count of insts sent to commit") 2202727Sktlim@umich.edu .flags(total); 2212727Sktlim@umich.edu 2222727Sktlim@umich.edu writebackCount 2232727Sktlim@umich.edu .init(cpu->numThreads) 2242727Sktlim@umich.edu .name(name() + ".WB:count") 2252727Sktlim@umich.edu .desc("cumulative count of insts written-back") 2262727Sktlim@umich.edu .flags(total); 2272301SN/A 2282301SN/A producerInst 2296221Snate@binkert.org .init(cpu->numThreads) 2302301SN/A .name(name() + ".WB:producers") 2312301SN/A .desc("num instructions producing a value") 2322727Sktlim@umich.edu .flags(total); 2332301SN/A 2342326SN/A consumerInst 2356221Snate@binkert.org .init(cpu->numThreads) 2362301SN/A .name(name() + ".WB:consumers") 2372301SN/A .desc("num instructions consuming a value") 2382727Sktlim@umich.edu .flags(total); 2392301SN/A 2402326SN/A wbPenalized 2416221Snate@binkert.org .init(cpu->numThreads) 2422301SN/A .name(name() + ".WB:penalized") 2432301SN/A .desc("number of instrctions required to write to 'other' IQ") 2442727Sktlim@umich.edu .flags(total); 2452301SN/A 2462326SN/A wbPenalizedRate 2476221Snate@binkert.org .name(name() + ".WB:penalized_rate") 2482301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2492301SN/A .flags(total); 2502727Sktlim@umich.edu 2512301SN/A wbPenalizedRate = wbPenalized / writebackCount; 2522326SN/A 2536221Snate@binkert.org wbFanout 2542301SN/A .name(name() + ".WB:fanout") 2552301SN/A .desc("average fanout of values written-back") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A wbFanout = producerInst / consumerInst; 2592301SN/A 2602301SN/A wbRate 2612727Sktlim@umich.edu .name(name() + ".WB:rate") 2622301SN/A .desc("insts written-back per cycle") 2632326SN/A .flags(total); 2642301SN/A wbRate = writebackCount / cpu->numCycles; 2652326SN/A} 2662301SN/A 2672301SN/Atemplate<class Impl> 2682727Sktlim@umich.eduvoid 2692301SN/ADefaultIEW<Impl>::initStage() 2702326SN/A{ 2712301SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 2722326SN/A toRename->iewInfo[tid].usedIQ = true; 2732301SN/A toRename->iewInfo[tid].freeIQEntries = 2742301SN/A instQueue.numFreeEntries(tid); 2752727Sktlim@umich.edu 2762326SN/A toRename->iewInfo[tid].usedLSQ = true; 2771062SN/A toRename->iewInfo[tid].freeLSQEntries = 2781062SN/A ldstQueue.numFreeEntries(tid); 2791681SN/A } 2801060SN/A 2812292SN/A cpu->activateStage(O3CPU::IEWIdx); 2821060SN/A} 2836221Snate@binkert.org 2842292SN/Atemplate<class Impl> 2852292SN/Avoid 2862292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2872292SN/A{ 2882292SN/A timeBuffer = tb_ptr; 2892292SN/A 2902292SN/A // Setup wire to read information from time buffer, from commit. 2912292SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2922292SN/A 2932733Sktlim@umich.edu // Setup wire to write information back to previous stages. 2941060SN/A toRename = timeBuffer->getWire(0); 2951060SN/A 2961681SN/A toFetch = timeBuffer->getWire(0); 2971060SN/A 2982292SN/A // Instruction queue also needs main time buffer. 2991060SN/A instQueue.setTimeBuffer(tb_ptr); 3001060SN/A} 3011060SN/A 3021060SN/Atemplate<class Impl> 3031060SN/Avoid 3041060SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3051060SN/A{ 3061060SN/A renameQueue = rq_ptr; 3071060SN/A 3082292SN/A // Setup wire to read information from rename queue. 3092292SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3101060SN/A} 3111060SN/A 3121060SN/Atemplate<class Impl> 3131060SN/Avoid 3141681SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3151060SN/A{ 3162292SN/A iewQueue = iq_ptr; 3171060SN/A 3181060SN/A // Setup wire to write instructions to commit. 3191060SN/A toCommit = iewQueue->getWire(0); 3201060SN/A} 3211060SN/A 3221060SN/Atemplate<class Impl> 3231060SN/Avoid 3241681SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3251060SN/A{ 3262292SN/A activeThreads = at_ptr; 3271060SN/A 3281060SN/A ldstQueue.setActiveThreads(at_ptr); 3291060SN/A instQueue.setActiveThreads(at_ptr); 3301060SN/A} 3311060SN/A 3321060SN/Atemplate<class Impl> 3331060SN/Avoid 3341681SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3351060SN/A{ 3366221Snate@binkert.org scoreboard = sb_ptr; 3371060SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402292SN/Abool 3412292SN/ADefaultIEW<Impl>::drain() 3421060SN/A{ 3431060SN/A // IEW is ready to drain at any time. 3441681SN/A cpu->signalDrained(); 3451060SN/A return true; 3462292SN/A} 3471060SN/A 3482292SN/Atemplate <class Impl> 3491060SN/Avoid 3501060SN/ADefaultIEW<Impl>::resume() 3512307SN/A{ 3522863Sktlim@umich.edu} 3532843Sktlim@umich.edu 3542307SN/Atemplate <class Impl> 3552843Sktlim@umich.eduvoid 3562843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3572863Sktlim@umich.edu{ 3581681SN/A // Clear any state. 3591681SN/A switchedOut = true; 3602316SN/A assert(insts[0].empty()); 3611681SN/A assert(skidBuffer[0].empty()); 3622843Sktlim@umich.edu 3632843Sktlim@umich.edu instQueue.switchOut(); 3642843Sktlim@umich.edu ldstQueue.switchOut(); 3652843Sktlim@umich.edu fuPool->switchOut(); 3662843Sktlim@umich.edu 3672843Sktlim@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3682843Sktlim@umich.edu while (!insts[tid].empty()) 3691681SN/A insts[tid].pop(); 3702348SN/A while (!skidBuffer[tid].empty()) 3712307SN/A skidBuffer[tid].pop(); 3722367SN/A } 3732367SN/A} 3741681SN/A 3752307SN/Atemplate <class Impl> 3762307SN/Avoid 3772307SN/ADefaultIEW<Impl>::takeOverFrom() 3782307SN/A{ 3796221Snate@binkert.org // Reset all state. 3806221Snate@binkert.org _status = Active; 3816221Snate@binkert.org exeStatus = Running; 3826221Snate@binkert.org wbStatus = Idle; 3836221Snate@binkert.org switchedOut = false; 3842307SN/A 3851681SN/A instQueue.takeOverFrom(); 3861681SN/A ldstQueue.takeOverFrom(); 3872307SN/A fuPool->takeOverFrom(); 3881681SN/A 3892307SN/A initStage(); 3901060SN/A cpu->activityThisCycle(); 3912348SN/A 3922307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3932307SN/A dispatchStatus[tid] = Running; 3942307SN/A stalls[tid].commit = false; 3952307SN/A fetchRedirect[tid] = false; 3961060SN/A } 3972307SN/A 3982307SN/A updateLSQNextCycle = false; 3992307SN/A 4001060SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4012307SN/A issueToExecQueue.advance(); 4022307SN/A } 4031060SN/A} 4046221Snate@binkert.org 4056221Snate@binkert.orgtemplate<class Impl> 4066221Snate@binkert.orgvoid 4076221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4082307SN/A{ 4091060SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4102307SN/A 4112307SN/A // Tell the IQ to start squashing. 4122873Sktlim@umich.edu instQueue.squash(tid); 4132307SN/A 4141060SN/A // Tell the LDSTQ to start squashing. 4151060SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4161060SN/A updatedQueues = true; 4171681SN/A 4181060SN/A // Clear the skid buffer in case it has any data in it. 4196221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4202107SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4216221Snate@binkert.org 4222107SN/A while (!skidBuffer[tid].empty()) { 4232292SN/A if (skidBuffer[tid].front()->isLoad() || 4242292SN/A skidBuffer[tid].front()->isStore() ) { 4252107SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4262292SN/A } 4272326SN/A 4282292SN/A toRename->iewInfo[tid].dispatched++; 4292107SN/A 4302292SN/A skidBuffer[tid].pop(); 4312935Sksewell@umich.edu } 4324632Sgblack@eecs.umich.edu 4332935Sksewell@umich.edu emptyRenameInsts(tid); 4342292SN/A} 4352292SN/A 4362292SN/Atemplate<class Impl> 4372292SN/Avoid 4382292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4392107SN/A{ 4402292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4412107SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4422292SN/A 4432292SN/A toCommit->squash[tid] = true; 4442107SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4452702Sktlim@umich.edu toCommit->mispredPC[tid] = inst->readPC(); 4462107SN/A toCommit->branchMispredict[tid] = true; 4472107SN/A 4482107SN/A#if ISA_HAS_DELAY_SLOT 4492107SN/A int instSize = sizeof(TheISA::MachInst); 4506221Snate@binkert.org toCommit->branchTaken[tid] = 4512292SN/A !(inst->readNextPC() + instSize == inst->readNextNPC() && 4527720Sgblack@eecs.umich.edu (inst->readNextPC() == inst->readPC() + instSize || 4537720Sgblack@eecs.umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4542292SN/A#else 4557852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->readNextPC() != 4567852SMatt.Horsnell@arm.com (inst->readPC() + sizeof(TheISA::MachInst)); 4577852SMatt.Horsnell@arm.com#endif 4587852SMatt.Horsnell@arm.com toCommit->nextPC[tid] = inst->readNextPC(); 4597852SMatt.Horsnell@arm.com toCommit->nextNPC[tid] = inst->readNextNPC(); 4602935Sksewell@umich.edu toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 4617852SMatt.Horsnell@arm.com 4627852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4632292SN/A 4647852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4657852SMatt.Horsnell@arm.com} 4667852SMatt.Horsnell@arm.com 4672292SN/Atemplate<class Impl> 4687852SMatt.Horsnell@arm.comvoid 4697852SMatt.Horsnell@arm.comDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4707852SMatt.Horsnell@arm.com{ 4712292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4722292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4732292SN/A 4742292SN/A toCommit->squash[tid] = true; 4756221Snate@binkert.org toCommit->squashedSeqNum[tid] = inst->seqNum; 4762292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4772292SN/A toCommit->nextNPC[tid] = inst->readNextNPC(); 4787720Sgblack@eecs.umich.edu toCommit->branchMispredict[tid] = false; 4792292SN/A 4807852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4817852SMatt.Horsnell@arm.com 4827852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4837852SMatt.Horsnell@arm.com} 4847852SMatt.Horsnell@arm.com 4857852SMatt.Horsnell@arm.comtemplate<class Impl> 4867852SMatt.Horsnell@arm.comvoid 4878137SAli.Saidi@ARM.comDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 4882292SN/A{ 4897852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4902292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4917852SMatt.Horsnell@arm.com 4927852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4932292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4942292SN/A toCommit->nextPC[tid] = inst->readPC(); 4952292SN/A toCommit->nextNPC[tid] = inst->readNextPC(); 4962292SN/A toCommit->branchMispredict[tid] = false; 4976221Snate@binkert.org 4982292SN/A // Must include the broadcasted SN in the squash. 4992292SN/A toCommit->includeSquashInst[tid] = true; 5007720Sgblack@eecs.umich.edu 5017852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5027852SMatt.Horsnell@arm.com 5037852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5042292SN/A} 5057852SMatt.Horsnell@arm.com 5067852SMatt.Horsnell@arm.comtemplate<class Impl> 5078137SAli.Saidi@ARM.comvoid 5082292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5097852SMatt.Horsnell@arm.com{ 5107852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5112292SN/A 5127852SMatt.Horsnell@arm.com if (dispatchStatus[tid] != Blocked && 5132292SN/A dispatchStatus[tid] != Unblocking) { 5147852SMatt.Horsnell@arm.com toRename->iewBlock[tid] = true; 5157852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5162292SN/A } 5172292SN/A 5182292SN/A // Add the current inputs to the skid buffer so they can be 5192292SN/A // reprocessed when this stage unblocks. 5206221Snate@binkert.org skidInsert(tid); 5212292SN/A 5222292SN/A dispatchStatus[tid] = Blocked; 5232292SN/A} 5242292SN/A 5252292SN/Atemplate<class Impl> 5262292SN/Avoid 5272292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5282292SN/A{ 5292292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5302292SN/A "buffer %u.\n",tid, tid); 5312292SN/A 5322292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5332292SN/A // Also switch status to running. 5342292SN/A if (skidBuffer[tid].empty()) { 5352292SN/A toRename->iewUnblock[tid] = true; 5362292SN/A wroteToTimeBuffer = true; 5372292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5382292SN/A dispatchStatus[tid] = Running; 5396221Snate@binkert.org } 5402292SN/A} 5412292SN/A 5422292SN/Atemplate<class Impl> 5432292SN/Avoid 5442292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5452292SN/A{ 5462292SN/A instQueue.wakeDependents(inst); 5472292SN/A} 5482292SN/A 5492292SN/Atemplate<class Impl> 5502292SN/Avoid 5512292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5522292SN/A{ 5532292SN/A instQueue.rescheduleMemInst(inst); 5542292SN/A} 5552292SN/A 5562292SN/Atemplate<class Impl> 5571060SN/Avoid 5581681SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5591060SN/A{ 5601060SN/A instQueue.replayMemInst(inst); 5612292SN/A} 5622292SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5662292SN/A{ 5671681SN/A // This function should not be called after writebackInsts in a 5681681SN/A // single cycle. That will cause problems with an instruction 5691060SN/A // being added to the queue to commit without being processed by 5702292SN/A // writebackInsts prior to being sent to commit. 5711060SN/A 5722292SN/A // First check the time slot that this instruction will write 5732292SN/A // to. If there are free write ports at the time, then go ahead 5741060SN/A // and write the instruction to that time. If there are not, 5752292SN/A // keep looking back to see where's the first time there's a 5762292SN/A // free slot. 5772292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5782292SN/A ++wbNumInst; 5793221Sktlim@umich.edu if (wbNumInst == wbWidth) { 5803221Sktlim@umich.edu ++wbCycle; 5813221Sktlim@umich.edu wbNumInst = 0; 5823221Sktlim@umich.edu } 5833221Sktlim@umich.edu 5842292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5852292SN/A } 5862292SN/A 5872292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 5882326SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 5892292SN/A // Add finished instruction to queue to commit. 5902292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5912820Sktlim@umich.edu (*iewQueue)[wbCycle].size++; 5922292SN/A} 5932292SN/A 5942292SN/Atemplate <class Impl> 5952292SN/Aunsigned 5962353SN/ADefaultIEW<Impl>::validInstsFromRename() 5972292SN/A{ 5982292SN/A unsigned inst_count = 0; 5992353SN/A 6002353SN/A for (int i=0; i<fromRename->size; i++) { 6012292SN/A if (!fromRename->insts[i]->isSquashed()) 6022292SN/A inst_count++; 6032292SN/A } 6042292SN/A 6052292SN/A return inst_count; 6062292SN/A} 6072292SN/A 6082292SN/Atemplate<class Impl> 6092292SN/Avoid 6102292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6112292SN/A{ 6122292SN/A DynInstPtr inst = NULL; 6132731Sktlim@umich.edu 6142292SN/A while (!insts[tid].empty()) { 6152292SN/A inst = insts[tid].front(); 6162292SN/A 6172292SN/A insts[tid].pop(); 6182292SN/A 6192292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6202292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6212292SN/A inst->readPC(),tid); 6226221Snate@binkert.org 6232292SN/A skidBuffer[tid].push(inst); 6242292SN/A } 6252292SN/A 6262292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6272292SN/A "Skidbuffer Exceeded Max Size"); 6282292SN/A} 6292292SN/A 6302292SN/Atemplate<class Impl> 6317720Sgblack@eecs.umich.eduint 6322292SN/ADefaultIEW<Impl>::skidCount() 6337720Sgblack@eecs.umich.edu{ 6342292SN/A int max=0; 6352292SN/A 6362292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6372292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6382292SN/A 6392292SN/A while (threads != end) { 6402292SN/A ThreadID tid = *threads++; 6412292SN/A unsigned thread_count = skidBuffer[tid].size(); 6422292SN/A if (max < thread_count) 6432292SN/A max = thread_count; 6442292SN/A } 6452292SN/A 6462292SN/A return max; 6472292SN/A} 6486221Snate@binkert.org 6496221Snate@binkert.orgtemplate<class Impl> 6502292SN/Abool 6513867Sbinkertn@umich.eduDefaultIEW<Impl>::skidsEmpty() 6526221Snate@binkert.org{ 6533867Sbinkertn@umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 6542292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6552292SN/A 6562292SN/A while (threads != end) { 6572292SN/A ThreadID tid = *threads++; 6582292SN/A 6592292SN/A if (!skidBuffer[tid].empty()) 6602292SN/A return false; 6612292SN/A } 6622292SN/A 6632292SN/A return true; 6642292SN/A} 6656221Snate@binkert.org 6666221Snate@binkert.orgtemplate <class Impl> 6672292SN/Avoid 6683867Sbinkertn@umich.eduDefaultIEW<Impl>::updateStatus() 6696221Snate@binkert.org{ 6703867Sbinkertn@umich.edu bool any_unblocking = false; 6713867Sbinkertn@umich.edu 6722292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6732292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6742292SN/A 6752292SN/A while (threads != end) { 6761062SN/A ThreadID tid = *threads++; 6771062SN/A 6781681SN/A if (dispatchStatus[tid] == Unblocking) { 6791062SN/A any_unblocking = true; 6802292SN/A break; 6811062SN/A } 6822292SN/A } 6831062SN/A 6846221Snate@binkert.org // If there are no ready instructions waiting to be scheduled by the IQ, 6856221Snate@binkert.org // and there's no stores waiting to write back, and dispatch is not 6861062SN/A // unblocking, then there is no internal activity for the IEW stage. 6873867Sbinkertn@umich.edu if (_status == Active && !instQueue.hasReadyInsts() && 6886221Snate@binkert.org !ldstQueue.willWB() && !any_unblocking) { 6891062SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6902292SN/A 6912292SN/A deactivateStage(); 6922292SN/A 6932292SN/A _status = Inactive; 6942292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6951062SN/A ldstQueue.willWB() || 6962292SN/A any_unblocking)) { 6972292SN/A // Otherwise there is internal activity. Set to active. 6982292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6997897Shestness@cs.utexas.edu 7002292SN/A activateStage(); 7012292SN/A 7022292SN/A _status = Active; 7031062SN/A } 7042292SN/A} 7051062SN/A 7062292SN/Atemplate <class Impl> 7072292SN/Avoid 7082292SN/ADefaultIEW<Impl>::resetEntries() 7092292SN/A{ 7102292SN/A instQueue.resetEntries(); 7112292SN/A ldstQueue.resetEntries(); 7121062SN/A} 7132292SN/A 7141062SN/Atemplate <class Impl> 7152292SN/Avoid 7161062SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7171062SN/A{ 7181062SN/A if (fromCommit->commitBlock[tid]) { 7191681SN/A stalls[tid].commit = true; 7201062SN/A } 7212292SN/A 7221062SN/A if (fromCommit->commitUnblock[tid]) { 7232292SN/A assert(stalls[tid].commit); 7242292SN/A stalls[tid].commit = false; 7252292SN/A } 7261062SN/A} 7272292SN/A 7282292SN/Atemplate <class Impl> 7296221Snate@binkert.orgbool 7302292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7312292SN/A{ 7322292SN/A bool ret_val(false); 7332292SN/A 7341062SN/A if (stalls[tid].commit) { 7352292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7362292SN/A ret_val = true; 7372292SN/A } else if (instQueue.isFull(tid)) { 7382292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7392292SN/A ret_val = true; 7402292SN/A } else if (ldstQueue.isFull(tid)) { 7412292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7422292SN/A 7436221Snate@binkert.org if (ldstQueue.numLoads(tid) > 0 ) { 7442292SN/A 7452292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7462292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7472292SN/A } 7482292SN/A 7492292SN/A if (ldstQueue.numStores(tid) > 0) { 7502292SN/A 7512292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7522292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7532292SN/A } 7542292SN/A 7552292SN/A ret_val = true; 7562292SN/A } else if (ldstQueue.isStalled(tid)) { 7572292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7582292SN/A ret_val = true; 7592292SN/A } 7602292SN/A 7612292SN/A return ret_val; 7622292SN/A} 7632292SN/A 7642292SN/Atemplate <class Impl> 7652292SN/Avoid 7662292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7672292SN/A{ 7682292SN/A // Check if there's a squash signal, squash if there is 7692292SN/A // Check stall signals, block if there is. 7702292SN/A // If status was Blocked 7712292SN/A // if so then go to unblocking 7722292SN/A // If status was Squashing 7732292SN/A // check if squashing is not high. Switch to running this cycle. 7742292SN/A 7752292SN/A readStallSignals(tid); 7762292SN/A 7772292SN/A if (fromCommit->commitInfo[tid].squash) { 7782292SN/A squash(tid); 7796221Snate@binkert.org 7802292SN/A if (dispatchStatus[tid] == Blocked || 7812292SN/A dispatchStatus[tid] == Unblocking) { 7822292SN/A toRename->iewUnblock[tid] = true; 7832292SN/A wroteToTimeBuffer = true; 7842292SN/A } 7852292SN/A 7862292SN/A dispatchStatus[tid] = Squashing; 7872292SN/A 7882292SN/A fetchRedirect[tid] = false; 7892292SN/A return; 7902292SN/A } 7912292SN/A 7922292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7932292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7942292SN/A 7952292SN/A dispatchStatus[tid] = Squashing; 7962292SN/A 7972292SN/A emptyRenameInsts(tid); 7982292SN/A wroteToTimeBuffer = true; 7992292SN/A return; 8002292SN/A } 8012292SN/A 8022292SN/A if (checkStall(tid)) { 8032292SN/A block(tid); 8042292SN/A dispatchStatus[tid] = Blocked; 8052702Sktlim@umich.edu return; 8062292SN/A } 8072292SN/A 8082702Sktlim@umich.edu if (dispatchStatus[tid] == Blocked) { 8092702Sktlim@umich.edu // Status from previous cycle was blocked, but there are no more stall 8102292SN/A // conditions. Switch over to unblocking. 8112292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8122292SN/A tid); 8132292SN/A 8142292SN/A dispatchStatus[tid] = Unblocking; 8152292SN/A 8162292SN/A unblock(tid); 8172292SN/A 8182292SN/A return; 8192292SN/A } 8202292SN/A 8212292SN/A if (dispatchStatus[tid] == Squashing) { 8222292SN/A // Switch status to running if rename isn't being told to block or 8232292SN/A // squash this cycle. 8242292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8252292SN/A tid); 8262292SN/A 8272292SN/A dispatchStatus[tid] = Running; 8282292SN/A 8292292SN/A return; 8302292SN/A } 8312292SN/A} 8322292SN/A 8332292SN/Atemplate <class Impl> 8342292SN/Avoid 8352292SN/ADefaultIEW<Impl>::sortInsts() 8362292SN/A{ 8372292SN/A int insts_from_rename = fromRename->size; 8382292SN/A#ifdef DEBUG 8392292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8402292SN/A assert(insts[tid].empty()); 8412292SN/A#endif 8422292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8432292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8442292SN/A } 8452292SN/A} 8462292SN/A 8472292SN/Atemplate <class Impl> 8482292SN/Avoid 8492326SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8506221Snate@binkert.org{ 8516221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8522326SN/A 8532292SN/A while (!insts[tid].empty()) { 8542292SN/A 8552292SN/A if (insts[tid].front()->isLoad() || 8562292SN/A insts[tid].front()->isStore() ) { 8572292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 8582292SN/A } 8592292SN/A 8606221Snate@binkert.org toRename->iewInfo[tid].dispatched++; 8612702Sktlim@umich.edu 8624632Sgblack@eecs.umich.edu insts[tid].pop(); 8632935Sksewell@umich.edu } 8642702Sktlim@umich.edu} 8652935Sksewell@umich.edu 8662702Sktlim@umich.edutemplate <class Impl> 8672702Sktlim@umich.eduvoid 8682702Sktlim@umich.eduDefaultIEW<Impl>::wakeCPU() 8692702Sktlim@umich.edu{ 8702702Sktlim@umich.edu cpu->wakeCPU(); 8712702Sktlim@umich.edu} 8722702Sktlim@umich.edu 8732702Sktlim@umich.edutemplate <class Impl> 8742702Sktlim@umich.eduvoid 8752702Sktlim@umich.eduDefaultIEW<Impl>::activityThisCycle() 8762702Sktlim@umich.edu{ 8772702Sktlim@umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 8782702Sktlim@umich.edu cpu->activityThisCycle(); 8792292SN/A} 8802292SN/A 8812292SN/Atemplate <class Impl> 8822292SN/Ainline void 8832292SN/ADefaultIEW<Impl>::activateStage() 8842292SN/A{ 8852292SN/A DPRINTF(Activity, "Activating stage.\n"); 8862292SN/A cpu->activateStage(O3CPU::IEWIdx); 8872292SN/A} 8882292SN/A 8892292SN/Atemplate <class Impl> 8902292SN/Ainline void 8912292SN/ADefaultIEW<Impl>::deactivateStage() 8922292SN/A{ 8932292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8942292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 8952292SN/A} 8962292SN/A 8972733Sktlim@umich.edutemplate<class Impl> 8982292SN/Avoid 8992292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9002292SN/A{ 9012292SN/A // If status is Running or idle, 9022292SN/A // call dispatchInsts() 9032292SN/A // If status is Unblocking, 9042292SN/A // buffer any instructions coming from rename 9052733Sktlim@umich.edu // continue trying to empty skid buffer 9062292SN/A // check if stall conditions have passed 9072292SN/A 9082292SN/A if (dispatchStatus[tid] == Blocked) { 9092292SN/A ++iewBlockCycles; 9106221Snate@binkert.org 9112292SN/A } else if (dispatchStatus[tid] == Squashing) { 9122292SN/A ++iewSquashCycles; 9132292SN/A } 9142292SN/A 9152292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9162292SN/A // will allow, as long as it is not currently blocked. 9172292SN/A if (dispatchStatus[tid] == Running || 9182292SN/A dispatchStatus[tid] == Idle) { 9192292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9202292SN/A "dispatch.\n", tid); 9212292SN/A 9222292SN/A dispatchInsts(tid); 9232292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9242292SN/A // Make sure that the skid buffer has something in it if the 9252292SN/A // status is unblocking. 9262292SN/A assert(!skidsEmpty()); 9272292SN/A 9282292SN/A // If the status was unblocking, then instructions from the skid 9292292SN/A // buffer were used. Remove those instructions and handle 9302292SN/A // the rest of unblocking. 9312292SN/A dispatchInsts(tid); 9322292SN/A 9332292SN/A ++iewUnblockCycles; 9342292SN/A 9352292SN/A if (validInstsFromRename()) { 9362292SN/A // Add the current inputs to the skid buffer so they can be 9372292SN/A // reprocessed when this stage unblocks. 9382292SN/A skidInsert(tid); 9392292SN/A } 9402292SN/A 9412292SN/A unblock(tid); 9422292SN/A } 9432292SN/A} 9442292SN/A 9452292SN/Atemplate <class Impl> 9465215Sgblack@eecs.umich.eduvoid 9472292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9482292SN/A{ 9492292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9502292SN/A // otherwise. 9512292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9522292SN/A dispatchStatus[tid] == Unblocking ? 9532292SN/A skidBuffer[tid] : insts[tid]; 9542292SN/A 9552292SN/A int insts_to_add = insts_to_dispatch.size(); 9562292SN/A 9572292SN/A DynInstPtr inst; 9586221Snate@binkert.org bool add_to_iq = false; 9592292SN/A int dis_num_inst = 0; 9602292SN/A 9612292SN/A // Loop through the instructions, putting them in the instruction 9622292SN/A // queue. 9632292SN/A for ( ; dis_num_inst < insts_to_add && 9642292SN/A dis_num_inst < dispatchWidth; 9652292SN/A ++dis_num_inst) 9662292SN/A { 9672292SN/A inst = insts_to_dispatch.front(); 9682292SN/A 9692292SN/A if (dispatchStatus[tid] == Unblocking) { 9702292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9712292SN/A "buffer\n", tid); 9722292SN/A } 9732292SN/A 9742292SN/A // Make sure there's a valid instruction there. 9752820Sktlim@umich.edu assert(inst); 9762292SN/A 9772292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9782292SN/A "IQ.\n", 9792292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9802292SN/A 9812292SN/A // Be sure to mark these instructions as ready so that the 9822292SN/A // commit stage can go ahead and execute them, and mark 9832292SN/A // them as issued so the IQ doesn't reprocess them. 9842292SN/A 9852292SN/A // Check for squashed instructions. 9862292SN/A if (inst->isSquashed()) { 9872292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9887720Sgblack@eecs.umich.edu "not adding to IQ.\n", tid); 9892292SN/A 9907720Sgblack@eecs.umich.edu ++iewDispSquashedInsts; 9912292SN/A 9922292SN/A insts_to_dispatch.pop(); 9932292SN/A 9942292SN/A //Tell Rename That An Instruction has been processed 9952292SN/A if (inst->isLoad() || inst->isStore()) { 9962292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9972292SN/A } 9982292SN/A toRename->iewInfo[tid].dispatched++; 9992292SN/A 10002292SN/A continue; 10012292SN/A } 10022292SN/A 10032292SN/A // Check for full conditions. 10042292SN/A if (instQueue.isFull(tid)) { 10052292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10062292SN/A 10072292SN/A // Call function to start blocking. 10082292SN/A block(tid); 10092292SN/A 10102292SN/A // Set unblock to false. Special case where we are using 10112292SN/A // skidbuffer (unblocking) instructions but then we still 10122292SN/A // get full in the IQ. 10132292SN/A toRename->iewUnblock[tid] = false; 10142292SN/A 10152292SN/A ++iewIQFullEvents; 10162292SN/A break; 10172292SN/A } else if (ldstQueue.isFull(tid)) { 10182292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10192292SN/A 10202292SN/A // Call function to start blocking. 10212292SN/A block(tid); 10222292SN/A 10232292SN/A // Set unblock to false. Special case where we are using 10242292SN/A // skidbuffer (unblocking) instructions but then we still 10252292SN/A // get full in the IQ. 10262292SN/A toRename->iewUnblock[tid] = false; 10272292SN/A 10282292SN/A ++iewLSQFullEvents; 10292292SN/A break; 10302292SN/A } 10312292SN/A 10322292SN/A // Otherwise issue the instruction just fine. 10332292SN/A if (inst->isLoad()) { 10342292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10352292SN/A "encountered, adding to LSQ.\n", tid); 10362292SN/A 10372292SN/A // Reserve a spot in the load store queue for this 10382292SN/A // memory access. 10392292SN/A ldstQueue.insertLoad(inst); 10402292SN/A 10412292SN/A ++iewDispLoadInsts; 10422292SN/A 10432292SN/A add_to_iq = true; 10442292SN/A 10452292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10462292SN/A } else if (inst->isStore()) { 10472292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10482292SN/A "encountered, adding to LSQ.\n", tid); 10492292SN/A 10502292SN/A ldstQueue.insertStore(inst); 10512292SN/A 10522292SN/A ++iewDispStoreInsts; 10532292SN/A 10542292SN/A if (inst->isStoreConditional()) { 10552292SN/A // Store conditionals need to be set as "canCommit()" 10562292SN/A // so that commit can process them when they reach the 10572292SN/A // head of commit. 10582292SN/A // @todo: This is somewhat specific to Alpha. 10592292SN/A inst->setCanCommit(); 10602292SN/A instQueue.insertNonSpec(inst); 10612292SN/A add_to_iq = false; 10622292SN/A 10632292SN/A ++iewDispNonSpecInsts; 10642292SN/A } else { 10652336SN/A add_to_iq = true; 10662336SN/A } 10672336SN/A 10682336SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10692348SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10702292SN/A // Same as non-speculative stores. 10712292SN/A inst->setCanCommit(); 10722292SN/A instQueue.insertBarrier(inst); 10732292SN/A add_to_iq = false; 10742292SN/A } else if (inst->isNop()) { 10752292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10762292SN/A "skipping.\n", tid); 10772292SN/A 10782292SN/A inst->setIssued(); 10792292SN/A inst->setExecuted(); 10802292SN/A inst->setCanCommit(); 10812326SN/A 10822292SN/A instQueue.recordProducer(inst); 10832292SN/A 10842292SN/A iewExecutedNop[tid]++; 10852292SN/A 10862292SN/A add_to_iq = false; 10872292SN/A } else if (inst->isExecuted()) { 10882292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10892292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10902292SN/A "skipping.\n"); 10912292SN/A 10922292SN/A inst->setIssued(); 10932326SN/A inst->setCanCommit(); 10942292SN/A 10952727Sktlim@umich.edu instQueue.recordProducer(inst); 10962301SN/A 10972292SN/A add_to_iq = false; 10982292SN/A } else { 10992292SN/A add_to_iq = true; 11002292SN/A } 11012292SN/A if (inst->isNonSpeculative()) { 11022292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11032292SN/A "encountered, skipping.\n", tid); 11042292SN/A 11052292SN/A // Same as non-speculative stores. 11062326SN/A inst->setCanCommit(); 11072292SN/A 11082292SN/A // Specifically insert it as nonspeculative. 11092292SN/A instQueue.insertNonSpec(inst); 11102292SN/A 11112292SN/A ++iewDispNonSpecInsts; 11124033Sktlim@umich.edu 11134033Sktlim@umich.edu add_to_iq = false; 11144033Sktlim@umich.edu } 11154033Sktlim@umich.edu 11164033Sktlim@umich.edu // If the instruction queue is not full, then add the 11174033Sktlim@umich.edu // instruction. 11184033Sktlim@umich.edu if (add_to_iq) { 11194033Sktlim@umich.edu instQueue.insert(inst); 11204033Sktlim@umich.edu } 11214033Sktlim@umich.edu 11224033Sktlim@umich.edu insts_to_dispatch.pop(); 11234033Sktlim@umich.edu 11244033Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 11254033Sktlim@umich.edu 11262292SN/A ++iewDispatchedInsts; 11272292SN/A } 11282292SN/A 11292292SN/A if (!insts_to_dispatch.empty()) { 11302292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11312292SN/A block(tid); 11322292SN/A toRename->iewUnblock[tid] = false; 11332292SN/A } 11342292SN/A 11352292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11362292SN/A dispatchStatus[tid] = Running; 11372292SN/A 11382292SN/A updatedQueues = true; 11392292SN/A } 11402292SN/A 11412935Sksewell@umich.edu dis_num_inst = 0; 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Avoid 11462292SN/ADefaultIEW<Impl>::printAvailableInsts() 11472292SN/A{ 11482292SN/A int inst = 0; 11492292SN/A 11502292SN/A std::cout << "Available Instructions: "; 11512292SN/A 11522292SN/A while (fromIssue->insts[inst]) { 11532292SN/A 11542292SN/A if (inst%3==0) std::cout << "\n\t"; 11552292SN/A 11562292SN/A std::cout << "PC: " << fromIssue->insts[inst]->readPC() 11572292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11582292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11592292SN/A 11602292SN/A inst++; 11612980Sgblack@eecs.umich.edu 11622292SN/A } 11632292SN/A 11642292SN/A std::cout << "\n"; 11652980Sgblack@eecs.umich.edu} 11662292SN/A 11677720Sgblack@eecs.umich.edutemplate <class Impl> 11682292SN/Avoid 11692292SN/ADefaultIEW<Impl>::executeInsts() 11702292SN/A{ 11712292SN/A wbNumInst = 0; 11722292SN/A wbCycle = 0; 11732292SN/A 11742292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 11752980Sgblack@eecs.umich.edu list<ThreadID>::iterator end = activeThreads->end(); 11762292SN/A 11772292SN/A while (threads != end) { 11782292SN/A ThreadID tid = *threads++; 11792292SN/A fetchRedirect[tid] = false; 11802292SN/A } 11812292SN/A 11822292SN/A // Uncomment this if you want to see all available instructions. 11832292SN/A// printAvailableInsts(); 11842292SN/A 11856221Snate@binkert.org // Execute/writeback any instructions that are available. 11866221Snate@binkert.org int insts_to_execute = fromIssue->size; 11872292SN/A int inst_num = 0; 11883867Sbinkertn@umich.edu for (; inst_num < insts_to_execute; 11896221Snate@binkert.org ++inst_num) { 11902292SN/A 11912292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11922292SN/A 11932698Sktlim@umich.edu DynInstPtr inst = instQueue.getInstToExecute(); 11947599Sminkyu.jeong@arm.com 11952698Sktlim@umich.edu DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11961062SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11971062SN/A 11982333SN/A // Check if the instruction is squashed; if so then skip it 11992292SN/A if (inst->isSquashed()) { 12002333SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12012326SN/A 12021062SN/A // Consider this instruction executed so that commit can go 12032292SN/A // ahead and retire the instruction. 12041062SN/A inst->setExecuted(); 12052333SN/A 12061062SN/A // Not sure if I should set this here or just let commit try to 12077720Sgblack@eecs.umich.edu // commit any squashed instructions. I like the latter a bit more. 12087720Sgblack@eecs.umich.edu inst->setCanCommit(); 12091062SN/A 12101062SN/A ++iewExecSquashedInsts; 12111062SN/A 12122292SN/A decrWb(inst->seqNum); 12131062SN/A continue; 12141062SN/A } 12151062SN/A 12161062SN/A Fault fault = NoFault; 12171062SN/A 12182292SN/A // Execute instruction. 12192292SN/A // Note that if the instruction faults, it will be handled 12202292SN/A // at the commit stage. 12211062SN/A if (inst->isMemRef() && 12221062SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12231062SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12242820Sktlim@umich.edu "reference.\n"); 12251062SN/A 12261062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12271062SN/A if (inst->isLoad()) { 12282292SN/A // Loads will mark themselves as executed, and their writeback 12291062SN/A // event adds the instruction to the queue to commit 12301062SN/A fault = ldstQueue.executeLoad(inst); 12311062SN/A } else if (inst->isStore()) { 12321062SN/A fault = ldstQueue.executeStore(inst); 12337850SMatt.Horsnell@arm.com 12342292SN/A // If the store had a fault then it may not have a mem req 12351062SN/A if (!inst->isStoreConditional() && fault == NoFault) { 12361062SN/A inst->setExecuted(); 12371062SN/A 12381062SN/A instToCommit(inst); 12392292SN/A } else if (fault != NoFault) { 12402292SN/A // If the instruction faulted, then we need to send it along to commit 12412292SN/A // without the instruction completing. 12427944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 12437944SGiacomo.Gabrielli@arm.com fault->name(), inst->seqNum); 12447944SGiacomo.Gabrielli@arm.com 12457944SGiacomo.Gabrielli@arm.com // Send this instruction to commit, also make sure iew stage 12467944SGiacomo.Gabrielli@arm.com // realizes there is activity. 12477944SGiacomo.Gabrielli@arm.com inst->setExecuted(); 12487944SGiacomo.Gabrielli@arm.com 12497944SGiacomo.Gabrielli@arm.com instToCommit(inst); 12507944SGiacomo.Gabrielli@arm.com activityThisCycle(); 12517944SGiacomo.Gabrielli@arm.com } 12527944SGiacomo.Gabrielli@arm.com 12537850SMatt.Horsnell@arm.com // Store conditionals will mark themselves as 12548073SAli.Saidi@ARM.com // executed, and their writeback event will add the 12557850SMatt.Horsnell@arm.com // instruction to the queue to commit. 12561062SN/A } else { 12572367SN/A panic("Unexpected memory type!\n"); 12581062SN/A } 12597944SGiacomo.Gabrielli@arm.com 12607944SGiacomo.Gabrielli@arm.com } else { 12617944SGiacomo.Gabrielli@arm.com inst->execute(); 12627944SGiacomo.Gabrielli@arm.com 12637944SGiacomo.Gabrielli@arm.com inst->setExecuted(); 12647944SGiacomo.Gabrielli@arm.com 12657944SGiacomo.Gabrielli@arm.com instToCommit(inst); 12667944SGiacomo.Gabrielli@arm.com } 12677944SGiacomo.Gabrielli@arm.com 12687944SGiacomo.Gabrielli@arm.com updateExeInstStats(inst); 12692292SN/A 12707782Sminkyu.jeong@arm.com // Check if branch prediction was correct, if not then we need 12717782Sminkyu.jeong@arm.com // to tell commit to squash in flight instructions. Only 12727782Sminkyu.jeong@arm.com // handle this if there hasn't already been something that 12737782Sminkyu.jeong@arm.com // redirects fetch in this group of instructions. 12742367SN/A 12752367SN/A // This probably needs to prioritize the redirects if a different 12762367SN/A // scheduler is used. Currently the scheduler schedules the oldest 12772367SN/A // instruction first, so the branch resolution order will be correct. 12782367SN/A ThreadID tid = inst->threadNumber; 12792292SN/A 12802326SN/A if (!fetchRedirect[tid] || 12812326SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 12822326SN/A 12832326SN/A if (inst->mispredicted()) { 12841062SN/A fetchRedirect[tid] = true; 12852292SN/A 12861062SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12871062SN/A DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 12881062SN/A inst->readPredPC(), inst->readPredNPC()); 12897847Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 12907847Sminkyu.jeong@arm.com " NPC: %#x.\n", inst->readNextPC(), 12917847Sminkyu.jeong@arm.com inst->readNextNPC()); 12927847Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 12937847Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 12947847Sminkyu.jeong@arm.com 12957848SAli.Saidi@ARM.com if (inst->readPredTaken()) { 12967848SAli.Saidi@ARM.com predictedTakenIncorrect++; 12977847Sminkyu.jeong@arm.com } else { 12981062SN/A predictedNotTakenIncorrect++; 12992292SN/A } 13002292SN/A } else if (ldstQueue.violation(tid)) { 13012292SN/A assert(inst->isMemRef()); 13021062SN/A // If there was an ordering violation, then get the 13031062SN/A // DynInst that caused the violation. Note that this 13042301SN/A // clears the violation signal. 13051681SN/A DynInstPtr violator; 13062326SN/A violator = ldstQueue.getMemDepViolator(tid); 13072326SN/A 13082326SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13092107SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13101681SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13112292SN/A 13122292SN/A // Ensure the violating instruction is older than 13132292SN/A // current squash 13146221Snate@binkert.org/* if (fetchRedirect[tid] && 13151062SN/A violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 13163732Sktlim@umich.edu continue; 13177852SMatt.Horsnell@arm.com*/ 13183732Sktlim@umich.edu fetchRedirect[tid] = true; 13191062SN/A 13207856SMatt.Horsnell@arm.com // Tell the instruction queue that a violation has occured. 13217856SMatt.Horsnell@arm.com instQueue.violation(inst, violator); 13227856SMatt.Horsnell@arm.com 13237856SMatt.Horsnell@arm.com // Squash. 13247856SMatt.Horsnell@arm.com squashDueToMemOrder(inst,tid); 13252292SN/A 13261062SN/A ++memOrderViolationEvents; 13272292SN/A } else if (ldstQueue.loadBlocked(tid) && 13286036Sksewell@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13297720Sgblack@eecs.umich.edu fetchRedirect[tid] = true; 13307720Sgblack@eecs.umich.edu 13317720Sgblack@eecs.umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13321062SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13332292SN/A inst->readPC(), inst->seqNum); 13341062SN/A 13353795Sgblack@eecs.umich.edu squashDueToMemBlocked(inst, tid); 13361062SN/A } 13372292SN/A } else { 13382292SN/A // Reset any state associated with redirects that will not 13391062SN/A // be used. 13402292SN/A if (ldstQueue.violation(tid)) { 13414033Sktlim@umich.edu assert(inst->isMemRef()); 13422326SN/A 13432326SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13442292SN/A 13452292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13462292SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13471062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13487720Sgblack@eecs.umich.edu DPRINTF(IEW, "Violation will not be handled because " 13497720Sgblack@eecs.umich.edu "already squashing\n"); 13507720Sgblack@eecs.umich.edu 13517720Sgblack@eecs.umich.edu ++memOrderViolationEvents; 13527720Sgblack@eecs.umich.edu } 13533732Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 13543732Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13551062SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13561062SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13571062SN/A inst->readPC(), inst->seqNum); 13581062SN/A DPRINTF(IEW, "Blocked load will not be handled because " 13592292SN/A "already squashing\n"); 13601062SN/A 13611062SN/A ldstQueue.setLoadBlockedHandled(tid); 13622292SN/A } 13632292SN/A 13642292SN/A } 13652292SN/A } 13662292SN/A 13677720Sgblack@eecs.umich.edu // Update and record activity if we processed any instructions. 13687720Sgblack@eecs.umich.edu if (inst_num) { 13692292SN/A if (exeStatus == Idle) { 13702292SN/A exeStatus = Running; 13711062SN/A } 13724033Sktlim@umich.edu 13734033Sktlim@umich.edu updatedQueues = true; 13744033Sktlim@umich.edu 13754033Sktlim@umich.edu cpu->activityThisCycle(); 13764033Sktlim@umich.edu } 13774033Sktlim@umich.edu 13784033Sktlim@umich.edu // Need to reset this in case a writeback event needs to write into the 13794033Sktlim@umich.edu // iew queue. That way the writeback event will write into the correct 13804033Sktlim@umich.edu // spot in the queue. 13817720Sgblack@eecs.umich.edu wbNumInst = 0; 13827720Sgblack@eecs.umich.edu} 13837720Sgblack@eecs.umich.edu 13844033Sktlim@umich.edutemplate <class Impl> 13854033Sktlim@umich.eduvoid 13864033Sktlim@umich.eduDefaultIEW<Impl>::writebackInsts() 13874033Sktlim@umich.edu{ 13884033Sktlim@umich.edu // Loop through the head of the time buffer and wake any 13894033Sktlim@umich.edu // dependents. These instructions are about to write back. Also 13904033Sktlim@umich.edu // mark scoreboard that this instruction is finally complete. 13914033Sktlim@umich.edu // Either have IEW have direct access to scoreboard, or have this 13927720Sgblack@eecs.umich.edu // as part of backwards communication. 13937720Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 13944033Sktlim@umich.edu toCommit->insts[inst_num]; inst_num++) { 13954033Sktlim@umich.edu DynInstPtr inst = toCommit->insts[inst_num]; 13964033Sktlim@umich.edu ThreadID tid = inst->threadNumber; 13974033Sktlim@umich.edu 13984033Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13994033Sktlim@umich.edu inst->seqNum, inst->readPC()); 14001062SN/A 14011062SN/A iewInstsToCommit[tid]++; 14022292SN/A 14032348SN/A // Some instructions will be sent to commit without having 14042292SN/A // executed because they need commit to handle them. 14052292SN/A // E.g. Uncached loads have not actually executed when they 14062292SN/A // are first sent to commit. Instead commit must tell the LSQ 14072292SN/A // when it's ready to execute the uncached load. 14082292SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14092292SN/A int dependents = instQueue.wakeDependents(inst); 14102292SN/A 14112292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14122292SN/A //mark as Ready 14132292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14142292SN/A inst->renamedDestRegIdx(i)); 14152292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14162292SN/A } 14172292SN/A 14187852SMatt.Horsnell@arm.com if (dependents) { 14192107SN/A producerInst[tid]++; 14202107SN/A consumerInst[tid]+= dependents; 14212292SN/A } 14222107SN/A writebackCount[tid]++; 14232292SN/A } 14242107SN/A 14252326SN/A decrWb(inst->seqNum); 14262326SN/A } 14272326SN/A} 14282326SN/A 14292326SN/Atemplate<class Impl> 14303958Sgblack@eecs.umich.eduvoid 14312292SN/ADefaultIEW<Impl>::tick() 14322107SN/A{ 14336221Snate@binkert.org wbNumInst = 0; 14342107SN/A wbCycle = 0; 14357720Sgblack@eecs.umich.edu 14367720Sgblack@eecs.umich.edu wroteToTimeBuffer = false; 14372107SN/A updatedQueues = false; 14382301SN/A 14392301SN/A sortInsts(); 14402292SN/A 14412292SN/A // Free function units marked as being freed this cycle. 14422292SN/A fuPool->processFreeUnits(); 14432292SN/A 14442292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 14452367SN/A list<ThreadID>::iterator end = activeThreads->end(); 14462301SN/A 14472107SN/A // Check stall and squash signals, dispatch any instructions. 14482292SN/A while (threads != end) { 14492292SN/A ThreadID tid = *threads++; 14502292SN/A 14512292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14522292SN/A 14532107SN/A checkSignalsAndUpdate(tid); 14542301SN/A dispatch(tid); 14552348SN/A } 14562348SN/A 14572348SN/A if (exeStatus != Squashing) { 14582348SN/A executeInsts(); 14592326SN/A 14602107SN/A writebackInsts(); 14612820Sktlim@umich.edu 14622820Sktlim@umich.edu // Have the instruction queue try to schedule any ready instructions. 14632107SN/A // (In actuality, this scheduling is for instructions that will 14641060SN/A // be executed next cycle.) 14651060SN/A instQueue.scheduleReadyInsts(); 14661681SN/A 14671060SN/A // Also should advance its own time buffers if the stage ran. 14682292SN/A // Not the best place for it, but this works (hopefully). 14691060SN/A issueToExecQueue.advance(); 14702292SN/A } 14712292SN/A 14721060SN/A bool broadcast_free_entries = false; 14732292SN/A 14742292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14751060SN/A exeStatus = Idle; 14762292SN/A updateLSQNextCycle = false; 14771060SN/A 14782326SN/A broadcast_free_entries = true; 14792326SN/A } 14801062SN/A 14816221Snate@binkert.org // Writeback any stores using any leftover bandwidth. 14826221Snate@binkert.org ldstQueue.writebackStores(); 14831060SN/A 14842326SN/A // Check the committed load/store signals to see if there's a load 14853867Sbinkertn@umich.edu // or store to commit. Also check if it's being told to execute a 14866221Snate@binkert.org // nonspeculative instruction. 14871060SN/A // This is pretty inefficient... 14882292SN/A 14891060SN/A threads = activeThreads->begin(); 14902292SN/A while (threads != end) { 14912292SN/A ThreadID tid = (*threads++); 14921060SN/A 14931060SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14942292SN/A 14952292SN/A // Update structures based on instructions committed. 14961060SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14972292SN/A !fromCommit->commitInfo[tid].squash && 14982292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14992292SN/A 15002292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15012292SN/A 15022292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15032292SN/A 15042292SN/A updateLSQNextCycle = true; 15052292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15062292SN/A } 15072292SN/A 15082292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15092292SN/A 15102292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15112292SN/A if (fromCommit->commitInfo[tid].uncached) { 15122292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15132292SN/A fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15142292SN/A } else { 15152292SN/A instQueue.scheduleNonSpec( 15162292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15172292SN/A } 15182292SN/A } 15191681SN/A 15201681SN/A if (broadcast_free_entries) { 15211061SN/A toFetch->iewInfo[tid].iqCount = 15221061SN/A instQueue.getCount(tid); 15231061SN/A toFetch->iewInfo[tid].ldstqCount = 15241681SN/A ldstQueue.getCount(tid); 15252292SN/A 15263867Sbinkertn@umich.edu toRename->iewInfo[tid].usedIQ = true; 15273867Sbinkertn@umich.edu toRename->iewInfo[tid].freeIQEntries = 15286221Snate@binkert.org instQueue.numFreeEntries(); 15292292SN/A toRename->iewInfo[tid].usedLSQ = true; 15302292SN/A toRename->iewInfo[tid].freeLSQEntries = 15312292SN/A ldstQueue.numFreeEntries(tid); 15322348SN/A 15332292SN/A wroteToTimeBuffer = true; 15342292SN/A } 15352292SN/A 15362292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15372292SN/A tid, toRename->iewInfo[tid].dispatched); 15382292SN/A } 15392292SN/A 15402292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15412292SN/A "LSQ has %i free entries.\n", 15422292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15432292SN/A ldstQueue.numFreeEntries()); 15442292SN/A 15452292SN/A updateStatus(); 15462292SN/A 15472292SN/A if (wroteToTimeBuffer) { 15482292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15492292SN/A cpu->activityThisCycle(); 15504033Sktlim@umich.edu } 15512292SN/A} 15522292SN/A 15532292SN/Atemplate <class Impl> 15542292SN/Avoid 15552292SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15562292SN/A{ 15572292SN/A ThreadID tid = inst->threadNumber; 15582292SN/A 15592292SN/A // 15602292SN/A // Pick off the software prefetches 15612292SN/A // 15622292SN/A#ifdef TARGET_ALPHA 15632292SN/A if (inst->isDataPrefetch()) 15642292SN/A iewExecutedSwp[tid]++; 15652292SN/A else 15662292SN/A iewIewExecutedcutedInsts++; 15672292SN/A#else 15682292SN/A iewExecutedInsts++; 15692292SN/A#endif 15702292SN/A 15712292SN/A // 15722292SN/A // Control operations 15732292SN/A // 15742292SN/A if (inst->isControl()) 15751061SN/A iewExecutedBranches[tid]++; 15761061SN/A 15772292SN/A // 15782292SN/A // Memory operations 15792292SN/A // 15802292SN/A if (inst->isMemRef()) { 15812292SN/A iewExecutedRefs[tid]++; 15822292SN/A 15832292SN/A if (inst->isLoad()) { 15842292SN/A iewExecLoadInsts[tid]++; 15852292SN/A } 15862292SN/A } 15871061SN/A} 15881060SN/A