iew_impl.hh revision 2698
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 412292SN/Ausing namespace std; 421681SN/A 431681SN/Atemplate<class Impl> 442292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params) 452326SN/A : // @todo: Make this into a parameter. 461061SN/A issueToExecQueue(5, 5), 471060SN/A instQueue(params), 481061SN/A ldstQueue(params), 492292SN/A fuPool(params->fuPool), 502292SN/A commitToIEWDelay(params->commitToIEWDelay), 512292SN/A renameToIEWDelay(params->renameToIEWDelay), 522292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 532292SN/A issueReadWidth(params->issueWidth), 542292SN/A issueWidth(params->issueWidth), 552292SN/A executeWidth(params->executeWidth), 562307SN/A numThreads(params->numberOfThreads), 572307SN/A switchedOut(false) 581060SN/A{ 592292SN/A _status = Active; 602292SN/A exeStatus = Running; 612292SN/A wbStatus = Idle; 621060SN/A 631060SN/A // Setup wire to read instructions coming from issue. 641060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 651060SN/A 661060SN/A // Instruction queue needs the queue between issue and execute. 671060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 681681SN/A 692292SN/A instQueue.setIEW(this); 701681SN/A ldstQueue.setIEW(this); 712292SN/A 722292SN/A for (int i=0; i < numThreads; i++) { 732292SN/A dispatchStatus[i] = Running; 742292SN/A stalls[i].commit = false; 752292SN/A fetchRedirect[i] = false; 762292SN/A } 772292SN/A 782292SN/A updateLSQNextCycle = false; 792292SN/A 802292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 842292SN/Astd::string 852292SN/ADefaultIEW<Impl>::name() const 862292SN/A{ 872292SN/A return cpu->name() + ".iew"; 881060SN/A} 891060SN/A 901681SN/Atemplate <class Impl> 911062SN/Avoid 922292SN/ADefaultIEW<Impl>::regStats() 931062SN/A{ 942301SN/A using namespace Stats; 952301SN/A 961062SN/A instQueue.regStats(); 971062SN/A 981062SN/A iewIdleCycles 991062SN/A .name(name() + ".iewIdleCycles") 1001062SN/A .desc("Number of cycles IEW is idle"); 1011062SN/A 1021062SN/A iewSquashCycles 1031062SN/A .name(name() + ".iewSquashCycles") 1041062SN/A .desc("Number of cycles IEW is squashing"); 1051062SN/A 1061062SN/A iewBlockCycles 1071062SN/A .name(name() + ".iewBlockCycles") 1081062SN/A .desc("Number of cycles IEW is blocking"); 1091062SN/A 1101062SN/A iewUnblockCycles 1111062SN/A .name(name() + ".iewUnblockCycles") 1121062SN/A .desc("Number of cycles IEW is unblocking"); 1131062SN/A 1141062SN/A iewDispatchedInsts 1151062SN/A .name(name() + ".iewDispatchedInsts") 1161062SN/A .desc("Number of instructions dispatched to IQ"); 1171062SN/A 1181062SN/A iewDispSquashedInsts 1191062SN/A .name(name() + ".iewDispSquashedInsts") 1201062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1211062SN/A 1221062SN/A iewDispLoadInsts 1231062SN/A .name(name() + ".iewDispLoadInsts") 1241062SN/A .desc("Number of dispatched load instructions"); 1251062SN/A 1261062SN/A iewDispStoreInsts 1271062SN/A .name(name() + ".iewDispStoreInsts") 1281062SN/A .desc("Number of dispatched store instructions"); 1291062SN/A 1301062SN/A iewDispNonSpecInsts 1311062SN/A .name(name() + ".iewDispNonSpecInsts") 1321062SN/A .desc("Number of dispatched non-speculative instructions"); 1331062SN/A 1341062SN/A iewIQFullEvents 1351062SN/A .name(name() + ".iewIQFullEvents") 1361062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1371062SN/A 1382292SN/A iewLSQFullEvents 1392292SN/A .name(name() + ".iewLSQFullEvents") 1402292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1412292SN/A 1421062SN/A iewExecutedInsts 1431062SN/A .name(name() + ".iewExecutedInsts") 1441062SN/A .desc("Number of executed instructions"); 1451062SN/A 1461062SN/A iewExecLoadInsts 1472301SN/A .init(cpu->number_of_threads) 1481062SN/A .name(name() + ".iewExecLoadInsts") 1492301SN/A .desc("Number of load instructions executed") 1502301SN/A .flags(total); 1511062SN/A 1521062SN/A iewExecSquashedInsts 1531062SN/A .name(name() + ".iewExecSquashedInsts") 1541062SN/A .desc("Number of squashed instructions skipped in execute"); 1551062SN/A 1561062SN/A memOrderViolationEvents 1571062SN/A .name(name() + ".memOrderViolationEvents") 1581062SN/A .desc("Number of memory order violations"); 1591062SN/A 1601062SN/A predictedTakenIncorrect 1611062SN/A .name(name() + ".predictedTakenIncorrect") 1621062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1632292SN/A 1642292SN/A predictedNotTakenIncorrect 1652292SN/A .name(name() + ".predictedNotTakenIncorrect") 1662292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1672292SN/A 1682292SN/A branchMispredicts 1692292SN/A .name(name() + ".branchMispredicts") 1702292SN/A .desc("Number of branch mispredicts detected at execute"); 1712292SN/A 1722292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1732301SN/A 1742326SN/A exeSwp 1752301SN/A .init(cpu->number_of_threads) 1762301SN/A .name(name() + ".EXEC:swp") 1772301SN/A .desc("number of swp insts executed") 1782301SN/A .flags(total) 1792301SN/A ; 1802301SN/A 1812326SN/A exeNop 1822301SN/A .init(cpu->number_of_threads) 1832301SN/A .name(name() + ".EXEC:nop") 1842301SN/A .desc("number of nop insts executed") 1852301SN/A .flags(total) 1862301SN/A ; 1872301SN/A 1882326SN/A exeRefs 1892301SN/A .init(cpu->number_of_threads) 1902301SN/A .name(name() + ".EXEC:refs") 1912301SN/A .desc("number of memory reference insts executed") 1922301SN/A .flags(total) 1932301SN/A ; 1942301SN/A 1952326SN/A exeBranches 1962301SN/A .init(cpu->number_of_threads) 1972301SN/A .name(name() + ".EXEC:branches") 1982301SN/A .desc("Number of branches executed") 1992301SN/A .flags(total) 2002301SN/A ; 2012301SN/A 2022326SN/A issueRate 2032301SN/A .name(name() + ".EXEC:rate") 2042301SN/A .desc("Inst execution rate") 2052301SN/A .flags(total) 2062301SN/A ; 2072326SN/A issueRate = iewExecutedInsts / cpu->numCycles; 2082301SN/A 2092301SN/A iewExecStoreInsts 2102301SN/A .name(name() + ".EXEC:stores") 2112301SN/A .desc("Number of stores executed") 2122301SN/A .flags(total) 2132301SN/A ; 2142326SN/A iewExecStoreInsts = exeRefs - iewExecLoadInsts; 2152301SN/A/* 2162301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2172301SN/A stringstream subname; 2182301SN/A subname << opClassStrings[i] << "_delay"; 2192301SN/A issue_delay_dist.subname(i, subname.str()); 2202301SN/A } 2212301SN/A*/ 2222301SN/A // 2232301SN/A // Other stats 2242301SN/A // 2252301SN/A 2262301SN/A iewInstsToCommit 2272301SN/A .init(cpu->number_of_threads) 2282301SN/A .name(name() + ".WB:sent") 2292301SN/A .desc("cumulative count of insts sent to commit") 2302301SN/A .flags(total) 2312301SN/A ; 2322301SN/A 2332326SN/A writebackCount 2342301SN/A .init(cpu->number_of_threads) 2352301SN/A .name(name() + ".WB:count") 2362301SN/A .desc("cumulative count of insts written-back") 2372301SN/A .flags(total) 2382301SN/A ; 2392301SN/A 2402326SN/A producerInst 2412301SN/A .init(cpu->number_of_threads) 2422301SN/A .name(name() + ".WB:producers") 2432301SN/A .desc("num instructions producing a value") 2442301SN/A .flags(total) 2452301SN/A ; 2462301SN/A 2472326SN/A consumerInst 2482301SN/A .init(cpu->number_of_threads) 2492301SN/A .name(name() + ".WB:consumers") 2502301SN/A .desc("num instructions consuming a value") 2512301SN/A .flags(total) 2522301SN/A ; 2532301SN/A 2542326SN/A wbPenalized 2552301SN/A .init(cpu->number_of_threads) 2562301SN/A .name(name() + ".WB:penalized") 2572301SN/A .desc("number of instrctions required to write to 'other' IQ") 2582301SN/A .flags(total) 2592301SN/A ; 2602301SN/A 2612326SN/A wbPenalizedRate 2622301SN/A .name(name() + ".WB:penalized_rate") 2632301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2642301SN/A .flags(total) 2652301SN/A ; 2662301SN/A 2672326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2682301SN/A 2692326SN/A wbFanout 2702301SN/A .name(name() + ".WB:fanout") 2712301SN/A .desc("average fanout of values written-back") 2722301SN/A .flags(total) 2732301SN/A ; 2742301SN/A 2752326SN/A wbFanout = producerInst / consumerInst; 2762301SN/A 2772326SN/A wbRate 2782301SN/A .name(name() + ".WB:rate") 2792301SN/A .desc("insts written-back per cycle") 2802301SN/A .flags(total) 2812301SN/A ; 2822326SN/A wbRate = writebackCount / cpu->numCycles; 2831062SN/A} 2841062SN/A 2851681SN/Atemplate<class Impl> 2861060SN/Avoid 2872292SN/ADefaultIEW<Impl>::initStage() 2881060SN/A{ 2892292SN/A for (int tid=0; tid < numThreads; tid++) { 2902292SN/A toRename->iewInfo[tid].usedIQ = true; 2912292SN/A toRename->iewInfo[tid].freeIQEntries = 2922292SN/A instQueue.numFreeEntries(tid); 2932292SN/A 2942292SN/A toRename->iewInfo[tid].usedLSQ = true; 2952292SN/A toRename->iewInfo[tid].freeLSQEntries = 2962292SN/A ldstQueue.numFreeEntries(tid); 2972292SN/A } 2982292SN/A} 2992292SN/A 3002292SN/Atemplate<class Impl> 3012292SN/Avoid 3022292SN/ADefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 3032292SN/A{ 3042292SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 3051060SN/A cpu = cpu_ptr; 3061060SN/A 3071060SN/A instQueue.setCPU(cpu_ptr); 3081061SN/A ldstQueue.setCPU(cpu_ptr); 3092292SN/A 3102292SN/A cpu->activateStage(FullCPU::IEWIdx); 3111060SN/A} 3121060SN/A 3131681SN/Atemplate<class Impl> 3141060SN/Avoid 3152292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3161060SN/A{ 3172292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3181060SN/A timeBuffer = tb_ptr; 3191060SN/A 3201060SN/A // Setup wire to read information from time buffer, from commit. 3211060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3221060SN/A 3231060SN/A // Setup wire to write information back to previous stages. 3241060SN/A toRename = timeBuffer->getWire(0); 3251060SN/A 3262292SN/A toFetch = timeBuffer->getWire(0); 3272292SN/A 3281060SN/A // Instruction queue also needs main time buffer. 3291060SN/A instQueue.setTimeBuffer(tb_ptr); 3301060SN/A} 3311060SN/A 3321681SN/Atemplate<class Impl> 3331060SN/Avoid 3342292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3351060SN/A{ 3362292SN/A DPRINTF(IEW, "Setting rename queue pointer.\n"); 3371060SN/A renameQueue = rq_ptr; 3381060SN/A 3391060SN/A // Setup wire to read information from rename queue. 3401060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3411060SN/A} 3421060SN/A 3431681SN/Atemplate<class Impl> 3441060SN/Avoid 3452292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3461060SN/A{ 3472292SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3481060SN/A iewQueue = iq_ptr; 3491060SN/A 3501060SN/A // Setup wire to write instructions to commit. 3511060SN/A toCommit = iewQueue->getWire(0); 3521060SN/A} 3531060SN/A 3541681SN/Atemplate<class Impl> 3551060SN/Avoid 3562292SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3571060SN/A{ 3582292SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 3592292SN/A activeThreads = at_ptr; 3602292SN/A 3612292SN/A ldstQueue.setActiveThreads(at_ptr); 3622292SN/A instQueue.setActiveThreads(at_ptr); 3631060SN/A} 3641060SN/A 3651681SN/Atemplate<class Impl> 3661060SN/Avoid 3672292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3681060SN/A{ 3692292SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 3702292SN/A scoreboard = sb_ptr; 3711060SN/A} 3721060SN/A 3732307SN/Atemplate <class Impl> 3742307SN/Avoid 3752307SN/ADefaultIEW<Impl>::switchOut() 3762307SN/A{ 3772348SN/A // IEW is ready to switch out at any time. 3782316SN/A cpu->signalSwitched(); 3791681SN/A} 3801681SN/A 3812316SN/Atemplate <class Impl> 3821681SN/Avoid 3832316SN/ADefaultIEW<Impl>::doSwitchOut() 3841681SN/A{ 3852348SN/A // Clear any state. 3862307SN/A switchedOut = true; 3871681SN/A 3882307SN/A instQueue.switchOut(); 3892307SN/A ldstQueue.switchOut(); 3902307SN/A fuPool->switchOut(); 3912307SN/A 3922307SN/A for (int i = 0; i < numThreads; i++) { 3932307SN/A while (!insts[i].empty()) 3942307SN/A insts[i].pop(); 3952307SN/A while (!skidBuffer[i].empty()) 3962307SN/A skidBuffer[i].pop(); 3972307SN/A } 3981681SN/A} 3991681SN/A 4002307SN/Atemplate <class Impl> 4011681SN/Avoid 4022307SN/ADefaultIEW<Impl>::takeOverFrom() 4031060SN/A{ 4042348SN/A // Reset all state. 4052307SN/A _status = Active; 4062307SN/A exeStatus = Running; 4072307SN/A wbStatus = Idle; 4082307SN/A switchedOut = false; 4091060SN/A 4102307SN/A instQueue.takeOverFrom(); 4112307SN/A ldstQueue.takeOverFrom(); 4122307SN/A fuPool->takeOverFrom(); 4131060SN/A 4142307SN/A initStage(); 4152307SN/A cpu->activityThisCycle(); 4161060SN/A 4172307SN/A for (int i=0; i < numThreads; i++) { 4182307SN/A dispatchStatus[i] = Running; 4192307SN/A stalls[i].commit = false; 4202307SN/A fetchRedirect[i] = false; 4212307SN/A } 4221060SN/A 4232307SN/A updateLSQNextCycle = false; 4242307SN/A 4252307SN/A // @todo: Fix hardcoded number 4262307SN/A for (int i = 0; i < 6; ++i) { 4272307SN/A issueToExecQueue.advance(); 4281060SN/A } 4291060SN/A} 4301060SN/A 4311681SN/Atemplate<class Impl> 4321060SN/Avoid 4332292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4342107SN/A{ 4352292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4362292SN/A tid); 4372107SN/A 4382292SN/A // Tell the IQ to start squashing. 4392292SN/A instQueue.squash(tid); 4402107SN/A 4412292SN/A // Tell the LDSTQ to start squashing. 4422326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4432107SN/A 4442292SN/A updatedQueues = true; 4452107SN/A 4462292SN/A // Clear the skid buffer in case it has any data in it. 4472292SN/A while (!skidBuffer[tid].empty()) { 4482107SN/A 4492292SN/A if (skidBuffer[tid].front()->isLoad() || 4502292SN/A skidBuffer[tid].front()->isStore() ) { 4512292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4522292SN/A } 4532107SN/A 4542292SN/A toRename->iewInfo[tid].dispatched++; 4552107SN/A 4562292SN/A skidBuffer[tid].pop(); 4572292SN/A } 4582107SN/A 4592292SN/A while (!insts[tid].empty()) { 4602292SN/A if (insts[tid].front()->isLoad() || 4612292SN/A insts[tid].front()->isStore() ) { 4622292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4632292SN/A } 4642292SN/A 4652292SN/A toRename->iewInfo[tid].dispatched++; 4662292SN/A 4672292SN/A insts[tid].pop(); 4682107SN/A } 4692107SN/A} 4702107SN/A 4712107SN/Atemplate<class Impl> 4722107SN/Avoid 4732292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4742292SN/A{ 4752292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4762292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4772292SN/A 4782292SN/A toCommit->squash[tid] = true; 4792292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4802292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4812292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4822292SN/A toCommit->branchMispredict[tid] = true; 4832292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 4842292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 4852292SN/A 4862292SN/A toCommit->includeSquashInst[tid] = false; 4872292SN/A 4882292SN/A wroteToTimeBuffer = true; 4892292SN/A} 4902292SN/A 4912292SN/Atemplate<class Impl> 4922292SN/Avoid 4932292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4942292SN/A{ 4952292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4962292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4972292SN/A 4982292SN/A toCommit->squash[tid] = true; 4992292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5002292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5012292SN/A 5022292SN/A toCommit->includeSquashInst[tid] = false; 5032292SN/A 5042292SN/A wroteToTimeBuffer = true; 5052292SN/A} 5062292SN/A 5072292SN/Atemplate<class Impl> 5082292SN/Avoid 5092292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5102292SN/A{ 5112292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5122292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5132292SN/A 5142292SN/A toCommit->squash[tid] = true; 5152292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5162292SN/A toCommit->nextPC[tid] = inst->readPC(); 5172292SN/A 5182348SN/A // Must include the broadcasted SN in the squash. 5192292SN/A toCommit->includeSquashInst[tid] = true; 5202292SN/A 5212292SN/A ldstQueue.setLoadBlockedHandled(tid); 5222292SN/A 5232292SN/A wroteToTimeBuffer = true; 5242292SN/A} 5252292SN/A 5262292SN/Atemplate<class Impl> 5272292SN/Avoid 5282292SN/ADefaultIEW<Impl>::block(unsigned tid) 5292292SN/A{ 5302292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5312292SN/A 5322292SN/A if (dispatchStatus[tid] != Blocked && 5332292SN/A dispatchStatus[tid] != Unblocking) { 5342292SN/A toRename->iewBlock[tid] = true; 5352292SN/A wroteToTimeBuffer = true; 5362292SN/A } 5372292SN/A 5382292SN/A // Add the current inputs to the skid buffer so they can be 5392292SN/A // reprocessed when this stage unblocks. 5402292SN/A skidInsert(tid); 5412292SN/A 5422292SN/A dispatchStatus[tid] = Blocked; 5432292SN/A} 5442292SN/A 5452292SN/Atemplate<class Impl> 5462292SN/Avoid 5472292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5482292SN/A{ 5492292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5502292SN/A "buffer %u.\n",tid, tid); 5512292SN/A 5522292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5532292SN/A // Also switch status to running. 5542292SN/A if (skidBuffer[tid].empty()) { 5552292SN/A toRename->iewUnblock[tid] = true; 5562292SN/A wroteToTimeBuffer = true; 5572292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5582292SN/A dispatchStatus[tid] = Running; 5592292SN/A } 5602292SN/A} 5612292SN/A 5622292SN/Atemplate<class Impl> 5632292SN/Avoid 5642292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5651060SN/A{ 5661681SN/A instQueue.wakeDependents(inst); 5671060SN/A} 5681060SN/A 5692292SN/Atemplate<class Impl> 5702292SN/Avoid 5712292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5722292SN/A{ 5732292SN/A instQueue.rescheduleMemInst(inst); 5742292SN/A} 5751681SN/A 5761681SN/Atemplate<class Impl> 5771060SN/Avoid 5782292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5791060SN/A{ 5802292SN/A instQueue.replayMemInst(inst); 5812292SN/A} 5821060SN/A 5832292SN/Atemplate<class Impl> 5842292SN/Avoid 5852292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5862292SN/A{ 5872292SN/A // First check the time slot that this instruction will write 5882292SN/A // to. If there are free write ports at the time, then go ahead 5892292SN/A // and write the instruction to that time. If there are not, 5902292SN/A // keep looking back to see where's the first time there's a 5912326SN/A // free slot. 5922292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5932292SN/A ++wbNumInst; 5942292SN/A if (wbNumInst == issueWidth) { 5952292SN/A ++wbCycle; 5962292SN/A wbNumInst = 0; 5972292SN/A } 5982292SN/A 5992292SN/A assert(wbCycle < 5); 6002292SN/A } 6012292SN/A 6022292SN/A // Add finished instruction to queue to commit. 6032292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6042292SN/A (*iewQueue)[wbCycle].size++; 6052292SN/A} 6062292SN/A 6072292SN/Atemplate <class Impl> 6082292SN/Aunsigned 6092292SN/ADefaultIEW<Impl>::validInstsFromRename() 6102292SN/A{ 6112292SN/A unsigned inst_count = 0; 6122292SN/A 6132292SN/A for (int i=0; i<fromRename->size; i++) { 6142292SN/A if (!fromRename->insts[i]->squashed) 6152292SN/A inst_count++; 6162292SN/A } 6172292SN/A 6182292SN/A return inst_count; 6192292SN/A} 6202292SN/A 6212292SN/Atemplate<class Impl> 6222292SN/Avoid 6232292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6242292SN/A{ 6252292SN/A DynInstPtr inst = NULL; 6262292SN/A 6272292SN/A while (!insts[tid].empty()) { 6282292SN/A inst = insts[tid].front(); 6292292SN/A 6302292SN/A insts[tid].pop(); 6312292SN/A 6322292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6332292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6342292SN/A inst->readPC(),tid); 6352292SN/A 6362292SN/A skidBuffer[tid].push(inst); 6372292SN/A } 6382292SN/A 6392292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6402292SN/A "Skidbuffer Exceeded Max Size"); 6412292SN/A} 6422292SN/A 6432292SN/Atemplate<class Impl> 6442292SN/Aint 6452292SN/ADefaultIEW<Impl>::skidCount() 6462292SN/A{ 6472292SN/A int max=0; 6482292SN/A 6492292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6502292SN/A 6512292SN/A while (threads != (*activeThreads).end()) { 6522292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 6532292SN/A if (max < thread_count) 6542292SN/A max = thread_count; 6552292SN/A } 6562292SN/A 6572292SN/A return max; 6582292SN/A} 6592292SN/A 6602292SN/Atemplate<class Impl> 6612292SN/Abool 6622292SN/ADefaultIEW<Impl>::skidsEmpty() 6632292SN/A{ 6642292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6652292SN/A 6662292SN/A while (threads != (*activeThreads).end()) { 6672292SN/A if (!skidBuffer[*threads++].empty()) 6682292SN/A return false; 6692292SN/A } 6702292SN/A 6712292SN/A return true; 6721062SN/A} 6731062SN/A 6741681SN/Atemplate <class Impl> 6751062SN/Avoid 6762292SN/ADefaultIEW<Impl>::updateStatus() 6771062SN/A{ 6782292SN/A bool any_unblocking = false; 6791062SN/A 6802292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 6811062SN/A 6822292SN/A threads = (*activeThreads).begin(); 6831062SN/A 6842292SN/A while (threads != (*activeThreads).end()) { 6852292SN/A unsigned tid = *threads++; 6861062SN/A 6872292SN/A if (dispatchStatus[tid] == Unblocking) { 6882292SN/A any_unblocking = true; 6892292SN/A break; 6902292SN/A } 6912292SN/A } 6921062SN/A 6932292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6942292SN/A // and there's no stores waiting to write back, and dispatch is not 6952292SN/A // unblocking, then there is no internal activity for the IEW stage. 6962292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6972292SN/A !ldstQueue.willWB() && !any_unblocking) { 6982292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6991062SN/A 7002292SN/A deactivateStage(); 7011062SN/A 7022292SN/A _status = Inactive; 7032292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7042292SN/A ldstQueue.willWB() || 7052292SN/A any_unblocking)) { 7062292SN/A // Otherwise there is internal activity. Set to active. 7072292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7081062SN/A 7092292SN/A activateStage(); 7101062SN/A 7112292SN/A _status = Active; 7121062SN/A } 7131062SN/A} 7141062SN/A 7151681SN/Atemplate <class Impl> 7161062SN/Avoid 7172292SN/ADefaultIEW<Impl>::resetEntries() 7181062SN/A{ 7192292SN/A instQueue.resetEntries(); 7202292SN/A ldstQueue.resetEntries(); 7212292SN/A} 7221062SN/A 7232292SN/Atemplate <class Impl> 7242292SN/Avoid 7252292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7262292SN/A{ 7272292SN/A if (fromCommit->commitBlock[tid]) { 7282292SN/A stalls[tid].commit = true; 7292292SN/A } 7301062SN/A 7312292SN/A if (fromCommit->commitUnblock[tid]) { 7322292SN/A assert(stalls[tid].commit); 7332292SN/A stalls[tid].commit = false; 7342292SN/A } 7352292SN/A} 7362292SN/A 7372292SN/Atemplate <class Impl> 7382292SN/Abool 7392292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7402292SN/A{ 7412292SN/A bool ret_val(false); 7422292SN/A 7432292SN/A if (stalls[tid].commit) { 7442292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7452292SN/A ret_val = true; 7462292SN/A } else if (instQueue.isFull(tid)) { 7472292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7482292SN/A ret_val = true; 7492292SN/A } else if (ldstQueue.isFull(tid)) { 7502292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7512292SN/A 7522292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7532292SN/A 7542292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7552292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7562292SN/A } 7572292SN/A 7582292SN/A if (ldstQueue.numStores(tid) > 0) { 7592292SN/A 7602292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7612292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7622292SN/A } 7632292SN/A 7642292SN/A ret_val = true; 7652292SN/A } else if (ldstQueue.isStalled(tid)) { 7662292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7672292SN/A ret_val = true; 7682292SN/A } 7692292SN/A 7702292SN/A return ret_val; 7712292SN/A} 7722292SN/A 7732292SN/Atemplate <class Impl> 7742292SN/Avoid 7752292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7762292SN/A{ 7772292SN/A // Check if there's a squash signal, squash if there is 7782292SN/A // Check stall signals, block if there is. 7792292SN/A // If status was Blocked 7802292SN/A // if so then go to unblocking 7812292SN/A // If status was Squashing 7822292SN/A // check if squashing is not high. Switch to running this cycle. 7832292SN/A 7842292SN/A readStallSignals(tid); 7852292SN/A 7862292SN/A if (fromCommit->commitInfo[tid].squash) { 7872292SN/A squash(tid); 7882292SN/A 7892292SN/A if (dispatchStatus[tid] == Blocked || 7902292SN/A dispatchStatus[tid] == Unblocking) { 7912292SN/A toRename->iewUnblock[tid] = true; 7922292SN/A wroteToTimeBuffer = true; 7932292SN/A } 7942292SN/A 7952292SN/A dispatchStatus[tid] = Squashing; 7962292SN/A 7972292SN/A fetchRedirect[tid] = false; 7982292SN/A return; 7992292SN/A } 8002292SN/A 8012292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8022292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); 8032292SN/A 8042292SN/A dispatchStatus[tid] = Squashing; 8052292SN/A 8062292SN/A return; 8072292SN/A } 8082292SN/A 8092292SN/A if (checkStall(tid)) { 8102292SN/A block(tid); 8112292SN/A dispatchStatus[tid] = Blocked; 8122292SN/A return; 8132292SN/A } 8142292SN/A 8152292SN/A if (dispatchStatus[tid] == Blocked) { 8162292SN/A // Status from previous cycle was blocked, but there are no more stall 8172292SN/A // conditions. Switch over to unblocking. 8182292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8192292SN/A tid); 8202292SN/A 8212292SN/A dispatchStatus[tid] = Unblocking; 8222292SN/A 8232292SN/A unblock(tid); 8242292SN/A 8252292SN/A return; 8262292SN/A } 8272292SN/A 8282292SN/A if (dispatchStatus[tid] == Squashing) { 8292292SN/A // Switch status to running if rename isn't being told to block or 8302292SN/A // squash this cycle. 8312292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8322292SN/A tid); 8332292SN/A 8342292SN/A dispatchStatus[tid] = Running; 8352292SN/A 8362292SN/A return; 8372292SN/A } 8382292SN/A} 8392292SN/A 8402292SN/Atemplate <class Impl> 8412292SN/Avoid 8422292SN/ADefaultIEW<Impl>::sortInsts() 8432292SN/A{ 8442292SN/A int insts_from_rename = fromRename->size; 8452326SN/A#ifdef DEBUG 8462292SN/A for (int i = 0; i < numThreads; i++) 8472292SN/A assert(insts[i].empty()); 8482326SN/A#endif 8492292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8502292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8512292SN/A } 8522292SN/A} 8532292SN/A 8542292SN/Atemplate <class Impl> 8552292SN/Avoid 8562292SN/ADefaultIEW<Impl>::wakeCPU() 8572292SN/A{ 8582292SN/A cpu->wakeCPU(); 8592292SN/A} 8602292SN/A 8612292SN/Atemplate <class Impl> 8622292SN/Avoid 8632292SN/ADefaultIEW<Impl>::activityThisCycle() 8642292SN/A{ 8652292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8662292SN/A cpu->activityThisCycle(); 8672292SN/A} 8682292SN/A 8692292SN/Atemplate <class Impl> 8702292SN/Ainline void 8712292SN/ADefaultIEW<Impl>::activateStage() 8722292SN/A{ 8732292SN/A DPRINTF(Activity, "Activating stage.\n"); 8742292SN/A cpu->activateStage(FullCPU::IEWIdx); 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Ainline void 8792292SN/ADefaultIEW<Impl>::deactivateStage() 8802292SN/A{ 8812292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8822292SN/A cpu->deactivateStage(FullCPU::IEWIdx); 8832292SN/A} 8842292SN/A 8852292SN/Atemplate<class Impl> 8862292SN/Avoid 8872292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8882292SN/A{ 8892292SN/A // If status is Running or idle, 8902292SN/A // call dispatchInsts() 8912292SN/A // If status is Unblocking, 8922292SN/A // buffer any instructions coming from rename 8932292SN/A // continue trying to empty skid buffer 8942292SN/A // check if stall conditions have passed 8952292SN/A 8962292SN/A if (dispatchStatus[tid] == Blocked) { 8972292SN/A ++iewBlockCycles; 8982292SN/A 8992292SN/A } else if (dispatchStatus[tid] == Squashing) { 9002292SN/A ++iewSquashCycles; 9012292SN/A } 9022292SN/A 9032292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9042292SN/A // will allow, as long as it is not currently blocked. 9052292SN/A if (dispatchStatus[tid] == Running || 9062292SN/A dispatchStatus[tid] == Idle) { 9072292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9082292SN/A "dispatch.\n", tid); 9092292SN/A 9102292SN/A dispatchInsts(tid); 9112292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9122292SN/A // Make sure that the skid buffer has something in it if the 9132292SN/A // status is unblocking. 9142292SN/A assert(!skidsEmpty()); 9152292SN/A 9162292SN/A // If the status was unblocking, then instructions from the skid 9172292SN/A // buffer were used. Remove those instructions and handle 9182292SN/A // the rest of unblocking. 9192292SN/A dispatchInsts(tid); 9202292SN/A 9212292SN/A ++iewUnblockCycles; 9222292SN/A 9232292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9242292SN/A // Add the current inputs to the skid buffer so they can be 9252292SN/A // reprocessed when this stage unblocks. 9262292SN/A skidInsert(tid); 9272292SN/A } 9282292SN/A 9292292SN/A unblock(tid); 9302292SN/A } 9312292SN/A} 9322292SN/A 9332292SN/Atemplate <class Impl> 9342292SN/Avoid 9352292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9362292SN/A{ 9372292SN/A dispatchedAllInsts = true; 9382292SN/A 9392292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9402292SN/A // otherwise. 9412292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9422292SN/A dispatchStatus[tid] == Unblocking ? 9432292SN/A skidBuffer[tid] : insts[tid]; 9442292SN/A 9452292SN/A int insts_to_add = insts_to_dispatch.size(); 9462292SN/A 9472292SN/A DynInstPtr inst; 9482292SN/A bool add_to_iq = false; 9492292SN/A int dis_num_inst = 0; 9502292SN/A 9512292SN/A // Loop through the instructions, putting them in the instruction 9522292SN/A // queue. 9532292SN/A for ( ; dis_num_inst < insts_to_add && 9542292SN/A dis_num_inst < issueReadWidth; 9552292SN/A ++dis_num_inst) 9562292SN/A { 9572292SN/A inst = insts_to_dispatch.front(); 9582292SN/A 9592292SN/A if (dispatchStatus[tid] == Unblocking) { 9602292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9612292SN/A "buffer\n", tid); 9622292SN/A } 9632292SN/A 9642292SN/A // Make sure there's a valid instruction there. 9652292SN/A assert(inst); 9662292SN/A 9672292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9682292SN/A "IQ.\n", 9692292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9702292SN/A 9712292SN/A // Be sure to mark these instructions as ready so that the 9722292SN/A // commit stage can go ahead and execute them, and mark 9732292SN/A // them as issued so the IQ doesn't reprocess them. 9742292SN/A 9752292SN/A // Check for squashed instructions. 9762292SN/A if (inst->isSquashed()) { 9772292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9782292SN/A "not adding to IQ.\n", tid); 9792292SN/A 9802292SN/A ++iewDispSquashedInsts; 9812292SN/A 9822292SN/A insts_to_dispatch.pop(); 9832292SN/A 9842292SN/A //Tell Rename That An Instruction has been processed 9852292SN/A if (inst->isLoad() || inst->isStore()) { 9862292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9872292SN/A } 9882292SN/A toRename->iewInfo[tid].dispatched++; 9892292SN/A 9902292SN/A continue; 9912292SN/A } 9922292SN/A 9932292SN/A // Check for full conditions. 9942292SN/A if (instQueue.isFull(tid)) { 9952292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 9962292SN/A 9972292SN/A // Call function to start blocking. 9982292SN/A block(tid); 9992292SN/A 10002292SN/A // Set unblock to false. Special case where we are using 10012292SN/A // skidbuffer (unblocking) instructions but then we still 10022292SN/A // get full in the IQ. 10032292SN/A toRename->iewUnblock[tid] = false; 10042292SN/A 10052292SN/A dispatchedAllInsts = false; 10062292SN/A 10072292SN/A ++iewIQFullEvents; 10082292SN/A break; 10092292SN/A } else if (ldstQueue.isFull(tid)) { 10102292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10112292SN/A 10122292SN/A // Call function to start blocking. 10132292SN/A block(tid); 10142292SN/A 10152292SN/A // Set unblock to false. Special case where we are using 10162292SN/A // skidbuffer (unblocking) instructions but then we still 10172292SN/A // get full in the IQ. 10182292SN/A toRename->iewUnblock[tid] = false; 10192292SN/A 10202292SN/A dispatchedAllInsts = false; 10212292SN/A 10222292SN/A ++iewLSQFullEvents; 10232292SN/A break; 10242292SN/A } 10252292SN/A 10262292SN/A // Otherwise issue the instruction just fine. 10272292SN/A if (inst->isLoad()) { 10282292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10292292SN/A "encountered, adding to LSQ.\n", tid); 10302292SN/A 10312292SN/A // Reserve a spot in the load store queue for this 10322292SN/A // memory access. 10332292SN/A ldstQueue.insertLoad(inst); 10342292SN/A 10352292SN/A ++iewDispLoadInsts; 10362292SN/A 10372292SN/A add_to_iq = true; 10382292SN/A 10392292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10402292SN/A } else if (inst->isStore()) { 10412292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10422292SN/A "encountered, adding to LSQ.\n", tid); 10432292SN/A 10442292SN/A ldstQueue.insertStore(inst); 10452292SN/A 10462292SN/A ++iewDispStoreInsts; 10472292SN/A 10482336SN/A if (inst->isStoreConditional()) { 10492336SN/A // Store conditionals need to be set as "canCommit()" 10502336SN/A // so that commit can process them when they reach the 10512336SN/A // head of commit. 10522348SN/A // @todo: This is somewhat specific to Alpha. 10532292SN/A inst->setCanCommit(); 10542292SN/A instQueue.insertNonSpec(inst); 10552292SN/A add_to_iq = false; 10562292SN/A 10572292SN/A ++iewDispNonSpecInsts; 10582292SN/A } else { 10592292SN/A add_to_iq = true; 10602292SN/A } 10612292SN/A 10622292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10632292SN/A#if FULL_SYSTEM 10642292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10652326SN/A // Same as non-speculative stores. 10662292SN/A inst->setCanCommit(); 10672292SN/A instQueue.insertBarrier(inst); 10682292SN/A add_to_iq = false; 10692292SN/A#endif 10702292SN/A } else if (inst->isNonSpeculative()) { 10712292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10722292SN/A "encountered, skipping.\n", tid); 10732292SN/A 10742326SN/A // Same as non-speculative stores. 10752292SN/A inst->setCanCommit(); 10762292SN/A 10772292SN/A // Specifically insert it as nonspeculative. 10782292SN/A instQueue.insertNonSpec(inst); 10792292SN/A 10802292SN/A ++iewDispNonSpecInsts; 10812292SN/A 10822292SN/A add_to_iq = false; 10832292SN/A } else if (inst->isNop()) { 10842292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10852292SN/A "skipping.\n", tid); 10862292SN/A 10872292SN/A inst->setIssued(); 10882292SN/A inst->setExecuted(); 10892292SN/A inst->setCanCommit(); 10902292SN/A 10912326SN/A instQueue.recordProducer(inst); 10922292SN/A 10932326SN/A exeNop[tid]++; 10942301SN/A 10952292SN/A add_to_iq = false; 10962292SN/A } else if (inst->isExecuted()) { 10972292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10982292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10992292SN/A "skipping.\n"); 11002292SN/A 11012292SN/A inst->setIssued(); 11022292SN/A inst->setCanCommit(); 11032292SN/A 11042326SN/A instQueue.recordProducer(inst); 11052292SN/A 11062292SN/A add_to_iq = false; 11072292SN/A } else { 11082292SN/A add_to_iq = true; 11092292SN/A } 11102292SN/A 11112292SN/A // If the instruction queue is not full, then add the 11122292SN/A // instruction. 11132292SN/A if (add_to_iq) { 11142292SN/A instQueue.insert(inst); 11152292SN/A } 11162292SN/A 11172292SN/A insts_to_dispatch.pop(); 11182292SN/A 11192292SN/A toRename->iewInfo[tid].dispatched++; 11202292SN/A 11212292SN/A ++iewDispatchedInsts; 11222292SN/A } 11232292SN/A 11242292SN/A if (!insts_to_dispatch.empty()) { 11252292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11262292SN/A block(tid); 11272292SN/A toRename->iewUnblock[tid] = false; 11282292SN/A } 11292292SN/A 11302292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11312292SN/A dispatchStatus[tid] = Running; 11322292SN/A 11332292SN/A updatedQueues = true; 11342292SN/A } 11352292SN/A 11362292SN/A dis_num_inst = 0; 11372292SN/A} 11382292SN/A 11392292SN/Atemplate <class Impl> 11402292SN/Avoid 11412292SN/ADefaultIEW<Impl>::printAvailableInsts() 11422292SN/A{ 11432292SN/A int inst = 0; 11442292SN/A 11452292SN/A cout << "Available Instructions: "; 11462292SN/A 11472292SN/A while (fromIssue->insts[inst]) { 11482292SN/A 11492292SN/A if (inst%3==0) cout << "\n\t"; 11502292SN/A 11512292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 11522292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11532292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11542292SN/A 11552292SN/A inst++; 11562292SN/A 11572292SN/A } 11582292SN/A 11592292SN/A cout << "\n"; 11602292SN/A} 11612292SN/A 11622292SN/Atemplate <class Impl> 11632292SN/Avoid 11642292SN/ADefaultIEW<Impl>::executeInsts() 11652292SN/A{ 11662292SN/A wbNumInst = 0; 11672292SN/A wbCycle = 0; 11682292SN/A 11692292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 11702292SN/A 11712292SN/A while (threads != (*activeThreads).end()) { 11722292SN/A unsigned tid = *threads++; 11732292SN/A fetchRedirect[tid] = false; 11742292SN/A } 11752292SN/A 11762698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11772698Sktlim@umich.edu// printAvailableInsts(); 11781062SN/A 11791062SN/A // Execute/writeback any instructions that are available. 11802333SN/A int insts_to_execute = fromIssue->size; 11812292SN/A int inst_num = 0; 11822333SN/A for (; inst_num < insts_to_execute; 11832326SN/A ++inst_num) { 11841062SN/A 11852292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11861062SN/A 11872333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11881062SN/A 11892292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11902292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 11911062SN/A 11921062SN/A // Check if the instruction is squashed; if so then skip it 11931062SN/A if (inst->isSquashed()) { 11942292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 11951062SN/A 11961062SN/A // Consider this instruction executed so that commit can go 11971062SN/A // ahead and retire the instruction. 11981062SN/A inst->setExecuted(); 11991062SN/A 12002292SN/A // Not sure if I should set this here or just let commit try to 12012292SN/A // commit any squashed instructions. I like the latter a bit more. 12022292SN/A inst->setCanCommit(); 12031062SN/A 12041062SN/A ++iewExecSquashedInsts; 12051062SN/A 12061062SN/A continue; 12071062SN/A } 12081062SN/A 12092292SN/A Fault fault = NoFault; 12101062SN/A 12111062SN/A // Execute instruction. 12121062SN/A // Note that if the instruction faults, it will be handled 12131062SN/A // at the commit stage. 12142292SN/A if (inst->isMemRef() && 12152292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12162292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12171062SN/A "reference.\n"); 12181062SN/A 12191062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12201062SN/A if (inst->isLoad()) { 12212292SN/A // Loads will mark themselves as executed, and their writeback 12222292SN/A // event adds the instruction to the queue to commit 12232292SN/A fault = ldstQueue.executeLoad(inst); 12241062SN/A } else if (inst->isStore()) { 12251681SN/A ldstQueue.executeStore(inst); 12261062SN/A 12272292SN/A // If the store had a fault then it may not have a mem req 12282669Sktlim@umich.edu if (inst->req && !(inst->req->getFlags() & LOCKED)) { 12292292SN/A inst->setExecuted(); 12302292SN/A 12312292SN/A instToCommit(inst); 12322292SN/A } 12332326SN/A 12342326SN/A // Store conditionals will mark themselves as 12352326SN/A // executed, and their writeback event will add the 12362326SN/A // instruction to the queue to commit. 12371062SN/A } else { 12382292SN/A panic("Unexpected memory type!\n"); 12391062SN/A } 12401062SN/A 12411062SN/A } else { 12421062SN/A inst->execute(); 12431062SN/A 12442292SN/A inst->setExecuted(); 12452292SN/A 12462292SN/A instToCommit(inst); 12471062SN/A } 12481062SN/A 12492301SN/A updateExeInstStats(inst); 12501681SN/A 12512326SN/A // Check if branch prediction was correct, if not then we need 12522326SN/A // to tell commit to squash in flight instructions. Only 12532326SN/A // handle this if there hasn't already been something that 12542107SN/A // redirects fetch in this group of instructions. 12551681SN/A 12562292SN/A // This probably needs to prioritize the redirects if a different 12572292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12582292SN/A // instruction first, so the branch resolution order will be correct. 12592292SN/A unsigned tid = inst->threadNumber; 12601062SN/A 12612292SN/A if (!fetchRedirect[tid]) { 12621062SN/A 12631062SN/A if (inst->mispredicted()) { 12642292SN/A fetchRedirect[tid] = true; 12651062SN/A 12662292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12672292SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 12681062SN/A inst->nextPC); 12691062SN/A 12701062SN/A // If incorrect, then signal the ROB that it must be squashed. 12712292SN/A squashDueToBranch(inst, tid); 12721062SN/A 12731062SN/A if (inst->predTaken()) { 12741062SN/A predictedTakenIncorrect++; 12752292SN/A } else { 12762292SN/A predictedNotTakenIncorrect++; 12771062SN/A } 12782292SN/A } else if (ldstQueue.violation(tid)) { 12792292SN/A fetchRedirect[tid] = true; 12801062SN/A 12812326SN/A // If there was an ordering violation, then get the 12822326SN/A // DynInst that caused the violation. Note that this 12832292SN/A // clears the violation signal. 12842292SN/A DynInstPtr violator; 12852292SN/A violator = ldstQueue.getMemDepViolator(tid); 12861062SN/A 12872292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 12881062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 12891062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 12901062SN/A 12911062SN/A // Tell the instruction queue that a violation has occured. 12921062SN/A instQueue.violation(inst, violator); 12931062SN/A 12941062SN/A // Squash. 12952292SN/A squashDueToMemOrder(inst,tid); 12961062SN/A 12971062SN/A ++memOrderViolationEvents; 12982292SN/A } else if (ldstQueue.loadBlocked(tid) && 12992292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13002292SN/A fetchRedirect[tid] = true; 13012292SN/A 13022292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13032292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13042292SN/A inst->readPC(), inst->seqNum); 13052292SN/A 13062292SN/A squashDueToMemBlocked(inst, tid); 13071062SN/A } 13081062SN/A } 13091062SN/A } 13102292SN/A 13112348SN/A // Update and record activity if we processed any instructions. 13122292SN/A if (inst_num) { 13132292SN/A if (exeStatus == Idle) { 13142292SN/A exeStatus = Running; 13152292SN/A } 13162292SN/A 13172292SN/A updatedQueues = true; 13182292SN/A 13192292SN/A cpu->activityThisCycle(); 13202292SN/A } 13212292SN/A 13222292SN/A // Need to reset this in case a writeback event needs to write into the 13232292SN/A // iew queue. That way the writeback event will write into the correct 13242292SN/A // spot in the queue. 13252292SN/A wbNumInst = 0; 13262107SN/A} 13272107SN/A 13282292SN/Atemplate <class Impl> 13292107SN/Avoid 13302292SN/ADefaultIEW<Impl>::writebackInsts() 13312107SN/A{ 13322326SN/A // Loop through the head of the time buffer and wake any 13332326SN/A // dependents. These instructions are about to write back. Also 13342326SN/A // mark scoreboard that this instruction is finally complete. 13352326SN/A // Either have IEW have direct access to scoreboard, or have this 13362326SN/A // as part of backwards communication. 13372107SN/A for (int inst_num = 0; inst_num < issueWidth && 13382292SN/A toCommit->insts[inst_num]; inst_num++) { 13392107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13402301SN/A int tid = inst->threadNumber; 13412107SN/A 13422698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 13432698Sktlim@umich.edu inst->seqNum, inst->readPC()); 13442107SN/A 13452301SN/A iewInstsToCommit[tid]++; 13462301SN/A 13472292SN/A // Some instructions will be sent to commit without having 13482292SN/A // executed because they need commit to handle them. 13492292SN/A // E.g. Uncached loads have not actually executed when they 13502292SN/A // are first sent to commit. Instead commit must tell the LSQ 13512292SN/A // when it's ready to execute the uncached load. 13522292SN/A if (!inst->isSquashed() && inst->isExecuted()) { 13532301SN/A int dependents = instQueue.wakeDependents(inst); 13542107SN/A 13552292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 13562292SN/A //mark as Ready 13572292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 13582292SN/A inst->renamedDestRegIdx(i)); 13592292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 13602107SN/A } 13612301SN/A 13622348SN/A if (dependents) { 13632348SN/A producerInst[tid]++; 13642348SN/A consumerInst[tid]+= dependents; 13652348SN/A } 13662326SN/A writebackCount[tid]++; 13672107SN/A } 13682107SN/A } 13691060SN/A} 13701060SN/A 13711681SN/Atemplate<class Impl> 13721060SN/Avoid 13732292SN/ADefaultIEW<Impl>::tick() 13741060SN/A{ 13752292SN/A wbNumInst = 0; 13762292SN/A wbCycle = 0; 13771060SN/A 13782292SN/A wroteToTimeBuffer = false; 13792292SN/A updatedQueues = false; 13801060SN/A 13812292SN/A sortInsts(); 13821060SN/A 13832326SN/A // Free function units marked as being freed this cycle. 13842326SN/A fuPool->processFreeUnits(); 13851062SN/A 13862292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 13871060SN/A 13882326SN/A // Check stall and squash signals, dispatch any instructions. 13892292SN/A while (threads != (*activeThreads).end()) { 13902292SN/A unsigned tid = *threads++; 13911060SN/A 13922292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 13931060SN/A 13942292SN/A checkSignalsAndUpdate(tid); 13952292SN/A dispatch(tid); 13961060SN/A } 13971060SN/A 13982292SN/A if (exeStatus != Squashing) { 13992292SN/A executeInsts(); 14001060SN/A 14012292SN/A writebackInsts(); 14022292SN/A 14032292SN/A // Have the instruction queue try to schedule any ready instructions. 14042292SN/A // (In actuality, this scheduling is for instructions that will 14052292SN/A // be executed next cycle.) 14062292SN/A instQueue.scheduleReadyInsts(); 14072292SN/A 14082292SN/A // Also should advance its own time buffers if the stage ran. 14092292SN/A // Not the best place for it, but this works (hopefully). 14102292SN/A issueToExecQueue.advance(); 14112292SN/A } 14122292SN/A 14132292SN/A bool broadcast_free_entries = false; 14142292SN/A 14152292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14162292SN/A exeStatus = Idle; 14172292SN/A updateLSQNextCycle = false; 14182292SN/A 14192292SN/A broadcast_free_entries = true; 14202292SN/A } 14212292SN/A 14222292SN/A // Writeback any stores using any leftover bandwidth. 14231681SN/A ldstQueue.writebackStores(); 14241681SN/A 14251061SN/A // Check the committed load/store signals to see if there's a load 14261061SN/A // or store to commit. Also check if it's being told to execute a 14271061SN/A // nonspeculative instruction. 14281681SN/A // This is pretty inefficient... 14292292SN/A 14302292SN/A threads = (*activeThreads).begin(); 14312292SN/A while (threads != (*activeThreads).end()) { 14322292SN/A unsigned tid = (*threads++); 14332292SN/A 14342292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14352292SN/A 14362348SN/A // Update structures based on instructions committed. 14372292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14382292SN/A !fromCommit->commitInfo[tid].squash && 14392292SN/A !fromCommit->commitInfo[tid].robSquashing) { 14402292SN/A 14412292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14422292SN/A 14432292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14442292SN/A 14452292SN/A updateLSQNextCycle = true; 14462292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14472292SN/A } 14482292SN/A 14492292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 14502292SN/A 14512292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 14522292SN/A if (fromCommit->commitInfo[tid].uncached) { 14532292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 14542292SN/A } else { 14552292SN/A instQueue.scheduleNonSpec( 14562292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 14572292SN/A } 14582292SN/A } 14592292SN/A 14602292SN/A if (broadcast_free_entries) { 14612292SN/A toFetch->iewInfo[tid].iqCount = 14622292SN/A instQueue.getCount(tid); 14632292SN/A toFetch->iewInfo[tid].ldstqCount = 14642292SN/A ldstQueue.getCount(tid); 14652292SN/A 14662292SN/A toRename->iewInfo[tid].usedIQ = true; 14672292SN/A toRename->iewInfo[tid].freeIQEntries = 14682292SN/A instQueue.numFreeEntries(); 14692292SN/A toRename->iewInfo[tid].usedLSQ = true; 14702292SN/A toRename->iewInfo[tid].freeLSQEntries = 14712292SN/A ldstQueue.numFreeEntries(tid); 14722292SN/A 14732292SN/A wroteToTimeBuffer = true; 14742292SN/A } 14752292SN/A 14762292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 14772292SN/A tid, toRename->iewInfo[tid].dispatched); 14781061SN/A } 14791061SN/A 14802292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 14812292SN/A "LSQ has %i free entries.\n", 14822292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 14832292SN/A ldstQueue.numFreeEntries()); 14842292SN/A 14852292SN/A updateStatus(); 14862292SN/A 14872292SN/A if (wroteToTimeBuffer) { 14882292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 14892292SN/A cpu->activityThisCycle(); 14901061SN/A } 14911060SN/A} 14921060SN/A 14932301SN/Atemplate <class Impl> 14941060SN/Avoid 14952301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 14961060SN/A{ 14972301SN/A int thread_number = inst->threadNumber; 14981060SN/A 14992301SN/A // 15002301SN/A // Pick off the software prefetches 15012301SN/A // 15022301SN/A#ifdef TARGET_ALPHA 15032301SN/A if (inst->isDataPrefetch()) 15042326SN/A exeSwp[thread_number]++; 15052301SN/A else 15062301SN/A iewExecutedInsts++; 15072301SN/A#else 15082669Sktlim@umich.edu iewExecutedInsts++; 15092301SN/A#endif 15101060SN/A 15112301SN/A // 15122301SN/A // Control operations 15132301SN/A // 15142301SN/A if (inst->isControl()) 15152326SN/A exeBranches[thread_number]++; 15161060SN/A 15172301SN/A // 15182301SN/A // Memory operations 15192301SN/A // 15202301SN/A if (inst->isMemRef()) { 15212326SN/A exeRefs[thread_number]++; 15221060SN/A 15232301SN/A if (inst->isLoad()) { 15242301SN/A iewExecLoadInsts[thread_number]++; 15251060SN/A } 15261060SN/A } 15271060SN/A} 1528