iew_impl.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// @todo: Fix the instantaneous communication among all the stages within
30// iew.  There's a clear delay between issue and execute, yet backwards
31// communication happens simultaneously.
32
33#include <queue>
34
35#include "base/timebuf.hh"
36#include "cpu/o3/fu_pool.hh"
37#include "cpu/o3/iew.hh"
38
39using namespace std;
40
41template<class Impl>
42DefaultIEW<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst,
43                                                     DefaultIEW<Impl> *_iew)
44    : Event(&mainEventQueue), inst(_inst), iewStage(_iew)
45{
46    this->setFlags(Event::AutoDelete);
47}
48
49template<class Impl>
50void
51DefaultIEW<Impl>::LdWritebackEvent::process()
52{
53    DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum);
54    DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
55
56    //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
57
58    if (iewStage->isSwitchedOut()) {
59        inst = NULL;
60        return;
61    } else if (inst->isSquashed()) {
62        iewStage->wakeCPU();
63        inst = NULL;
64        return;
65    }
66
67    iewStage->wakeCPU();
68
69    if (!inst->isExecuted()) {
70        inst->setExecuted();
71
72        // Complete access to copy data to proper place.
73        if (inst->isStore()) {
74            inst->completeAcc();
75        }
76    }
77
78    // Need to insert instruction into queue to commit
79    iewStage->instToCommit(inst);
80
81    iewStage->activityThisCycle();
82
83    inst = NULL;
84}
85
86template<class Impl>
87const char *
88DefaultIEW<Impl>::LdWritebackEvent::description()
89{
90    return "Load writeback event";
91}
92
93template<class Impl>
94DefaultIEW<Impl>::DefaultIEW(Params *params)
95    : // @todo: Make this into a parameter.
96      issueToExecQueue(5, 5),
97      instQueue(params),
98      ldstQueue(params),
99      fuPool(params->fuPool),
100      commitToIEWDelay(params->commitToIEWDelay),
101      renameToIEWDelay(params->renameToIEWDelay),
102      issueToExecuteDelay(params->issueToExecuteDelay),
103      issueReadWidth(params->issueWidth),
104      issueWidth(params->issueWidth),
105      executeWidth(params->executeWidth),
106      numThreads(params->numberOfThreads),
107      switchedOut(false)
108{
109    _status = Active;
110    exeStatus = Running;
111    wbStatus = Idle;
112
113    // Setup wire to read instructions coming from issue.
114    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
115
116    // Instruction queue needs the queue between issue and execute.
117    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
118
119    instQueue.setIEW(this);
120    ldstQueue.setIEW(this);
121
122    for (int i=0; i < numThreads; i++) {
123        dispatchStatus[i] = Running;
124        stalls[i].commit = false;
125        fetchRedirect[i] = false;
126    }
127
128    updateLSQNextCycle = false;
129
130    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
131}
132
133template <class Impl>
134std::string
135DefaultIEW<Impl>::name() const
136{
137    return cpu->name() + ".iew";
138}
139
140template <class Impl>
141void
142DefaultIEW<Impl>::regStats()
143{
144    using namespace Stats;
145
146    instQueue.regStats();
147
148    iewIdleCycles
149        .name(name() + ".iewIdleCycles")
150        .desc("Number of cycles IEW is idle");
151
152    iewSquashCycles
153        .name(name() + ".iewSquashCycles")
154        .desc("Number of cycles IEW is squashing");
155
156    iewBlockCycles
157        .name(name() + ".iewBlockCycles")
158        .desc("Number of cycles IEW is blocking");
159
160    iewUnblockCycles
161        .name(name() + ".iewUnblockCycles")
162        .desc("Number of cycles IEW is unblocking");
163
164    iewDispatchedInsts
165        .name(name() + ".iewDispatchedInsts")
166        .desc("Number of instructions dispatched to IQ");
167
168    iewDispSquashedInsts
169        .name(name() + ".iewDispSquashedInsts")
170        .desc("Number of squashed instructions skipped by dispatch");
171
172    iewDispLoadInsts
173        .name(name() + ".iewDispLoadInsts")
174        .desc("Number of dispatched load instructions");
175
176    iewDispStoreInsts
177        .name(name() + ".iewDispStoreInsts")
178        .desc("Number of dispatched store instructions");
179
180    iewDispNonSpecInsts
181        .name(name() + ".iewDispNonSpecInsts")
182        .desc("Number of dispatched non-speculative instructions");
183
184    iewIQFullEvents
185        .name(name() + ".iewIQFullEvents")
186        .desc("Number of times the IQ has become full, causing a stall");
187
188    iewLSQFullEvents
189        .name(name() + ".iewLSQFullEvents")
190        .desc("Number of times the LSQ has become full, causing a stall");
191
192    iewExecutedInsts
193        .name(name() + ".iewExecutedInsts")
194        .desc("Number of executed instructions");
195
196    iewExecLoadInsts
197        .init(cpu->number_of_threads)
198        .name(name() + ".iewExecLoadInsts")
199        .desc("Number of load instructions executed")
200        .flags(total);
201
202    iewExecSquashedInsts
203        .name(name() + ".iewExecSquashedInsts")
204        .desc("Number of squashed instructions skipped in execute");
205
206    memOrderViolationEvents
207        .name(name() + ".memOrderViolationEvents")
208        .desc("Number of memory order violations");
209
210    predictedTakenIncorrect
211        .name(name() + ".predictedTakenIncorrect")
212        .desc("Number of branches that were predicted taken incorrectly");
213
214    predictedNotTakenIncorrect
215        .name(name() + ".predictedNotTakenIncorrect")
216        .desc("Number of branches that were predicted not taken incorrectly");
217
218    branchMispredicts
219        .name(name() + ".branchMispredicts")
220        .desc("Number of branch mispredicts detected at execute");
221
222    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
223
224    exeSwp
225        .init(cpu->number_of_threads)
226        .name(name() + ".EXEC:swp")
227        .desc("number of swp insts executed")
228        .flags(total)
229        ;
230
231    exeNop
232        .init(cpu->number_of_threads)
233        .name(name() + ".EXEC:nop")
234        .desc("number of nop insts executed")
235        .flags(total)
236        ;
237
238    exeRefs
239        .init(cpu->number_of_threads)
240        .name(name() + ".EXEC:refs")
241        .desc("number of memory reference insts executed")
242        .flags(total)
243        ;
244
245    exeBranches
246        .init(cpu->number_of_threads)
247        .name(name() + ".EXEC:branches")
248        .desc("Number of branches executed")
249        .flags(total)
250        ;
251
252    issueRate
253        .name(name() + ".EXEC:rate")
254        .desc("Inst execution rate")
255        .flags(total)
256        ;
257    issueRate = iewExecutedInsts / cpu->numCycles;
258
259    iewExecStoreInsts
260        .name(name() + ".EXEC:stores")
261        .desc("Number of stores executed")
262        .flags(total)
263        ;
264    iewExecStoreInsts = exeRefs - iewExecLoadInsts;
265/*
266    for (int i=0; i<Num_OpClasses; ++i) {
267        stringstream subname;
268        subname << opClassStrings[i] << "_delay";
269        issue_delay_dist.subname(i, subname.str());
270    }
271*/
272    //
273    //  Other stats
274    //
275
276    iewInstsToCommit
277        .init(cpu->number_of_threads)
278        .name(name() + ".WB:sent")
279        .desc("cumulative count of insts sent to commit")
280        .flags(total)
281        ;
282
283    writebackCount
284        .init(cpu->number_of_threads)
285        .name(name() + ".WB:count")
286        .desc("cumulative count of insts written-back")
287        .flags(total)
288        ;
289
290    producerInst
291        .init(cpu->number_of_threads)
292        .name(name() + ".WB:producers")
293        .desc("num instructions producing a value")
294        .flags(total)
295        ;
296
297    consumerInst
298        .init(cpu->number_of_threads)
299        .name(name() + ".WB:consumers")
300        .desc("num instructions consuming a value")
301        .flags(total)
302        ;
303
304    wbPenalized
305        .init(cpu->number_of_threads)
306        .name(name() + ".WB:penalized")
307        .desc("number of instrctions required to write to 'other' IQ")
308        .flags(total)
309        ;
310
311    wbPenalizedRate
312        .name(name() + ".WB:penalized_rate")
313        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
314        .flags(total)
315        ;
316
317    wbPenalizedRate = wbPenalized / writebackCount;
318
319    wbFanout
320        .name(name() + ".WB:fanout")
321        .desc("average fanout of values written-back")
322        .flags(total)
323        ;
324
325    wbFanout = producerInst / consumerInst;
326
327    wbRate
328        .name(name() + ".WB:rate")
329        .desc("insts written-back per cycle")
330        .flags(total)
331        ;
332    wbRate = writebackCount / cpu->numCycles;
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::initStage()
338{
339    for (int tid=0; tid < numThreads; tid++) {
340        toRename->iewInfo[tid].usedIQ = true;
341        toRename->iewInfo[tid].freeIQEntries =
342            instQueue.numFreeEntries(tid);
343
344        toRename->iewInfo[tid].usedLSQ = true;
345        toRename->iewInfo[tid].freeLSQEntries =
346            ldstQueue.numFreeEntries(tid);
347    }
348}
349
350template<class Impl>
351void
352DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
353{
354    DPRINTF(IEW, "Setting CPU pointer.\n");
355    cpu = cpu_ptr;
356
357    instQueue.setCPU(cpu_ptr);
358    ldstQueue.setCPU(cpu_ptr);
359
360    cpu->activateStage(FullCPU::IEWIdx);
361}
362
363template<class Impl>
364void
365DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
366{
367    DPRINTF(IEW, "Setting time buffer pointer.\n");
368    timeBuffer = tb_ptr;
369
370    // Setup wire to read information from time buffer, from commit.
371    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
372
373    // Setup wire to write information back to previous stages.
374    toRename = timeBuffer->getWire(0);
375
376    toFetch = timeBuffer->getWire(0);
377
378    // Instruction queue also needs main time buffer.
379    instQueue.setTimeBuffer(tb_ptr);
380}
381
382template<class Impl>
383void
384DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
385{
386    DPRINTF(IEW, "Setting rename queue pointer.\n");
387    renameQueue = rq_ptr;
388
389    // Setup wire to read information from rename queue.
390    fromRename = renameQueue->getWire(-renameToIEWDelay);
391}
392
393template<class Impl>
394void
395DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
396{
397    DPRINTF(IEW, "Setting IEW queue pointer.\n");
398    iewQueue = iq_ptr;
399
400    // Setup wire to write instructions to commit.
401    toCommit = iewQueue->getWire(0);
402}
403
404template<class Impl>
405void
406DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
407{
408    DPRINTF(IEW, "Setting active threads list pointer.\n");
409    activeThreads = at_ptr;
410
411    ldstQueue.setActiveThreads(at_ptr);
412    instQueue.setActiveThreads(at_ptr);
413}
414
415template<class Impl>
416void
417DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
418{
419    DPRINTF(IEW, "Setting scoreboard pointer.\n");
420    scoreboard = sb_ptr;
421}
422
423#if 0
424template<class Impl>
425void
426DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
427{
428    ldstQueue.setPageTable(pt_ptr);
429}
430#endif
431
432template <class Impl>
433void
434DefaultIEW<Impl>::switchOut()
435{
436    // IEW is ready to switch out at any time.
437    cpu->signalSwitched();
438}
439
440template <class Impl>
441void
442DefaultIEW<Impl>::doSwitchOut()
443{
444    // Clear any state.
445    switchedOut = true;
446
447    instQueue.switchOut();
448    ldstQueue.switchOut();
449    fuPool->switchOut();
450
451    for (int i = 0; i < numThreads; i++) {
452        while (!insts[i].empty())
453            insts[i].pop();
454        while (!skidBuffer[i].empty())
455            skidBuffer[i].pop();
456    }
457}
458
459template <class Impl>
460void
461DefaultIEW<Impl>::takeOverFrom()
462{
463    // Reset all state.
464    _status = Active;
465    exeStatus = Running;
466    wbStatus = Idle;
467    switchedOut = false;
468
469    instQueue.takeOverFrom();
470    ldstQueue.takeOverFrom();
471    fuPool->takeOverFrom();
472
473    initStage();
474    cpu->activityThisCycle();
475
476    for (int i=0; i < numThreads; i++) {
477        dispatchStatus[i] = Running;
478        stalls[i].commit = false;
479        fetchRedirect[i] = false;
480    }
481
482    updateLSQNextCycle = false;
483
484    // @todo: Fix hardcoded number
485    for (int i = 0; i < 6; ++i) {
486        issueToExecQueue.advance();
487    }
488}
489
490template<class Impl>
491void
492DefaultIEW<Impl>::squash(unsigned tid)
493{
494    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
495            tid);
496
497    // Tell the IQ to start squashing.
498    instQueue.squash(tid);
499
500    // Tell the LDSTQ to start squashing.
501    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
502
503    updatedQueues = true;
504
505    // Clear the skid buffer in case it has any data in it.
506    while (!skidBuffer[tid].empty()) {
507
508        if (skidBuffer[tid].front()->isLoad() ||
509            skidBuffer[tid].front()->isStore() ) {
510            toRename->iewInfo[tid].dispatchedToLSQ++;
511        }
512
513        toRename->iewInfo[tid].dispatched++;
514
515        skidBuffer[tid].pop();
516    }
517
518    while (!insts[tid].empty()) {
519        if (insts[tid].front()->isLoad() ||
520            insts[tid].front()->isStore() ) {
521            toRename->iewInfo[tid].dispatchedToLSQ++;
522        }
523
524        toRename->iewInfo[tid].dispatched++;
525
526        insts[tid].pop();
527    }
528}
529
530template<class Impl>
531void
532DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
533{
534    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
535            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
536
537    toCommit->squash[tid] = true;
538    toCommit->squashedSeqNum[tid] = inst->seqNum;
539    toCommit->mispredPC[tid] = inst->readPC();
540    toCommit->nextPC[tid] = inst->readNextPC();
541    toCommit->branchMispredict[tid] = true;
542    toCommit->branchTaken[tid] = inst->readNextPC() !=
543        (inst->readPC() + sizeof(TheISA::MachInst));
544
545    toCommit->includeSquashInst[tid] = false;
546
547    wroteToTimeBuffer = true;
548}
549
550template<class Impl>
551void
552DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
553{
554    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
555            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
556
557    toCommit->squash[tid] = true;
558    toCommit->squashedSeqNum[tid] = inst->seqNum;
559    toCommit->nextPC[tid] = inst->readNextPC();
560
561    toCommit->includeSquashInst[tid] = false;
562
563    wroteToTimeBuffer = true;
564}
565
566template<class Impl>
567void
568DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
569{
570    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
571            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
572
573    toCommit->squash[tid] = true;
574    toCommit->squashedSeqNum[tid] = inst->seqNum;
575    toCommit->nextPC[tid] = inst->readPC();
576
577    // Must include the broadcasted SN in the squash.
578    toCommit->includeSquashInst[tid] = true;
579
580    ldstQueue.setLoadBlockedHandled(tid);
581
582    wroteToTimeBuffer = true;
583}
584
585template<class Impl>
586void
587DefaultIEW<Impl>::block(unsigned tid)
588{
589    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
590
591    if (dispatchStatus[tid] != Blocked &&
592        dispatchStatus[tid] != Unblocking) {
593        toRename->iewBlock[tid] = true;
594        wroteToTimeBuffer = true;
595    }
596
597    // Add the current inputs to the skid buffer so they can be
598    // reprocessed when this stage unblocks.
599    skidInsert(tid);
600
601    dispatchStatus[tid] = Blocked;
602}
603
604template<class Impl>
605void
606DefaultIEW<Impl>::unblock(unsigned tid)
607{
608    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
609            "buffer %u.\n",tid, tid);
610
611    // If the skid bufffer is empty, signal back to previous stages to unblock.
612    // Also switch status to running.
613    if (skidBuffer[tid].empty()) {
614        toRename->iewUnblock[tid] = true;
615        wroteToTimeBuffer = true;
616        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
617        dispatchStatus[tid] = Running;
618    }
619}
620
621template<class Impl>
622void
623DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
624{
625    instQueue.wakeDependents(inst);
626}
627
628template<class Impl>
629void
630DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
631{
632    instQueue.rescheduleMemInst(inst);
633}
634
635template<class Impl>
636void
637DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
638{
639    instQueue.replayMemInst(inst);
640}
641
642template<class Impl>
643void
644DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
645{
646    // First check the time slot that this instruction will write
647    // to.  If there are free write ports at the time, then go ahead
648    // and write the instruction to that time.  If there are not,
649    // keep looking back to see where's the first time there's a
650    // free slot.
651    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
652        ++wbNumInst;
653        if (wbNumInst == issueWidth) {
654            ++wbCycle;
655            wbNumInst = 0;
656        }
657
658        assert(wbCycle < 5);
659    }
660
661    // Add finished instruction to queue to commit.
662    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
663    (*iewQueue)[wbCycle].size++;
664}
665
666template <class Impl>
667unsigned
668DefaultIEW<Impl>::validInstsFromRename()
669{
670    unsigned inst_count = 0;
671
672    for (int i=0; i<fromRename->size; i++) {
673        if (!fromRename->insts[i]->squashed)
674            inst_count++;
675    }
676
677    return inst_count;
678}
679
680template<class Impl>
681void
682DefaultIEW<Impl>::skidInsert(unsigned tid)
683{
684    DynInstPtr inst = NULL;
685
686    while (!insts[tid].empty()) {
687        inst = insts[tid].front();
688
689        insts[tid].pop();
690
691        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
692                "dispatch skidBuffer %i\n",tid, inst->seqNum,
693                inst->readPC(),tid);
694
695        skidBuffer[tid].push(inst);
696    }
697
698    assert(skidBuffer[tid].size() <= skidBufferMax &&
699           "Skidbuffer Exceeded Max Size");
700}
701
702template<class Impl>
703int
704DefaultIEW<Impl>::skidCount()
705{
706    int max=0;
707
708    list<unsigned>::iterator threads = (*activeThreads).begin();
709
710    while (threads != (*activeThreads).end()) {
711        unsigned thread_count = skidBuffer[*threads++].size();
712        if (max < thread_count)
713            max = thread_count;
714    }
715
716    return max;
717}
718
719template<class Impl>
720bool
721DefaultIEW<Impl>::skidsEmpty()
722{
723    list<unsigned>::iterator threads = (*activeThreads).begin();
724
725    while (threads != (*activeThreads).end()) {
726        if (!skidBuffer[*threads++].empty())
727            return false;
728    }
729
730    return true;
731}
732
733template <class Impl>
734void
735DefaultIEW<Impl>::updateStatus()
736{
737    bool any_unblocking = false;
738
739    list<unsigned>::iterator threads = (*activeThreads).begin();
740
741    threads = (*activeThreads).begin();
742
743    while (threads != (*activeThreads).end()) {
744        unsigned tid = *threads++;
745
746        if (dispatchStatus[tid] == Unblocking) {
747            any_unblocking = true;
748            break;
749        }
750    }
751
752    // If there are no ready instructions waiting to be scheduled by the IQ,
753    // and there's no stores waiting to write back, and dispatch is not
754    // unblocking, then there is no internal activity for the IEW stage.
755    if (_status == Active && !instQueue.hasReadyInsts() &&
756        !ldstQueue.willWB() && !any_unblocking) {
757        DPRINTF(IEW, "IEW switching to idle\n");
758
759        deactivateStage();
760
761        _status = Inactive;
762    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
763                                       ldstQueue.willWB() ||
764                                       any_unblocking)) {
765        // Otherwise there is internal activity.  Set to active.
766        DPRINTF(IEW, "IEW switching to active\n");
767
768        activateStage();
769
770        _status = Active;
771    }
772}
773
774template <class Impl>
775void
776DefaultIEW<Impl>::resetEntries()
777{
778    instQueue.resetEntries();
779    ldstQueue.resetEntries();
780}
781
782template <class Impl>
783void
784DefaultIEW<Impl>::readStallSignals(unsigned tid)
785{
786    if (fromCommit->commitBlock[tid]) {
787        stalls[tid].commit = true;
788    }
789
790    if (fromCommit->commitUnblock[tid]) {
791        assert(stalls[tid].commit);
792        stalls[tid].commit = false;
793    }
794}
795
796template <class Impl>
797bool
798DefaultIEW<Impl>::checkStall(unsigned tid)
799{
800    bool ret_val(false);
801
802    if (stalls[tid].commit) {
803        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
804        ret_val = true;
805    } else if (instQueue.isFull(tid)) {
806        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
807        ret_val = true;
808    } else if (ldstQueue.isFull(tid)) {
809        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
810
811        if (ldstQueue.numLoads(tid) > 0 ) {
812
813            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
814                    tid,ldstQueue.getLoadHeadSeqNum(tid));
815        }
816
817        if (ldstQueue.numStores(tid) > 0) {
818
819            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
820                    tid,ldstQueue.getStoreHeadSeqNum(tid));
821        }
822
823        ret_val = true;
824    } else if (ldstQueue.isStalled(tid)) {
825        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
826        ret_val = true;
827    }
828
829    return ret_val;
830}
831
832template <class Impl>
833void
834DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
835{
836    // Check if there's a squash signal, squash if there is
837    // Check stall signals, block if there is.
838    // If status was Blocked
839    //     if so then go to unblocking
840    // If status was Squashing
841    //     check if squashing is not high.  Switch to running this cycle.
842
843    readStallSignals(tid);
844
845    if (fromCommit->commitInfo[tid].squash) {
846        squash(tid);
847
848        if (dispatchStatus[tid] == Blocked ||
849            dispatchStatus[tid] == Unblocking) {
850            toRename->iewUnblock[tid] = true;
851            wroteToTimeBuffer = true;
852        }
853
854        dispatchStatus[tid] = Squashing;
855
856        fetchRedirect[tid] = false;
857        return;
858    }
859
860    if (fromCommit->commitInfo[tid].robSquashing) {
861        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
862
863        dispatchStatus[tid] = Squashing;
864
865        return;
866    }
867
868    if (checkStall(tid)) {
869        block(tid);
870        dispatchStatus[tid] = Blocked;
871        return;
872    }
873
874    if (dispatchStatus[tid] == Blocked) {
875        // Status from previous cycle was blocked, but there are no more stall
876        // conditions.  Switch over to unblocking.
877        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
878                tid);
879
880        dispatchStatus[tid] = Unblocking;
881
882        unblock(tid);
883
884        return;
885    }
886
887    if (dispatchStatus[tid] == Squashing) {
888        // Switch status to running if rename isn't being told to block or
889        // squash this cycle.
890        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
891                tid);
892
893        dispatchStatus[tid] = Running;
894
895        return;
896    }
897}
898
899template <class Impl>
900void
901DefaultIEW<Impl>::sortInsts()
902{
903    int insts_from_rename = fromRename->size;
904#ifdef DEBUG
905    for (int i = 0; i < numThreads; i++)
906        assert(insts[i].empty());
907#endif
908    for (int i = 0; i < insts_from_rename; ++i) {
909        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
910    }
911}
912
913template <class Impl>
914void
915DefaultIEW<Impl>::wakeCPU()
916{
917    cpu->wakeCPU();
918}
919
920template <class Impl>
921void
922DefaultIEW<Impl>::activityThisCycle()
923{
924    DPRINTF(Activity, "Activity this cycle.\n");
925    cpu->activityThisCycle();
926}
927
928template <class Impl>
929inline void
930DefaultIEW<Impl>::activateStage()
931{
932    DPRINTF(Activity, "Activating stage.\n");
933    cpu->activateStage(FullCPU::IEWIdx);
934}
935
936template <class Impl>
937inline void
938DefaultIEW<Impl>::deactivateStage()
939{
940    DPRINTF(Activity, "Deactivating stage.\n");
941    cpu->deactivateStage(FullCPU::IEWIdx);
942}
943
944template<class Impl>
945void
946DefaultIEW<Impl>::dispatch(unsigned tid)
947{
948    // If status is Running or idle,
949    //     call dispatchInsts()
950    // If status is Unblocking,
951    //     buffer any instructions coming from rename
952    //     continue trying to empty skid buffer
953    //     check if stall conditions have passed
954
955    if (dispatchStatus[tid] == Blocked) {
956        ++iewBlockCycles;
957
958    } else if (dispatchStatus[tid] == Squashing) {
959        ++iewSquashCycles;
960    }
961
962    // Dispatch should try to dispatch as many instructions as its bandwidth
963    // will allow, as long as it is not currently blocked.
964    if (dispatchStatus[tid] == Running ||
965        dispatchStatus[tid] == Idle) {
966        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
967                "dispatch.\n", tid);
968
969        dispatchInsts(tid);
970    } else if (dispatchStatus[tid] == Unblocking) {
971        // Make sure that the skid buffer has something in it if the
972        // status is unblocking.
973        assert(!skidsEmpty());
974
975        // If the status was unblocking, then instructions from the skid
976        // buffer were used.  Remove those instructions and handle
977        // the rest of unblocking.
978        dispatchInsts(tid);
979
980        ++iewUnblockCycles;
981
982        if (validInstsFromRename() && dispatchedAllInsts) {
983            // Add the current inputs to the skid buffer so they can be
984            // reprocessed when this stage unblocks.
985            skidInsert(tid);
986        }
987
988        unblock(tid);
989    }
990}
991
992template <class Impl>
993void
994DefaultIEW<Impl>::dispatchInsts(unsigned tid)
995{
996    dispatchedAllInsts = true;
997
998    // Obtain instructions from skid buffer if unblocking, or queue from rename
999    // otherwise.
1000    std::queue<DynInstPtr> &insts_to_dispatch =
1001        dispatchStatus[tid] == Unblocking ?
1002        skidBuffer[tid] : insts[tid];
1003
1004    int insts_to_add = insts_to_dispatch.size();
1005
1006    DynInstPtr inst;
1007    bool add_to_iq = false;
1008    int dis_num_inst = 0;
1009
1010    // Loop through the instructions, putting them in the instruction
1011    // queue.
1012    for ( ; dis_num_inst < insts_to_add &&
1013              dis_num_inst < issueReadWidth;
1014          ++dis_num_inst)
1015    {
1016        inst = insts_to_dispatch.front();
1017
1018        if (dispatchStatus[tid] == Unblocking) {
1019            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1020                    "buffer\n", tid);
1021        }
1022
1023        // Make sure there's a valid instruction there.
1024        assert(inst);
1025
1026        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1027                "IQ.\n",
1028                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1029
1030        // Be sure to mark these instructions as ready so that the
1031        // commit stage can go ahead and execute them, and mark
1032        // them as issued so the IQ doesn't reprocess them.
1033
1034        // Check for squashed instructions.
1035        if (inst->isSquashed()) {
1036            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1037                    "not adding to IQ.\n", tid);
1038
1039            ++iewDispSquashedInsts;
1040
1041            insts_to_dispatch.pop();
1042
1043            //Tell Rename That An Instruction has been processed
1044            if (inst->isLoad() || inst->isStore()) {
1045                toRename->iewInfo[tid].dispatchedToLSQ++;
1046            }
1047            toRename->iewInfo[tid].dispatched++;
1048
1049            continue;
1050        }
1051
1052        // Check for full conditions.
1053        if (instQueue.isFull(tid)) {
1054            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1055
1056            // Call function to start blocking.
1057            block(tid);
1058
1059            // Set unblock to false. Special case where we are using
1060            // skidbuffer (unblocking) instructions but then we still
1061            // get full in the IQ.
1062            toRename->iewUnblock[tid] = false;
1063
1064            dispatchedAllInsts = false;
1065
1066            ++iewIQFullEvents;
1067            break;
1068        } else if (ldstQueue.isFull(tid)) {
1069            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1070
1071            // Call function to start blocking.
1072            block(tid);
1073
1074            // Set unblock to false. Special case where we are using
1075            // skidbuffer (unblocking) instructions but then we still
1076            // get full in the IQ.
1077            toRename->iewUnblock[tid] = false;
1078
1079            dispatchedAllInsts = false;
1080
1081            ++iewLSQFullEvents;
1082            break;
1083        }
1084
1085        // Otherwise issue the instruction just fine.
1086        if (inst->isLoad()) {
1087            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1088                    "encountered, adding to LSQ.\n", tid);
1089
1090            // Reserve a spot in the load store queue for this
1091            // memory access.
1092            ldstQueue.insertLoad(inst);
1093
1094            ++iewDispLoadInsts;
1095
1096            add_to_iq = true;
1097
1098            toRename->iewInfo[tid].dispatchedToLSQ++;
1099        } else if (inst->isStore()) {
1100            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1101                    "encountered, adding to LSQ.\n", tid);
1102
1103            ldstQueue.insertStore(inst);
1104
1105            ++iewDispStoreInsts;
1106
1107            if (inst->isStoreConditional()) {
1108                // Store conditionals need to be set as "canCommit()"
1109                // so that commit can process them when they reach the
1110                // head of commit.
1111                // @todo: This is somewhat specific to Alpha.
1112                inst->setCanCommit();
1113                instQueue.insertNonSpec(inst);
1114                add_to_iq = false;
1115
1116                ++iewDispNonSpecInsts;
1117            } else {
1118                add_to_iq = true;
1119            }
1120
1121            toRename->iewInfo[tid].dispatchedToLSQ++;
1122#if FULL_SYSTEM
1123        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1124            // Same as non-speculative stores.
1125            inst->setCanCommit();
1126            instQueue.insertBarrier(inst);
1127            add_to_iq = false;
1128#endif
1129        } else if (inst->isNonSpeculative()) {
1130            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1131                    "encountered, skipping.\n", tid);
1132
1133            // Same as non-speculative stores.
1134            inst->setCanCommit();
1135
1136            // Specifically insert it as nonspeculative.
1137            instQueue.insertNonSpec(inst);
1138
1139            ++iewDispNonSpecInsts;
1140
1141            add_to_iq = false;
1142        } else if (inst->isNop()) {
1143            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1144                    "skipping.\n", tid);
1145
1146            inst->setIssued();
1147            inst->setExecuted();
1148            inst->setCanCommit();
1149
1150            instQueue.recordProducer(inst);
1151
1152            exeNop[tid]++;
1153
1154            add_to_iq = false;
1155        } else if (inst->isExecuted()) {
1156            assert(0 && "Instruction shouldn't be executed.\n");
1157            DPRINTF(IEW, "Issue: Executed branch encountered, "
1158                    "skipping.\n");
1159
1160            inst->setIssued();
1161            inst->setCanCommit();
1162
1163            instQueue.recordProducer(inst);
1164
1165            add_to_iq = false;
1166        } else {
1167            add_to_iq = true;
1168        }
1169
1170        // If the instruction queue is not full, then add the
1171        // instruction.
1172        if (add_to_iq) {
1173            instQueue.insert(inst);
1174        }
1175
1176        insts_to_dispatch.pop();
1177
1178        toRename->iewInfo[tid].dispatched++;
1179
1180        ++iewDispatchedInsts;
1181    }
1182
1183    if (!insts_to_dispatch.empty()) {
1184        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
1185        block(tid);
1186        toRename->iewUnblock[tid] = false;
1187    }
1188
1189    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1190        dispatchStatus[tid] = Running;
1191
1192        updatedQueues = true;
1193    }
1194
1195    dis_num_inst = 0;
1196}
1197
1198template <class Impl>
1199void
1200DefaultIEW<Impl>::printAvailableInsts()
1201{
1202    int inst = 0;
1203
1204    cout << "Available Instructions: ";
1205
1206    while (fromIssue->insts[inst]) {
1207
1208        if (inst%3==0) cout << "\n\t";
1209
1210        cout << "PC: " << fromIssue->insts[inst]->readPC()
1211             << " TN: " << fromIssue->insts[inst]->threadNumber
1212             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1213
1214        inst++;
1215
1216    }
1217
1218    cout << "\n";
1219}
1220
1221template <class Impl>
1222void
1223DefaultIEW<Impl>::executeInsts()
1224{
1225    wbNumInst = 0;
1226    wbCycle = 0;
1227
1228    list<unsigned>::iterator threads = (*activeThreads).begin();
1229
1230    while (threads != (*activeThreads).end()) {
1231        unsigned tid = *threads++;
1232        fetchRedirect[tid] = false;
1233    }
1234
1235#if 0
1236    printAvailableInsts();
1237#endif
1238
1239    // Execute/writeback any instructions that are available.
1240    int insts_to_execute = fromIssue->size;
1241    int inst_num = 0;
1242    for (; inst_num < insts_to_execute;
1243          ++inst_num) {
1244
1245        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1246
1247        DynInstPtr inst = instQueue.getInstToExecute();
1248
1249        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1250                inst->readPC(), inst->threadNumber,inst->seqNum);
1251
1252        // Check if the instruction is squashed; if so then skip it
1253        if (inst->isSquashed()) {
1254            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1255
1256            // Consider this instruction executed so that commit can go
1257            // ahead and retire the instruction.
1258            inst->setExecuted();
1259
1260            // Not sure if I should set this here or just let commit try to
1261            // commit any squashed instructions.  I like the latter a bit more.
1262            inst->setCanCommit();
1263
1264            ++iewExecSquashedInsts;
1265
1266            continue;
1267        }
1268
1269        Fault fault = NoFault;
1270
1271        // Execute instruction.
1272        // Note that if the instruction faults, it will be handled
1273        // at the commit stage.
1274        if (inst->isMemRef() &&
1275            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1276            DPRINTF(IEW, "Execute: Calculating address for memory "
1277                    "reference.\n");
1278
1279            // Tell the LDSTQ to execute this instruction (if it is a load).
1280            if (inst->isLoad()) {
1281                // Loads will mark themselves as executed, and their writeback
1282                // event adds the instruction to the queue to commit
1283                fault = ldstQueue.executeLoad(inst);
1284            } else if (inst->isStore()) {
1285                ldstQueue.executeStore(inst);
1286
1287                // If the store had a fault then it may not have a mem req
1288                if (inst->req && !(inst->req->flags & LOCKED)) {
1289                    inst->setExecuted();
1290
1291                    instToCommit(inst);
1292                }
1293
1294                // Store conditionals will mark themselves as
1295                // executed, and their writeback event will add the
1296                // instruction to the queue to commit.
1297            } else {
1298                panic("Unexpected memory type!\n");
1299            }
1300
1301        } else {
1302            inst->execute();
1303
1304            inst->setExecuted();
1305
1306            instToCommit(inst);
1307        }
1308
1309        updateExeInstStats(inst);
1310
1311        // Check if branch prediction was correct, if not then we need
1312        // to tell commit to squash in flight instructions.  Only
1313        // handle this if there hasn't already been something that
1314        // redirects fetch in this group of instructions.
1315
1316        // This probably needs to prioritize the redirects if a different
1317        // scheduler is used.  Currently the scheduler schedules the oldest
1318        // instruction first, so the branch resolution order will be correct.
1319        unsigned tid = inst->threadNumber;
1320
1321        if (!fetchRedirect[tid]) {
1322
1323            if (inst->mispredicted()) {
1324                fetchRedirect[tid] = true;
1325
1326                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1327                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1328                        inst->nextPC);
1329
1330                // If incorrect, then signal the ROB that it must be squashed.
1331                squashDueToBranch(inst, tid);
1332
1333                if (inst->predTaken()) {
1334                    predictedTakenIncorrect++;
1335                } else {
1336                    predictedNotTakenIncorrect++;
1337                }
1338            } else if (ldstQueue.violation(tid)) {
1339                fetchRedirect[tid] = true;
1340
1341                // If there was an ordering violation, then get the
1342                // DynInst that caused the violation.  Note that this
1343                // clears the violation signal.
1344                DynInstPtr violator;
1345                violator = ldstQueue.getMemDepViolator(tid);
1346
1347                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1348                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1349                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1350
1351                // Tell the instruction queue that a violation has occured.
1352                instQueue.violation(inst, violator);
1353
1354                // Squash.
1355                squashDueToMemOrder(inst,tid);
1356
1357                ++memOrderViolationEvents;
1358            } else if (ldstQueue.loadBlocked(tid) &&
1359                       !ldstQueue.isLoadBlockedHandled(tid)) {
1360                fetchRedirect[tid] = true;
1361
1362                DPRINTF(IEW, "Load operation couldn't execute because the "
1363                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1364                        inst->readPC(), inst->seqNum);
1365
1366                squashDueToMemBlocked(inst, tid);
1367            }
1368        }
1369    }
1370
1371    // Update and record activity if we processed any instructions.
1372    if (inst_num) {
1373        if (exeStatus == Idle) {
1374            exeStatus = Running;
1375        }
1376
1377        updatedQueues = true;
1378
1379        cpu->activityThisCycle();
1380    }
1381
1382    // Need to reset this in case a writeback event needs to write into the
1383    // iew queue.  That way the writeback event will write into the correct
1384    // spot in the queue.
1385    wbNumInst = 0;
1386}
1387
1388template <class Impl>
1389void
1390DefaultIEW<Impl>::writebackInsts()
1391{
1392    // Loop through the head of the time buffer and wake any
1393    // dependents.  These instructions are about to write back.  Also
1394    // mark scoreboard that this instruction is finally complete.
1395    // Either have IEW have direct access to scoreboard, or have this
1396    // as part of backwards communication.
1397    for (int inst_num = 0; inst_num < issueWidth &&
1398             toCommit->insts[inst_num]; inst_num++) {
1399        DynInstPtr inst = toCommit->insts[inst_num];
1400        int tid = inst->threadNumber;
1401
1402        DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
1403                inst->readPC());
1404
1405        iewInstsToCommit[tid]++;
1406
1407        // Some instructions will be sent to commit without having
1408        // executed because they need commit to handle them.
1409        // E.g. Uncached loads have not actually executed when they
1410        // are first sent to commit.  Instead commit must tell the LSQ
1411        // when it's ready to execute the uncached load.
1412        if (!inst->isSquashed() && inst->isExecuted()) {
1413            int dependents = instQueue.wakeDependents(inst);
1414
1415            for (int i = 0; i < inst->numDestRegs(); i++) {
1416                //mark as Ready
1417                DPRINTF(IEW,"Setting Destination Register %i\n",
1418                        inst->renamedDestRegIdx(i));
1419                scoreboard->setReg(inst->renamedDestRegIdx(i));
1420            }
1421
1422            if (dependents) {
1423                producerInst[tid]++;
1424                consumerInst[tid]+= dependents;
1425            }
1426            writebackCount[tid]++;
1427        }
1428    }
1429}
1430
1431template<class Impl>
1432void
1433DefaultIEW<Impl>::tick()
1434{
1435    wbNumInst = 0;
1436    wbCycle = 0;
1437
1438    wroteToTimeBuffer = false;
1439    updatedQueues = false;
1440
1441    sortInsts();
1442
1443    // Free function units marked as being freed this cycle.
1444    fuPool->processFreeUnits();
1445
1446    list<unsigned>::iterator threads = (*activeThreads).begin();
1447
1448    // Check stall and squash signals, dispatch any instructions.
1449    while (threads != (*activeThreads).end()) {
1450           unsigned tid = *threads++;
1451
1452        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1453
1454        checkSignalsAndUpdate(tid);
1455        dispatch(tid);
1456    }
1457
1458    if (exeStatus != Squashing) {
1459        executeInsts();
1460
1461        writebackInsts();
1462
1463        // Have the instruction queue try to schedule any ready instructions.
1464        // (In actuality, this scheduling is for instructions that will
1465        // be executed next cycle.)
1466        instQueue.scheduleReadyInsts();
1467
1468        // Also should advance its own time buffers if the stage ran.
1469        // Not the best place for it, but this works (hopefully).
1470        issueToExecQueue.advance();
1471    }
1472
1473    bool broadcast_free_entries = false;
1474
1475    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1476        exeStatus = Idle;
1477        updateLSQNextCycle = false;
1478
1479        broadcast_free_entries = true;
1480    }
1481
1482    // Writeback any stores using any leftover bandwidth.
1483    ldstQueue.writebackStores();
1484
1485    // Check the committed load/store signals to see if there's a load
1486    // or store to commit.  Also check if it's being told to execute a
1487    // nonspeculative instruction.
1488    // This is pretty inefficient...
1489
1490    threads = (*activeThreads).begin();
1491    while (threads != (*activeThreads).end()) {
1492        unsigned tid = (*threads++);
1493
1494        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1495
1496        // Update structures based on instructions committed.
1497        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1498            !fromCommit->commitInfo[tid].squash &&
1499            !fromCommit->commitInfo[tid].robSquashing) {
1500
1501            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1502
1503            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1504
1505            updateLSQNextCycle = true;
1506            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1507        }
1508
1509        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1510
1511            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1512            if (fromCommit->commitInfo[tid].uncached) {
1513                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1514            } else {
1515                instQueue.scheduleNonSpec(
1516                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1517            }
1518        }
1519
1520        if (broadcast_free_entries) {
1521            toFetch->iewInfo[tid].iqCount =
1522                instQueue.getCount(tid);
1523            toFetch->iewInfo[tid].ldstqCount =
1524                ldstQueue.getCount(tid);
1525
1526            toRename->iewInfo[tid].usedIQ = true;
1527            toRename->iewInfo[tid].freeIQEntries =
1528                instQueue.numFreeEntries();
1529            toRename->iewInfo[tid].usedLSQ = true;
1530            toRename->iewInfo[tid].freeLSQEntries =
1531                ldstQueue.numFreeEntries(tid);
1532
1533            wroteToTimeBuffer = true;
1534        }
1535
1536        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1537                tid, toRename->iewInfo[tid].dispatched);
1538    }
1539
1540    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1541            "LSQ has %i free entries.\n",
1542            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1543            ldstQueue.numFreeEntries());
1544
1545    updateStatus();
1546
1547    if (wroteToTimeBuffer) {
1548        DPRINTF(Activity, "Activity this cycle.\n");
1549        cpu->activityThisCycle();
1550    }
1551}
1552
1553template <class Impl>
1554void
1555DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1556{
1557    int thread_number = inst->threadNumber;
1558
1559    //
1560    //  Pick off the software prefetches
1561    //
1562#ifdef TARGET_ALPHA
1563    if (inst->isDataPrefetch())
1564        exeSwp[thread_number]++;
1565    else
1566        iewExecutedInsts++;
1567#else
1568    iewExecutedInsts[thread_number]++;
1569#endif
1570
1571    //
1572    //  Control operations
1573    //
1574    if (inst->isControl())
1575        exeBranches[thread_number]++;
1576
1577    //
1578    //  Memory operations
1579    //
1580    if (inst->isMemRef()) {
1581        exeRefs[thread_number]++;
1582
1583        if (inst->isLoad()) {
1584            iewExecLoadInsts[thread_number]++;
1585        }
1586    }
1587}
1588