iew_impl.hh revision 13652
11689SN/A/* 213590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2010-2013, 2018 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 7913453Srekai.gonzalezalberquilla@arm.com wbNumInst(0), 8013453Srekai.gonzalezalberquilla@arm.com wbCycle(0), 812820Sktlim@umich.edu wbWidth(params->wbWidth), 829444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 831060SN/A{ 8410172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8510172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8710172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8810172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8910172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 9010172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9110172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9210172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9310172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9510172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9610172Sdam.sunwoo@arm.com 972292SN/A _status = Active; 982292SN/A exeStatus = Running; 992292SN/A wbStatus = Idle; 1001060SN/A 1011060SN/A // Setup wire to read instructions coming from issue. 1021060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1031060SN/A 1041060SN/A // Instruction queue needs the queue between issue and execute. 1051060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1061681SN/A 10713453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1086221Snate@binkert.org dispatchStatus[tid] = Running; 1096221Snate@binkert.org fetchRedirect[tid] = false; 1102292SN/A } 1112292SN/A 1122292SN/A updateLSQNextCycle = false; 1132292SN/A 11410328Smitch.hayenga@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1152292SN/A} 1162292SN/A 1172292SN/Atemplate <class Impl> 1182292SN/Astd::string 1192292SN/ADefaultIEW<Impl>::name() const 1202292SN/A{ 1212292SN/A return cpu->name() + ".iew"; 1221060SN/A} 1231060SN/A 1241681SN/Atemplate <class Impl> 1251062SN/Avoid 12610023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 12710023Smatt.horsnell@ARM.com{ 12810023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12910023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13011246Sradhika.jagtap@ARM.com /** 13111246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13211246Sradhika.jagtap@ARM.com * an instruction starts to execute. 13311246Sradhika.jagtap@ARM.com */ 13411246Sradhika.jagtap@ARM.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13511246Sradhika.jagtap@ARM.com "Execute"); 13611246Sradhika.jagtap@ARM.com /** 13711246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13811246Sradhika.jagtap@ARM.com * an instruction execution completes and it is marked ready to commit. 13911246Sradhika.jagtap@ARM.com */ 14011246Sradhika.jagtap@ARM.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 14111246Sradhika.jagtap@ARM.com "ToCommit"); 14210023Smatt.horsnell@ARM.com} 14310023Smatt.horsnell@ARM.com 14410023Smatt.horsnell@ARM.comtemplate <class Impl> 14510023Smatt.horsnell@ARM.comvoid 1462292SN/ADefaultIEW<Impl>::regStats() 1471062SN/A{ 1482301SN/A using namespace Stats; 1492301SN/A 1501062SN/A instQueue.regStats(); 1512727Sktlim@umich.edu ldstQueue.regStats(); 1521062SN/A 1531062SN/A iewIdleCycles 1541062SN/A .name(name() + ".iewIdleCycles") 1551062SN/A .desc("Number of cycles IEW is idle"); 1561062SN/A 1571062SN/A iewSquashCycles 1581062SN/A .name(name() + ".iewSquashCycles") 1591062SN/A .desc("Number of cycles IEW is squashing"); 1601062SN/A 1611062SN/A iewBlockCycles 1621062SN/A .name(name() + ".iewBlockCycles") 1631062SN/A .desc("Number of cycles IEW is blocking"); 1641062SN/A 1651062SN/A iewUnblockCycles 1661062SN/A .name(name() + ".iewUnblockCycles") 1671062SN/A .desc("Number of cycles IEW is unblocking"); 1681062SN/A 1691062SN/A iewDispatchedInsts 1701062SN/A .name(name() + ".iewDispatchedInsts") 1711062SN/A .desc("Number of instructions dispatched to IQ"); 1721062SN/A 1731062SN/A iewDispSquashedInsts 1741062SN/A .name(name() + ".iewDispSquashedInsts") 1751062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1761062SN/A 1771062SN/A iewDispLoadInsts 1781062SN/A .name(name() + ".iewDispLoadInsts") 1791062SN/A .desc("Number of dispatched load instructions"); 1801062SN/A 1811062SN/A iewDispStoreInsts 1821062SN/A .name(name() + ".iewDispStoreInsts") 1831062SN/A .desc("Number of dispatched store instructions"); 1841062SN/A 1851062SN/A iewDispNonSpecInsts 1861062SN/A .name(name() + ".iewDispNonSpecInsts") 1871062SN/A .desc("Number of dispatched non-speculative instructions"); 1881062SN/A 1891062SN/A iewIQFullEvents 1901062SN/A .name(name() + ".iewIQFullEvents") 1911062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1921062SN/A 1932292SN/A iewLSQFullEvents 1942292SN/A .name(name() + ".iewLSQFullEvents") 1952292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1962292SN/A 1971062SN/A memOrderViolationEvents 1981062SN/A .name(name() + ".memOrderViolationEvents") 1991062SN/A .desc("Number of memory order violations"); 2001062SN/A 2011062SN/A predictedTakenIncorrect 2021062SN/A .name(name() + ".predictedTakenIncorrect") 2031062SN/A .desc("Number of branches that were predicted taken incorrectly"); 2042292SN/A 2052292SN/A predictedNotTakenIncorrect 2062292SN/A .name(name() + ".predictedNotTakenIncorrect") 2072292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2082292SN/A 2092292SN/A branchMispredicts 2102292SN/A .name(name() + ".branchMispredicts") 2112292SN/A .desc("Number of branch mispredicts detected at execute"); 2122292SN/A 2132292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2142301SN/A 2152727Sktlim@umich.edu iewExecutedInsts 2162353SN/A .name(name() + ".iewExecutedInsts") 2172727Sktlim@umich.edu .desc("Number of executed instructions"); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu iewExecLoadInsts 2206221Snate@binkert.org .init(cpu->numThreads) 2212353SN/A .name(name() + ".iewExecLoadInsts") 2222727Sktlim@umich.edu .desc("Number of load instructions executed") 2232727Sktlim@umich.edu .flags(total); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecSquashedInsts 2262353SN/A .name(name() + ".iewExecSquashedInsts") 2272727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu iewExecutedSwp 2306221Snate@binkert.org .init(cpu->numThreads) 2318240Snate@binkert.org .name(name() + ".exec_swp") 2322301SN/A .desc("number of swp insts executed") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352727Sktlim@umich.edu iewExecutedNop 2366221Snate@binkert.org .init(cpu->numThreads) 2378240Snate@binkert.org .name(name() + ".exec_nop") 2382301SN/A .desc("number of nop insts executed") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412727Sktlim@umich.edu iewExecutedRefs 2426221Snate@binkert.org .init(cpu->numThreads) 2438240Snate@binkert.org .name(name() + ".exec_refs") 2442301SN/A .desc("number of memory reference insts executed") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472727Sktlim@umich.edu iewExecutedBranches 2486221Snate@binkert.org .init(cpu->numThreads) 2498240Snate@binkert.org .name(name() + ".exec_branches") 2502301SN/A .desc("Number of branches executed") 2512727Sktlim@umich.edu .flags(total); 2522301SN/A 2532301SN/A iewExecStoreInsts 2548240Snate@binkert.org .name(name() + ".exec_stores") 2552301SN/A .desc("Number of stores executed") 2562727Sktlim@umich.edu .flags(total); 2572727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2582727Sktlim@umich.edu 2592727Sktlim@umich.edu iewExecRate 2608240Snate@binkert.org .name(name() + ".exec_rate") 2612727Sktlim@umich.edu .desc("Inst execution rate") 2622727Sktlim@umich.edu .flags(total); 2632727Sktlim@umich.edu 2642727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2652301SN/A 2662301SN/A iewInstsToCommit 2676221Snate@binkert.org .init(cpu->numThreads) 2688240Snate@binkert.org .name(name() + ".wb_sent") 2692301SN/A .desc("cumulative count of insts sent to commit") 2702727Sktlim@umich.edu .flags(total); 2712301SN/A 2722326SN/A writebackCount 2736221Snate@binkert.org .init(cpu->numThreads) 2748240Snate@binkert.org .name(name() + ".wb_count") 2752301SN/A .desc("cumulative count of insts written-back") 2762727Sktlim@umich.edu .flags(total); 2772301SN/A 2782326SN/A producerInst 2796221Snate@binkert.org .init(cpu->numThreads) 2808240Snate@binkert.org .name(name() + ".wb_producers") 2812301SN/A .desc("num instructions producing a value") 2822727Sktlim@umich.edu .flags(total); 2832301SN/A 2842326SN/A consumerInst 2856221Snate@binkert.org .init(cpu->numThreads) 2868240Snate@binkert.org .name(name() + ".wb_consumers") 2872301SN/A .desc("num instructions consuming a value") 2882727Sktlim@umich.edu .flags(total); 2892301SN/A 2902326SN/A wbFanout 2918240Snate@binkert.org .name(name() + ".wb_fanout") 2922301SN/A .desc("average fanout of values written-back") 2932727Sktlim@umich.edu .flags(total); 2942301SN/A 2952326SN/A wbFanout = producerInst / consumerInst; 2962301SN/A 2972326SN/A wbRate 2988240Snate@binkert.org .name(name() + ".wb_rate") 2992301SN/A .desc("insts written-back per cycle") 3002727Sktlim@umich.edu .flags(total); 3012326SN/A wbRate = writebackCount / cpu->numCycles; 3021062SN/A} 3031062SN/A 3041681SN/Atemplate<class Impl> 3051060SN/Avoid 3069427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3071060SN/A{ 3086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3092292SN/A toRename->iewInfo[tid].usedIQ = true; 3102292SN/A toRename->iewInfo[tid].freeIQEntries = 3112292SN/A instQueue.numFreeEntries(tid); 3122292SN/A 3132292SN/A toRename->iewInfo[tid].usedLSQ = true; 31410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3162292SN/A } 3172292SN/A 3188887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3198733Sgeoffrey.blake@arm.com if (cpu->checker) { 3208850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3218887Sgeoffrey.blake@arm.com } 3228733Sgeoffrey.blake@arm.com 3232733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3241060SN/A} 3251060SN/A 3261681SN/Atemplate<class Impl> 3271060SN/Avoid 32813641Sqtt2@cornell.eduDefaultIEW<Impl>::clearStates(ThreadID tid) 32913641Sqtt2@cornell.edu{ 33013641Sqtt2@cornell.edu toRename->iewInfo[tid].usedIQ = true; 33113641Sqtt2@cornell.edu toRename->iewInfo[tid].freeIQEntries = 33213641Sqtt2@cornell.edu instQueue.numFreeEntries(tid); 33313641Sqtt2@cornell.edu 33413641Sqtt2@cornell.edu toRename->iewInfo[tid].usedLSQ = true; 33513641Sqtt2@cornell.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 33613641Sqtt2@cornell.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 33713641Sqtt2@cornell.edu} 33813641Sqtt2@cornell.edu 33913641Sqtt2@cornell.edutemplate<class Impl> 34013641Sqtt2@cornell.eduvoid 3412292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3421060SN/A{ 3431060SN/A timeBuffer = tb_ptr; 3441060SN/A 3451060SN/A // Setup wire to read information from time buffer, from commit. 3461060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3471060SN/A 3481060SN/A // Setup wire to write information back to previous stages. 3491060SN/A toRename = timeBuffer->getWire(0); 3501060SN/A 3512292SN/A toFetch = timeBuffer->getWire(0); 3522292SN/A 3531060SN/A // Instruction queue also needs main time buffer. 3541060SN/A instQueue.setTimeBuffer(tb_ptr); 3551060SN/A} 3561060SN/A 3571681SN/Atemplate<class Impl> 3581060SN/Avoid 3592292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3601060SN/A{ 3611060SN/A renameQueue = rq_ptr; 3621060SN/A 3631060SN/A // Setup wire to read information from rename queue. 3641060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3651060SN/A} 3661060SN/A 3671681SN/Atemplate<class Impl> 3681060SN/Avoid 3692292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3701060SN/A{ 3711060SN/A iewQueue = iq_ptr; 3721060SN/A 3731060SN/A // Setup wire to write instructions to commit. 3741060SN/A toCommit = iewQueue->getWire(0); 3751060SN/A} 3761060SN/A 3771681SN/Atemplate<class Impl> 3781060SN/Avoid 3796221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3801060SN/A{ 3812292SN/A activeThreads = at_ptr; 3822292SN/A 3832292SN/A ldstQueue.setActiveThreads(at_ptr); 3842292SN/A instQueue.setActiveThreads(at_ptr); 3851060SN/A} 3861060SN/A 3871681SN/Atemplate<class Impl> 3881060SN/Avoid 3892292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3901060SN/A{ 3912292SN/A scoreboard = sb_ptr; 3921060SN/A} 3931060SN/A 3942307SN/Atemplate <class Impl> 3952863Sktlim@umich.edubool 3969444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3972307SN/A{ 39810510Smitch.hayenga@arm.com bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3999444SAndreas.Sandberg@ARM.com 4009444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 4019444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 4029444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 4039444SAndreas.Sandberg@ARM.com drained = false; 4049444SAndreas.Sandberg@ARM.com } 4059444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 4069444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 4079444SAndreas.Sandberg@ARM.com drained = false; 4089444SAndreas.Sandberg@ARM.com } 40911650Srekai.gonzalezalberquilla@arm.com drained = drained && dispatchStatus[tid] == Running; 4109444SAndreas.Sandberg@ARM.com } 4119444SAndreas.Sandberg@ARM.com 4129783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4139783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4149783Sandreas.hansson@arm.com // above 4159783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4169783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4179783Sandreas.hansson@arm.com drained = false; 4189783Sandreas.hansson@arm.com } 4199783Sandreas.hansson@arm.com 4209444SAndreas.Sandberg@ARM.com return drained; 4211681SN/A} 4221681SN/A 4232316SN/Atemplate <class Impl> 4241681SN/Avoid 4259444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4262843Sktlim@umich.edu{ 4279444SAndreas.Sandberg@ARM.com assert(isDrained()); 4282843Sktlim@umich.edu 4299444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4309444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4311681SN/A} 4321681SN/A 4332307SN/Atemplate <class Impl> 4341681SN/Avoid 4352307SN/ADefaultIEW<Impl>::takeOverFrom() 4361060SN/A{ 4372348SN/A // Reset all state. 4382307SN/A _status = Active; 4392307SN/A exeStatus = Running; 4402307SN/A wbStatus = Idle; 4411060SN/A 4422307SN/A instQueue.takeOverFrom(); 4432307SN/A ldstQueue.takeOverFrom(); 4449444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4451060SN/A 4469427SAndreas.Sandberg@ARM.com startupStage(); 4472307SN/A cpu->activityThisCycle(); 4481060SN/A 4496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4506221Snate@binkert.org dispatchStatus[tid] = Running; 4516221Snate@binkert.org fetchRedirect[tid] = false; 4522307SN/A } 4531060SN/A 4542307SN/A updateLSQNextCycle = false; 4552307SN/A 4562873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4572307SN/A issueToExecQueue.advance(); 4581060SN/A } 4591060SN/A} 4601060SN/A 4611681SN/Atemplate<class Impl> 4621060SN/Avoid 4636221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4642107SN/A{ 4656221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4662107SN/A 4672292SN/A // Tell the IQ to start squashing. 4682292SN/A instQueue.squash(tid); 4692107SN/A 4702292SN/A // Tell the LDSTQ to start squashing. 4712326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4722292SN/A updatedQueues = true; 4732107SN/A 4742292SN/A // Clear the skid buffer in case it has any data in it. 4752935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4764632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4772935Sksewell@umich.edu 4782292SN/A while (!skidBuffer[tid].empty()) { 47910239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 48010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 48110239Sbinhpham@cs.rutgers.edu } 48213652Sqtt2@cornell.edu if (skidBuffer[tid].front()->isStore() || 48313652Sqtt2@cornell.edu skidBuffer[tid].front()->isAtomic()) { 48410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4852292SN/A } 4862107SN/A 4872292SN/A toRename->iewInfo[tid].dispatched++; 4882107SN/A 4892292SN/A skidBuffer[tid].pop(); 4902292SN/A } 4912107SN/A 4922702Sktlim@umich.edu emptyRenameInsts(tid); 4932107SN/A} 4942107SN/A 4952107SN/Atemplate<class Impl> 4962107SN/Avoid 49713429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 4982292SN/A{ 4997720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 5007720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5012292SN/A 50210231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5037852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5047852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5057852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5067852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 5072935Sksewell@umich.edu 5087852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 5097852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 5102292SN/A 5117852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 5127852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 5137852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5142292SN/A 5157852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5167852SMatt.Horsnell@arm.com } 5177852SMatt.Horsnell@arm.com 5182292SN/A} 5192292SN/A 5202292SN/Atemplate<class Impl> 5212292SN/Avoid 52213429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5232292SN/A{ 5248513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5258513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5268513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5278513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5288513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5298513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5308513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5318513SGiacomo.Gabrielli@arm.com // the squash. 53210231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5338513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5348513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5352292SN/A 5367852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5378513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5388137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5392292SN/A 5408513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5418513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5422292SN/A 5437852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5447852SMatt.Horsnell@arm.com } 5452292SN/A} 5462292SN/A 5472292SN/Atemplate<class Impl> 5482292SN/Avoid 5496221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5502292SN/A{ 5512292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5522292SN/A 5532292SN/A if (dispatchStatus[tid] != Blocked && 5542292SN/A dispatchStatus[tid] != Unblocking) { 5552292SN/A toRename->iewBlock[tid] = true; 5562292SN/A wroteToTimeBuffer = true; 5572292SN/A } 5582292SN/A 5592292SN/A // Add the current inputs to the skid buffer so they can be 5602292SN/A // reprocessed when this stage unblocks. 5612292SN/A skidInsert(tid); 5622292SN/A 5632292SN/A dispatchStatus[tid] = Blocked; 5642292SN/A} 5652292SN/A 5662292SN/Atemplate<class Impl> 5672292SN/Avoid 5686221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5692292SN/A{ 5702292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5712292SN/A "buffer %u.\n",tid, tid); 5722292SN/A 5732292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5742292SN/A // Also switch status to running. 5752292SN/A if (skidBuffer[tid].empty()) { 5762292SN/A toRename->iewUnblock[tid] = true; 5772292SN/A wroteToTimeBuffer = true; 5782292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5792292SN/A dispatchStatus[tid] = Running; 5802292SN/A } 5812292SN/A} 5822292SN/A 5832292SN/Atemplate<class Impl> 5842292SN/Avoid 58513429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5861060SN/A{ 5871681SN/A instQueue.wakeDependents(inst); 5881060SN/A} 5891060SN/A 5902292SN/Atemplate<class Impl> 5912292SN/Avoid 59213429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5932292SN/A{ 5942292SN/A instQueue.rescheduleMemInst(inst); 5952292SN/A} 5961681SN/A 5971681SN/Atemplate<class Impl> 5981060SN/Avoid 59913429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 6001060SN/A{ 6012292SN/A instQueue.replayMemInst(inst); 6022292SN/A} 6031060SN/A 6042292SN/Atemplate<class Impl> 6052292SN/Avoid 60613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 60710333Smitch.hayenga@arm.com{ 60810333Smitch.hayenga@arm.com instQueue.blockMemInst(inst); 60910333Smitch.hayenga@arm.com} 61010333Smitch.hayenga@arm.com 61110333Smitch.hayenga@arm.comtemplate<class Impl> 61210333Smitch.hayenga@arm.comvoid 61310333Smitch.hayenga@arm.comDefaultIEW<Impl>::cacheUnblocked() 61410333Smitch.hayenga@arm.com{ 61510333Smitch.hayenga@arm.com instQueue.cacheUnblocked(); 61610333Smitch.hayenga@arm.com} 61710333Smitch.hayenga@arm.com 61810333Smitch.hayenga@arm.comtemplate<class Impl> 61910333Smitch.hayenga@arm.comvoid 62013429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6212292SN/A{ 6223221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6233221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6243221Sktlim@umich.edu // being added to the queue to commit without being processed by 6253221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6263221Sktlim@umich.edu 6272292SN/A // First check the time slot that this instruction will write 6282292SN/A // to. If there are free write ports at the time, then go ahead 6292292SN/A // and write the instruction to that time. If there are not, 6302292SN/A // keep looking back to see where's the first time there's a 6312326SN/A // free slot. 6322292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6332292SN/A ++wbNumInst; 6342820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6352292SN/A ++wbCycle; 6362292SN/A wbNumInst = 0; 6372292SN/A } 6382292SN/A } 6392292SN/A 6402353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6412353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6422292SN/A // Add finished instruction to queue to commit. 6432292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6442292SN/A (*iewQueue)[wbCycle].size++; 6452292SN/A} 6462292SN/A 6472292SN/Atemplate <class Impl> 6482292SN/Aunsigned 6492292SN/ADefaultIEW<Impl>::validInstsFromRename() 6502292SN/A{ 6512292SN/A unsigned inst_count = 0; 6522292SN/A 6532292SN/A for (int i=0; i<fromRename->size; i++) { 6542731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6552292SN/A inst_count++; 6562292SN/A } 6572292SN/A 6582292SN/A return inst_count; 6592292SN/A} 6602292SN/A 6612292SN/Atemplate<class Impl> 6622292SN/Avoid 6636221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6642292SN/A{ 6652292SN/A DynInstPtr inst = NULL; 6662292SN/A 6672292SN/A while (!insts[tid].empty()) { 6682292SN/A inst = insts[tid].front(); 6692292SN/A 6702292SN/A insts[tid].pop(); 6712292SN/A 6729937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6732292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6747720Sgblack@eecs.umich.edu inst->pcState(),tid); 6752292SN/A 6762292SN/A skidBuffer[tid].push(inst); 6772292SN/A } 6782292SN/A 6792292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6802292SN/A "Skidbuffer Exceeded Max Size"); 6812292SN/A} 6822292SN/A 6832292SN/Atemplate<class Impl> 6842292SN/Aint 6852292SN/ADefaultIEW<Impl>::skidCount() 6862292SN/A{ 6872292SN/A int max=0; 6882292SN/A 6896221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6906221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6912292SN/A 6923867Sbinkertn@umich.edu while (threads != end) { 6936221Snate@binkert.org ThreadID tid = *threads++; 6943867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6952292SN/A if (max < thread_count) 6962292SN/A max = thread_count; 6972292SN/A } 6982292SN/A 6992292SN/A return max; 7002292SN/A} 7012292SN/A 7022292SN/Atemplate<class Impl> 7032292SN/Abool 7042292SN/ADefaultIEW<Impl>::skidsEmpty() 7052292SN/A{ 7066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7076221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7082292SN/A 7093867Sbinkertn@umich.edu while (threads != end) { 7106221Snate@binkert.org ThreadID tid = *threads++; 7113867Sbinkertn@umich.edu 7123867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7132292SN/A return false; 7142292SN/A } 7152292SN/A 7162292SN/A return true; 7171062SN/A} 7181062SN/A 7191681SN/Atemplate <class Impl> 7201062SN/Avoid 7212292SN/ADefaultIEW<Impl>::updateStatus() 7221062SN/A{ 7232292SN/A bool any_unblocking = false; 7241062SN/A 7256221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7266221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7271062SN/A 7283867Sbinkertn@umich.edu while (threads != end) { 7296221Snate@binkert.org ThreadID tid = *threads++; 7301062SN/A 7312292SN/A if (dispatchStatus[tid] == Unblocking) { 7322292SN/A any_unblocking = true; 7332292SN/A break; 7342292SN/A } 7352292SN/A } 7361062SN/A 7372292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7382292SN/A // and there's no stores waiting to write back, and dispatch is not 7392292SN/A // unblocking, then there is no internal activity for the IEW stage. 7407897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7412292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7422292SN/A !ldstQueue.willWB() && !any_unblocking) { 7432292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7441062SN/A 7452292SN/A deactivateStage(); 7461062SN/A 7472292SN/A _status = Inactive; 7482292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7492292SN/A ldstQueue.willWB() || 7502292SN/A any_unblocking)) { 7512292SN/A // Otherwise there is internal activity. Set to active. 7522292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7531062SN/A 7542292SN/A activateStage(); 7551062SN/A 7562292SN/A _status = Active; 7571062SN/A } 7581062SN/A} 7591062SN/A 7601681SN/Atemplate <class Impl> 7612292SN/Abool 7626221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7632292SN/A{ 7642292SN/A bool ret_val(false); 7652292SN/A 76610328Smitch.hayenga@arm.com if (fromCommit->commitInfo[tid].robSquashing) { 7672292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7682292SN/A ret_val = true; 7692292SN/A } else if (instQueue.isFull(tid)) { 7702292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7712292SN/A ret_val = true; 7722292SN/A } 7732292SN/A 7742292SN/A return ret_val; 7752292SN/A} 7762292SN/A 7772292SN/Atemplate <class Impl> 7782292SN/Avoid 7796221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7802292SN/A{ 7812292SN/A // Check if there's a squash signal, squash if there is 7822292SN/A // Check stall signals, block if there is. 7832292SN/A // If status was Blocked 7842292SN/A // if so then go to unblocking 7852292SN/A // If status was Squashing 7862292SN/A // check if squashing is not high. Switch to running this cycle. 7872292SN/A 7882292SN/A if (fromCommit->commitInfo[tid].squash) { 7892292SN/A squash(tid); 7902292SN/A 7912292SN/A if (dispatchStatus[tid] == Blocked || 7922292SN/A dispatchStatus[tid] == Unblocking) { 7932292SN/A toRename->iewUnblock[tid] = true; 7942292SN/A wroteToTimeBuffer = true; 7952292SN/A } 7962292SN/A 7972292SN/A dispatchStatus[tid] = Squashing; 7982292SN/A fetchRedirect[tid] = false; 7992292SN/A return; 8002292SN/A } 8012292SN/A 8022292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8032702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8042292SN/A 8052292SN/A dispatchStatus[tid] = Squashing; 8062702Sktlim@umich.edu emptyRenameInsts(tid); 8072702Sktlim@umich.edu wroteToTimeBuffer = true; 8082292SN/A } 8092292SN/A 8102292SN/A if (checkStall(tid)) { 8112292SN/A block(tid); 8122292SN/A dispatchStatus[tid] = Blocked; 8132292SN/A return; 8142292SN/A } 8152292SN/A 8162292SN/A if (dispatchStatus[tid] == Blocked) { 8172292SN/A // Status from previous cycle was blocked, but there are no more stall 8182292SN/A // conditions. Switch over to unblocking. 8192292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8202292SN/A tid); 8212292SN/A 8222292SN/A dispatchStatus[tid] = Unblocking; 8232292SN/A 8242292SN/A unblock(tid); 8252292SN/A 8262292SN/A return; 8272292SN/A } 8282292SN/A 8292292SN/A if (dispatchStatus[tid] == Squashing) { 8302292SN/A // Switch status to running if rename isn't being told to block or 8312292SN/A // squash this cycle. 8322292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8332292SN/A tid); 8342292SN/A 8352292SN/A dispatchStatus[tid] = Running; 8362292SN/A 8372292SN/A return; 8382292SN/A } 8392292SN/A} 8402292SN/A 8412292SN/Atemplate <class Impl> 8422292SN/Avoid 8432292SN/ADefaultIEW<Impl>::sortInsts() 8442292SN/A{ 8452292SN/A int insts_from_rename = fromRename->size; 8462326SN/A#ifdef DEBUG 8476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8486221Snate@binkert.org assert(insts[tid].empty()); 8492326SN/A#endif 8502292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8512292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8522292SN/A } 8532292SN/A} 8542292SN/A 8552292SN/Atemplate <class Impl> 8562292SN/Avoid 8576221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8582702Sktlim@umich.edu{ 8594632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8602935Sksewell@umich.edu 8612702Sktlim@umich.edu while (!insts[tid].empty()) { 8622935Sksewell@umich.edu 86310239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 86410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 86510239Sbinhpham@cs.rutgers.edu } 86613652Sqtt2@cornell.edu if (insts[tid].front()->isStore() || 86713652Sqtt2@cornell.edu insts[tid].front()->isAtomic()) { 86810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 8692702Sktlim@umich.edu } 8702702Sktlim@umich.edu 8712702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8722702Sktlim@umich.edu 8732702Sktlim@umich.edu insts[tid].pop(); 8742702Sktlim@umich.edu } 8752702Sktlim@umich.edu} 8762702Sktlim@umich.edu 8772702Sktlim@umich.edutemplate <class Impl> 8782702Sktlim@umich.eduvoid 8792292SN/ADefaultIEW<Impl>::wakeCPU() 8802292SN/A{ 8812292SN/A cpu->wakeCPU(); 8822292SN/A} 8832292SN/A 8842292SN/Atemplate <class Impl> 8852292SN/Avoid 8862292SN/ADefaultIEW<Impl>::activityThisCycle() 8872292SN/A{ 8882292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8892292SN/A cpu->activityThisCycle(); 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932292SN/Ainline void 8942292SN/ADefaultIEW<Impl>::activateStage() 8952292SN/A{ 8962292SN/A DPRINTF(Activity, "Activating stage.\n"); 8972733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Ainline void 9022292SN/ADefaultIEW<Impl>::deactivateStage() 9032292SN/A{ 9042292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9052733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9062292SN/A} 9072292SN/A 9082292SN/Atemplate<class Impl> 9092292SN/Avoid 9106221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9112292SN/A{ 9122292SN/A // If status is Running or idle, 9132292SN/A // call dispatchInsts() 9142292SN/A // If status is Unblocking, 9152292SN/A // buffer any instructions coming from rename 9162292SN/A // continue trying to empty skid buffer 9172292SN/A // check if stall conditions have passed 9182292SN/A 9192292SN/A if (dispatchStatus[tid] == Blocked) { 9202292SN/A ++iewBlockCycles; 9212292SN/A 9222292SN/A } else if (dispatchStatus[tid] == Squashing) { 9232292SN/A ++iewSquashCycles; 9242292SN/A } 9252292SN/A 9262292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9272292SN/A // will allow, as long as it is not currently blocked. 9282292SN/A if (dispatchStatus[tid] == Running || 9292292SN/A dispatchStatus[tid] == Idle) { 9302292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9312292SN/A "dispatch.\n", tid); 9322292SN/A 9332292SN/A dispatchInsts(tid); 9342292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9352292SN/A // Make sure that the skid buffer has something in it if the 9362292SN/A // status is unblocking. 9372292SN/A assert(!skidsEmpty()); 9382292SN/A 9392292SN/A // If the status was unblocking, then instructions from the skid 9402292SN/A // buffer were used. Remove those instructions and handle 9412292SN/A // the rest of unblocking. 9422292SN/A dispatchInsts(tid); 9432292SN/A 9442292SN/A ++iewUnblockCycles; 9452292SN/A 9465215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9472292SN/A // Add the current inputs to the skid buffer so they can be 9482292SN/A // reprocessed when this stage unblocks. 9492292SN/A skidInsert(tid); 9502292SN/A } 9512292SN/A 9522292SN/A unblock(tid); 9532292SN/A } 9542292SN/A} 9552292SN/A 9562292SN/Atemplate <class Impl> 9572292SN/Avoid 9586221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9592292SN/A{ 9602292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9612292SN/A // otherwise. 9622292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9632292SN/A dispatchStatus[tid] == Unblocking ? 9642292SN/A skidBuffer[tid] : insts[tid]; 9652292SN/A 9662292SN/A int insts_to_add = insts_to_dispatch.size(); 9672292SN/A 9682292SN/A DynInstPtr inst; 9692292SN/A bool add_to_iq = false; 9702292SN/A int dis_num_inst = 0; 9712292SN/A 9722292SN/A // Loop through the instructions, putting them in the instruction 9732292SN/A // queue. 9742292SN/A for ( ; dis_num_inst < insts_to_add && 9752820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9762292SN/A ++dis_num_inst) 9772292SN/A { 9782292SN/A inst = insts_to_dispatch.front(); 9792292SN/A 9802292SN/A if (dispatchStatus[tid] == Unblocking) { 9812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9822292SN/A "buffer\n", tid); 9832292SN/A } 9842292SN/A 9852292SN/A // Make sure there's a valid instruction there. 9862292SN/A assert(inst); 9872292SN/A 9887720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9892292SN/A "IQ.\n", 9907720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9912292SN/A 9922292SN/A // Be sure to mark these instructions as ready so that the 9932292SN/A // commit stage can go ahead and execute them, and mark 9942292SN/A // them as issued so the IQ doesn't reprocess them. 9952292SN/A 9962292SN/A // Check for squashed instructions. 9972292SN/A if (inst->isSquashed()) { 9982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9992292SN/A "not adding to IQ.\n", tid); 10002292SN/A 10012292SN/A ++iewDispSquashedInsts; 10022292SN/A 10032292SN/A insts_to_dispatch.pop(); 10042292SN/A 10052292SN/A //Tell Rename That An Instruction has been processed 100610239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 100710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10082292SN/A } 100913652Sqtt2@cornell.edu if (inst->isStore() || inst->isAtomic()) { 101010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 101110239Sbinhpham@cs.rutgers.edu } 101210239Sbinhpham@cs.rutgers.edu 10132292SN/A toRename->iewInfo[tid].dispatched++; 10142292SN/A 10152292SN/A continue; 10162292SN/A } 10172292SN/A 10182292SN/A // Check for full conditions. 10192292SN/A if (instQueue.isFull(tid)) { 10202292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10212292SN/A 10222292SN/A // Call function to start blocking. 10232292SN/A block(tid); 10242292SN/A 10252292SN/A // Set unblock to false. Special case where we are using 10262292SN/A // skidbuffer (unblocking) instructions but then we still 10272292SN/A // get full in the IQ. 10282292SN/A toRename->iewUnblock[tid] = false; 10292292SN/A 10302292SN/A ++iewIQFullEvents; 10312292SN/A break; 103210240Sbinhpham@cs.rutgers.edu } 103310240Sbinhpham@cs.rutgers.edu 103410240Sbinhpham@cs.rutgers.edu // Check LSQ if inst is LD/ST 103513652Sqtt2@cornell.edu if ((inst->isAtomic() && ldstQueue.sqFull(tid)) || 103613652Sqtt2@cornell.edu (inst->isLoad() && ldstQueue.lqFull(tid)) || 103710240Sbinhpham@cs.rutgers.edu (inst->isStore() && ldstQueue.sqFull(tid))) { 103810240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 103910240Sbinhpham@cs.rutgers.edu inst->isLoad() ? "LQ" : "SQ"); 10402292SN/A 10412292SN/A // Call function to start blocking. 10422292SN/A block(tid); 10432292SN/A 10442292SN/A // Set unblock to false. Special case where we are using 10452292SN/A // skidbuffer (unblocking) instructions but then we still 10462292SN/A // get full in the IQ. 10472292SN/A toRename->iewUnblock[tid] = false; 10482292SN/A 10492292SN/A ++iewLSQFullEvents; 10502292SN/A break; 10512292SN/A } 10522292SN/A 10532292SN/A // Otherwise issue the instruction just fine. 105413652Sqtt2@cornell.edu if (inst->isAtomic()) { 105513652Sqtt2@cornell.edu DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 105613652Sqtt2@cornell.edu "encountered, adding to LSQ.\n", tid); 105713652Sqtt2@cornell.edu 105813652Sqtt2@cornell.edu ldstQueue.insertStore(inst); 105913652Sqtt2@cornell.edu 106013652Sqtt2@cornell.edu ++iewDispStoreInsts; 106113652Sqtt2@cornell.edu 106213652Sqtt2@cornell.edu // AMOs need to be set as "canCommit()" 106313652Sqtt2@cornell.edu // so that commit can process them when they reach the 106413652Sqtt2@cornell.edu // head of commit. 106513652Sqtt2@cornell.edu inst->setCanCommit(); 106613652Sqtt2@cornell.edu instQueue.insertNonSpec(inst); 106713652Sqtt2@cornell.edu add_to_iq = false; 106813652Sqtt2@cornell.edu 106913652Sqtt2@cornell.edu ++iewDispNonSpecInsts; 107013652Sqtt2@cornell.edu 107113652Sqtt2@cornell.edu toRename->iewInfo[tid].dispatchedToSQ++; 107213652Sqtt2@cornell.edu } else if (inst->isLoad()) { 10732292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10742292SN/A "encountered, adding to LSQ.\n", tid); 10752292SN/A 10762292SN/A // Reserve a spot in the load store queue for this 10772292SN/A // memory access. 10782292SN/A ldstQueue.insertLoad(inst); 10792292SN/A 10802292SN/A ++iewDispLoadInsts; 10812292SN/A 10822292SN/A add_to_iq = true; 10832292SN/A 108410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10852292SN/A } else if (inst->isStore()) { 10862292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10872292SN/A "encountered, adding to LSQ.\n", tid); 10882292SN/A 10892292SN/A ldstQueue.insertStore(inst); 10902292SN/A 10912292SN/A ++iewDispStoreInsts; 10922292SN/A 10932336SN/A if (inst->isStoreConditional()) { 10942336SN/A // Store conditionals need to be set as "canCommit()" 10952336SN/A // so that commit can process them when they reach the 10962336SN/A // head of commit. 10972348SN/A // @todo: This is somewhat specific to Alpha. 10982292SN/A inst->setCanCommit(); 10992292SN/A instQueue.insertNonSpec(inst); 11002292SN/A add_to_iq = false; 11012292SN/A 11022292SN/A ++iewDispNonSpecInsts; 11032292SN/A } else { 11042292SN/A add_to_iq = true; 11052292SN/A } 11062292SN/A 110710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 11082292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11092326SN/A // Same as non-speculative stores. 11102292SN/A inst->setCanCommit(); 11112292SN/A instQueue.insertBarrier(inst); 11122292SN/A add_to_iq = false; 11132292SN/A } else if (inst->isNop()) { 11142292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11152292SN/A "skipping.\n", tid); 11162292SN/A 11172292SN/A inst->setIssued(); 11182292SN/A inst->setExecuted(); 11192292SN/A inst->setCanCommit(); 11202292SN/A 11212326SN/A instQueue.recordProducer(inst); 11222292SN/A 11232727Sktlim@umich.edu iewExecutedNop[tid]++; 11242301SN/A 11252292SN/A add_to_iq = false; 11262292SN/A } else { 112710733Snilay@cs.wisc.edu assert(!inst->isExecuted()); 11282292SN/A add_to_iq = true; 11292292SN/A } 113010733Snilay@cs.wisc.edu 113112537Sandreas.sandberg@arm.com if (add_to_iq && inst->isNonSpeculative()) { 11324033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11334033Sktlim@umich.edu "encountered, skipping.\n", tid); 11344033Sktlim@umich.edu 11354033Sktlim@umich.edu // Same as non-speculative stores. 11364033Sktlim@umich.edu inst->setCanCommit(); 11374033Sktlim@umich.edu 11384033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11394033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11404033Sktlim@umich.edu 11414033Sktlim@umich.edu ++iewDispNonSpecInsts; 11424033Sktlim@umich.edu 11434033Sktlim@umich.edu add_to_iq = false; 11444033Sktlim@umich.edu } 11452292SN/A 11462292SN/A // If the instruction queue is not full, then add the 11472292SN/A // instruction. 11482292SN/A if (add_to_iq) { 11492292SN/A instQueue.insert(inst); 11502292SN/A } 11512292SN/A 11522292SN/A insts_to_dispatch.pop(); 11532292SN/A 11542292SN/A toRename->iewInfo[tid].dispatched++; 11552292SN/A 11562292SN/A ++iewDispatchedInsts; 11578471SGiacomo.Gabrielli@arm.com 11588471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11599046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11608471SGiacomo.Gabrielli@arm.com#endif 116110023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11622292SN/A } 11632292SN/A 11642292SN/A if (!insts_to_dispatch.empty()) { 11652935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11662292SN/A block(tid); 11672292SN/A toRename->iewUnblock[tid] = false; 11682292SN/A } 11692292SN/A 11702292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11712292SN/A dispatchStatus[tid] = Running; 11722292SN/A 11732292SN/A updatedQueues = true; 11742292SN/A } 11752292SN/A 11762292SN/A dis_num_inst = 0; 11772292SN/A} 11782292SN/A 11792292SN/Atemplate <class Impl> 11802292SN/Avoid 11812292SN/ADefaultIEW<Impl>::printAvailableInsts() 11822292SN/A{ 11832292SN/A int inst = 0; 11842292SN/A 11852980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11862292SN/A 11872292SN/A while (fromIssue->insts[inst]) { 11882292SN/A 11892980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11902292SN/A 11917720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11922292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11932292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11942292SN/A 11952292SN/A inst++; 11962292SN/A 11972292SN/A } 11982292SN/A 11992980Sgblack@eecs.umich.edu std::cout << "\n"; 12002292SN/A} 12012292SN/A 12022292SN/Atemplate <class Impl> 12032292SN/Avoid 12042292SN/ADefaultIEW<Impl>::executeInsts() 12052292SN/A{ 12062292SN/A wbNumInst = 0; 12072292SN/A wbCycle = 0; 12082292SN/A 12096221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12106221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12112292SN/A 12123867Sbinkertn@umich.edu while (threads != end) { 12136221Snate@binkert.org ThreadID tid = *threads++; 12142292SN/A fetchRedirect[tid] = false; 12152292SN/A } 12162292SN/A 12172698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12187599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12192698Sktlim@umich.edu// printAvailableInsts(); 12201062SN/A 12211062SN/A // Execute/writeback any instructions that are available. 12222333SN/A int insts_to_execute = fromIssue->size; 12232292SN/A int inst_num = 0; 12242333SN/A for (; inst_num < insts_to_execute; 12252326SN/A ++inst_num) { 12261062SN/A 12272292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12281062SN/A 12292333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12301062SN/A 12317720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12327720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12331062SN/A 123411246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction has started 123511246Sradhika.jagtap@ARM.com // executing 123611246Sradhika.jagtap@ARM.com ppExecute->notify(inst); 123711246Sradhika.jagtap@ARM.com 12381062SN/A // Check if the instruction is squashed; if so then skip it 12391062SN/A if (inst->isSquashed()) { 12408315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12418315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12428315Sgeoffrey.blake@arm.com inst->seqNum); 12431062SN/A 12441062SN/A // Consider this instruction executed so that commit can go 12451062SN/A // ahead and retire the instruction. 12461062SN/A inst->setExecuted(); 12471062SN/A 12482292SN/A // Not sure if I should set this here or just let commit try to 12492292SN/A // commit any squashed instructions. I like the latter a bit more. 12502292SN/A inst->setCanCommit(); 12511062SN/A 12521062SN/A ++iewExecSquashedInsts; 12531062SN/A 12541062SN/A continue; 12551062SN/A } 12561062SN/A 12572292SN/A Fault fault = NoFault; 12581062SN/A 12591062SN/A // Execute instruction. 12601062SN/A // Note that if the instruction faults, it will be handled 12611062SN/A // at the commit stage. 12627850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12632292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12641062SN/A "reference.\n"); 12651062SN/A 12661062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 126713652Sqtt2@cornell.edu if (inst->isAtomic()) { 126813652Sqtt2@cornell.edu // AMOs are treated like store requests 126913652Sqtt2@cornell.edu fault = ldstQueue.executeStore(inst); 127013652Sqtt2@cornell.edu 127113652Sqtt2@cornell.edu if (inst->isTranslationDelayed() && 127213652Sqtt2@cornell.edu fault == NoFault) { 127313652Sqtt2@cornell.edu // A hw page table walk is currently going on; the 127413652Sqtt2@cornell.edu // instruction must be deferred. 127513652Sqtt2@cornell.edu DPRINTF(IEW, "Execute: Delayed translation, deferring " 127613652Sqtt2@cornell.edu "store.\n"); 127713652Sqtt2@cornell.edu instQueue.deferMemInst(inst); 127813652Sqtt2@cornell.edu continue; 127913652Sqtt2@cornell.edu } 128013652Sqtt2@cornell.edu } else if (inst->isLoad()) { 12812292SN/A // Loads will mark themselves as executed, and their writeback 12822292SN/A // event adds the instruction to the queue to commit 12832292SN/A fault = ldstQueue.executeLoad(inst); 12847944SGiacomo.Gabrielli@arm.com 12857944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12867944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12877944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12887944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12897944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12907944SGiacomo.Gabrielli@arm.com "load.\n"); 12917944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12927944SGiacomo.Gabrielli@arm.com continue; 12937944SGiacomo.Gabrielli@arm.com } 12947944SGiacomo.Gabrielli@arm.com 12957850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12968073SAli.Saidi@ARM.com inst->fault = NoFault; 12977850SMatt.Horsnell@arm.com } 12981062SN/A } else if (inst->isStore()) { 12992367SN/A fault = ldstQueue.executeStore(inst); 13001062SN/A 13017944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 13027944SGiacomo.Gabrielli@arm.com fault == NoFault) { 13037944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 13047944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 13057944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 13067944SGiacomo.Gabrielli@arm.com "store.\n"); 13077944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13087944SGiacomo.Gabrielli@arm.com continue; 13097944SGiacomo.Gabrielli@arm.com } 13107944SGiacomo.Gabrielli@arm.com 13112292SN/A // If the store had a fault then it may not have a mem req 131210231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 13137782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 13147782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 13157782Sminkyu.jeong@arm.com // to commit without the instruction completing. 13162367SN/A // Send this instruction to commit, also make sure iew stage 13172367SN/A // realizes there is activity. 13182367SN/A inst->setExecuted(); 13192367SN/A instToCommit(inst); 13202367SN/A activityThisCycle(); 13212292SN/A } 13222326SN/A 13232326SN/A // Store conditionals will mark themselves as 13242326SN/A // executed, and their writeback event will add the 13252326SN/A // instruction to the queue to commit. 13261062SN/A } else { 13272292SN/A panic("Unexpected memory type!\n"); 13281062SN/A } 13291062SN/A 13301062SN/A } else { 13317847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13327847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13337847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13347847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13357847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13367847Sminkyu.jeong@arm.com inst->execute(); 133710231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 13387848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13397847Sminkyu.jeong@arm.com } 13401062SN/A 13412292SN/A inst->setExecuted(); 13422292SN/A 13432292SN/A instToCommit(inst); 13441062SN/A } 13451062SN/A 13462301SN/A updateExeInstStats(inst); 13471681SN/A 13482326SN/A // Check if branch prediction was correct, if not then we need 13492326SN/A // to tell commit to squash in flight instructions. Only 13502326SN/A // handle this if there hasn't already been something that 13512107SN/A // redirects fetch in this group of instructions. 13521681SN/A 13532292SN/A // This probably needs to prioritize the redirects if a different 13542292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13552292SN/A // instruction first, so the branch resolution order will be correct. 13566221Snate@binkert.org ThreadID tid = inst->threadNumber; 13571062SN/A 13583732Sktlim@umich.edu if (!fetchRedirect[tid] || 13597852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13603732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13611062SN/A 13627856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13637856SMatt.Horsnell@arm.com // that have not been executed. 13647856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13657856SMatt.Horsnell@arm.com 13667856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13672292SN/A fetchRedirect[tid] = true; 13681062SN/A 13692292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13708674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13718674Snilay@cs.wisc.edu inst->readPredTarg()); 13727720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13738674Snilay@cs.wisc.edu inst->pcState()); 13741062SN/A // If incorrect, then signal the ROB that it must be squashed. 13752292SN/A squashDueToBranch(inst, tid); 13761062SN/A 137710023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 137810023Smatt.horsnell@ARM.com 13793795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13801062SN/A predictedTakenIncorrect++; 13812292SN/A } else { 13822292SN/A predictedNotTakenIncorrect++; 13831062SN/A } 13842292SN/A } else if (ldstQueue.violation(tid)) { 13854033Sktlim@umich.edu assert(inst->isMemRef()); 13862326SN/A // If there was an ordering violation, then get the 13872326SN/A // DynInst that caused the violation. Note that this 13882292SN/A // clears the violation signal. 13892292SN/A DynInstPtr violator; 13902292SN/A violator = ldstQueue.getMemDepViolator(tid); 13911062SN/A 13927720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13937720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13947720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 139513590Srekai.gonzalezalberquilla@arm.com inst->pcState(), inst->seqNum, inst->physEffAddr); 13967720Sgblack@eecs.umich.edu 13973732Sktlim@umich.edu fetchRedirect[tid] = true; 13983732Sktlim@umich.edu 13991062SN/A // Tell the instruction queue that a violation has occured. 14001062SN/A instQueue.violation(inst, violator); 14011062SN/A 14021062SN/A // Squash. 14038513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 14041062SN/A 14051062SN/A ++memOrderViolationEvents; 14061062SN/A } 14074033Sktlim@umich.edu } else { 14084033Sktlim@umich.edu // Reset any state associated with redirects that will not 14094033Sktlim@umich.edu // be used. 14104033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14114033Sktlim@umich.edu assert(inst->isMemRef()); 14124033Sktlim@umich.edu 14134033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14144033Sktlim@umich.edu 14154033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14167720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14177720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 141813590Srekai.gonzalezalberquilla@arm.com inst->physEffAddr); 14194033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14204033Sktlim@umich.edu "already squashing\n"); 14214033Sktlim@umich.edu 14224033Sktlim@umich.edu ++memOrderViolationEvents; 14234033Sktlim@umich.edu } 14241062SN/A } 14251062SN/A } 14262292SN/A 14272348SN/A // Update and record activity if we processed any instructions. 14282292SN/A if (inst_num) { 14292292SN/A if (exeStatus == Idle) { 14302292SN/A exeStatus = Running; 14312292SN/A } 14322292SN/A 14332292SN/A updatedQueues = true; 14342292SN/A 14352292SN/A cpu->activityThisCycle(); 14362292SN/A } 14372292SN/A 14382292SN/A // Need to reset this in case a writeback event needs to write into the 14392292SN/A // iew queue. That way the writeback event will write into the correct 14402292SN/A // spot in the queue. 14412292SN/A wbNumInst = 0; 14427852SMatt.Horsnell@arm.com 14432107SN/A} 14442107SN/A 14452292SN/Atemplate <class Impl> 14462107SN/Avoid 14472292SN/ADefaultIEW<Impl>::writebackInsts() 14482107SN/A{ 14492326SN/A // Loop through the head of the time buffer and wake any 14502326SN/A // dependents. These instructions are about to write back. Also 14512326SN/A // mark scoreboard that this instruction is finally complete. 14522326SN/A // Either have IEW have direct access to scoreboard, or have this 14532326SN/A // as part of backwards communication. 14543958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14552292SN/A toCommit->insts[inst_num]; inst_num++) { 14562107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14576221Snate@binkert.org ThreadID tid = inst->threadNumber; 14582107SN/A 14597720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14607720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14612107SN/A 14622301SN/A iewInstsToCommit[tid]++; 146311246Sradhika.jagtap@ARM.com // Notify potential listeners that execution is complete for this 146411246Sradhika.jagtap@ARM.com // instruction. 146511246Sradhika.jagtap@ARM.com ppToCommit->notify(inst); 14662301SN/A 14672292SN/A // Some instructions will be sent to commit without having 14682292SN/A // executed because they need commit to handle them. 146910824SAndreas.Sandberg@ARM.com // E.g. Strictly ordered loads have not actually executed when they 14702292SN/A // are first sent to commit. Instead commit must tell the LSQ 147110824SAndreas.Sandberg@ARM.com // when it's ready to execute the strictly ordered load. 14722367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14732301SN/A int dependents = instQueue.wakeDependents(inst); 14742107SN/A 14752292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14762292SN/A //mark as Ready 147712105Snathanael.premillieu@arm.com DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 147812106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->index(), 147912106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->className()); 14802292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14812107SN/A } 14822301SN/A 14832348SN/A if (dependents) { 14842348SN/A producerInst[tid]++; 14852348SN/A consumerInst[tid]+= dependents; 14862348SN/A } 14872326SN/A writebackCount[tid]++; 14882107SN/A } 14892107SN/A } 14901060SN/A} 14911060SN/A 14921681SN/Atemplate<class Impl> 14931060SN/Avoid 14942292SN/ADefaultIEW<Impl>::tick() 14951060SN/A{ 14962292SN/A wbNumInst = 0; 14972292SN/A wbCycle = 0; 14981060SN/A 14992292SN/A wroteToTimeBuffer = false; 15002292SN/A updatedQueues = false; 15011060SN/A 150213590Srekai.gonzalezalberquilla@arm.com ldstQueue.tick(); 150313590Srekai.gonzalezalberquilla@arm.com 15042292SN/A sortInsts(); 15051060SN/A 15062326SN/A // Free function units marked as being freed this cycle. 15072326SN/A fuPool->processFreeUnits(); 15081062SN/A 15096221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15106221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15111060SN/A 15122326SN/A // Check stall and squash signals, dispatch any instructions. 15133867Sbinkertn@umich.edu while (threads != end) { 15146221Snate@binkert.org ThreadID tid = *threads++; 15151060SN/A 15162292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15171060SN/A 15182292SN/A checkSignalsAndUpdate(tid); 15192292SN/A dispatch(tid); 15201060SN/A } 15211060SN/A 15222292SN/A if (exeStatus != Squashing) { 15232292SN/A executeInsts(); 15241060SN/A 15252292SN/A writebackInsts(); 15262292SN/A 15272292SN/A // Have the instruction queue try to schedule any ready instructions. 15282292SN/A // (In actuality, this scheduling is for instructions that will 15292292SN/A // be executed next cycle.) 15302292SN/A instQueue.scheduleReadyInsts(); 15312292SN/A 15322292SN/A // Also should advance its own time buffers if the stage ran. 15332292SN/A // Not the best place for it, but this works (hopefully). 15342292SN/A issueToExecQueue.advance(); 15352292SN/A } 15362292SN/A 15372292SN/A bool broadcast_free_entries = false; 15382292SN/A 15392292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15402292SN/A exeStatus = Idle; 15412292SN/A updateLSQNextCycle = false; 15422292SN/A 15432292SN/A broadcast_free_entries = true; 15442292SN/A } 15452292SN/A 15462292SN/A // Writeback any stores using any leftover bandwidth. 15471681SN/A ldstQueue.writebackStores(); 15481681SN/A 15491061SN/A // Check the committed load/store signals to see if there's a load 15501061SN/A // or store to commit. Also check if it's being told to execute a 15511061SN/A // nonspeculative instruction. 15521681SN/A // This is pretty inefficient... 15532292SN/A 15543867Sbinkertn@umich.edu threads = activeThreads->begin(); 15553867Sbinkertn@umich.edu while (threads != end) { 15566221Snate@binkert.org ThreadID tid = (*threads++); 15572292SN/A 15582292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15592292SN/A 15602348SN/A // Update structures based on instructions committed. 15612292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15622292SN/A !fromCommit->commitInfo[tid].squash && 15632292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15642292SN/A 15652292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15662292SN/A 15672292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15682292SN/A 15692292SN/A updateLSQNextCycle = true; 15702292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15712292SN/A } 15722292SN/A 15732292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15742292SN/A 15752292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 157610824SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo[tid].strictlyOrdered) { 157710824SAndreas.Sandberg@ARM.com instQueue.replayMemInst( 157810824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad); 157910824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 15802292SN/A } else { 15812292SN/A instQueue.scheduleNonSpec( 15822292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15832292SN/A } 15842292SN/A } 15852292SN/A 15862292SN/A if (broadcast_free_entries) { 15872292SN/A toFetch->iewInfo[tid].iqCount = 15882292SN/A instQueue.getCount(tid); 15892292SN/A toFetch->iewInfo[tid].ldstqCount = 15902292SN/A ldstQueue.getCount(tid); 15912292SN/A 15922292SN/A toRename->iewInfo[tid].usedIQ = true; 15932292SN/A toRename->iewInfo[tid].freeIQEntries = 159410164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 15952292SN/A toRename->iewInfo[tid].usedLSQ = true; 159610239Sbinhpham@cs.rutgers.edu 159710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 159810239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 159910239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 160010239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 16012292SN/A 16022292SN/A wroteToTimeBuffer = true; 16032292SN/A } 16042292SN/A 16052292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16062292SN/A tid, toRename->iewInfo[tid].dispatched); 16071061SN/A } 16081061SN/A 16092292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 161010239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 16112292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 161210239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 16132292SN/A 16142292SN/A updateStatus(); 16152292SN/A 16162292SN/A if (wroteToTimeBuffer) { 16172292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16182292SN/A cpu->activityThisCycle(); 16191061SN/A } 16201060SN/A} 16211060SN/A 16222301SN/Atemplate <class Impl> 16231060SN/Avoid 162413429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 16251060SN/A{ 16266221Snate@binkert.org ThreadID tid = inst->threadNumber; 16271060SN/A 16282669Sktlim@umich.edu iewExecutedInsts++; 16291060SN/A 16308471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16319527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16329527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16339527SMatt.Horsnell@arm.com } 16348471SGiacomo.Gabrielli@arm.com#endif 16358471SGiacomo.Gabrielli@arm.com 16362301SN/A // 16372301SN/A // Control operations 16382301SN/A // 16392301SN/A if (inst->isControl()) 16406221Snate@binkert.org iewExecutedBranches[tid]++; 16411060SN/A 16422301SN/A // 16432301SN/A // Memory operations 16442301SN/A // 16452301SN/A if (inst->isMemRef()) { 16466221Snate@binkert.org iewExecutedRefs[tid]++; 16471060SN/A 16482301SN/A if (inst->isLoad()) { 16496221Snate@binkert.org iewExecLoadInsts[tid]++; 16501060SN/A } 16511060SN/A } 16521060SN/A} 16537598Sminkyu.jeong@arm.com 16547598Sminkyu.jeong@arm.comtemplate <class Impl> 16557598Sminkyu.jeong@arm.comvoid 165613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 16577598Sminkyu.jeong@arm.com{ 16587598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16597598Sminkyu.jeong@arm.com 16607598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16617852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16627598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16637598Sminkyu.jeong@arm.com 16647598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16657598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16667598Sminkyu.jeong@arm.com 16677598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16687598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16697720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16707598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16717720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16727720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16737598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16747598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16757598Sminkyu.jeong@arm.com 16767598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16777598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16787598Sminkyu.jeong@arm.com } else { 16797598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16807598Sminkyu.jeong@arm.com } 16817598Sminkyu.jeong@arm.com } 16827598Sminkyu.jeong@arm.com } 16837598Sminkyu.jeong@arm.com} 16849944Smatt.horsnell@ARM.com 16859944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1686