iew_impl.hh revision 13590
11689SN/A/* 213590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2010-2013, 2018 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 7913453Srekai.gonzalezalberquilla@arm.com wbNumInst(0), 8013453Srekai.gonzalezalberquilla@arm.com wbCycle(0), 812820Sktlim@umich.edu wbWidth(params->wbWidth), 829444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 831060SN/A{ 8410172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8510172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8710172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8810172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8910172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 9010172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9110172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9210172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9310172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9510172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9610172Sdam.sunwoo@arm.com 972292SN/A _status = Active; 982292SN/A exeStatus = Running; 992292SN/A wbStatus = Idle; 1001060SN/A 1011060SN/A // Setup wire to read instructions coming from issue. 1021060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1031060SN/A 1041060SN/A // Instruction queue needs the queue between issue and execute. 1051060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1061681SN/A 10713453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1086221Snate@binkert.org dispatchStatus[tid] = Running; 1096221Snate@binkert.org fetchRedirect[tid] = false; 1102292SN/A } 1112292SN/A 1122292SN/A updateLSQNextCycle = false; 1132292SN/A 11410328Smitch.hayenga@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1152292SN/A} 1162292SN/A 1172292SN/Atemplate <class Impl> 1182292SN/Astd::string 1192292SN/ADefaultIEW<Impl>::name() const 1202292SN/A{ 1212292SN/A return cpu->name() + ".iew"; 1221060SN/A} 1231060SN/A 1241681SN/Atemplate <class Impl> 1251062SN/Avoid 12610023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 12710023Smatt.horsnell@ARM.com{ 12810023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12910023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13011246Sradhika.jagtap@ARM.com /** 13111246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13211246Sradhika.jagtap@ARM.com * an instruction starts to execute. 13311246Sradhika.jagtap@ARM.com */ 13411246Sradhika.jagtap@ARM.com ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 13511246Sradhika.jagtap@ARM.com "Execute"); 13611246Sradhika.jagtap@ARM.com /** 13711246Sradhika.jagtap@ARM.com * Probe point with dynamic instruction as the argument used to probe when 13811246Sradhika.jagtap@ARM.com * an instruction execution completes and it is marked ready to commit. 13911246Sradhika.jagtap@ARM.com */ 14011246Sradhika.jagtap@ARM.com ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 14111246Sradhika.jagtap@ARM.com "ToCommit"); 14210023Smatt.horsnell@ARM.com} 14310023Smatt.horsnell@ARM.com 14410023Smatt.horsnell@ARM.comtemplate <class Impl> 14510023Smatt.horsnell@ARM.comvoid 1462292SN/ADefaultIEW<Impl>::regStats() 1471062SN/A{ 1482301SN/A using namespace Stats; 1492301SN/A 1501062SN/A instQueue.regStats(); 1512727Sktlim@umich.edu ldstQueue.regStats(); 1521062SN/A 1531062SN/A iewIdleCycles 1541062SN/A .name(name() + ".iewIdleCycles") 1551062SN/A .desc("Number of cycles IEW is idle"); 1561062SN/A 1571062SN/A iewSquashCycles 1581062SN/A .name(name() + ".iewSquashCycles") 1591062SN/A .desc("Number of cycles IEW is squashing"); 1601062SN/A 1611062SN/A iewBlockCycles 1621062SN/A .name(name() + ".iewBlockCycles") 1631062SN/A .desc("Number of cycles IEW is blocking"); 1641062SN/A 1651062SN/A iewUnblockCycles 1661062SN/A .name(name() + ".iewUnblockCycles") 1671062SN/A .desc("Number of cycles IEW is unblocking"); 1681062SN/A 1691062SN/A iewDispatchedInsts 1701062SN/A .name(name() + ".iewDispatchedInsts") 1711062SN/A .desc("Number of instructions dispatched to IQ"); 1721062SN/A 1731062SN/A iewDispSquashedInsts 1741062SN/A .name(name() + ".iewDispSquashedInsts") 1751062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1761062SN/A 1771062SN/A iewDispLoadInsts 1781062SN/A .name(name() + ".iewDispLoadInsts") 1791062SN/A .desc("Number of dispatched load instructions"); 1801062SN/A 1811062SN/A iewDispStoreInsts 1821062SN/A .name(name() + ".iewDispStoreInsts") 1831062SN/A .desc("Number of dispatched store instructions"); 1841062SN/A 1851062SN/A iewDispNonSpecInsts 1861062SN/A .name(name() + ".iewDispNonSpecInsts") 1871062SN/A .desc("Number of dispatched non-speculative instructions"); 1881062SN/A 1891062SN/A iewIQFullEvents 1901062SN/A .name(name() + ".iewIQFullEvents") 1911062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1921062SN/A 1932292SN/A iewLSQFullEvents 1942292SN/A .name(name() + ".iewLSQFullEvents") 1952292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1962292SN/A 1971062SN/A memOrderViolationEvents 1981062SN/A .name(name() + ".memOrderViolationEvents") 1991062SN/A .desc("Number of memory order violations"); 2001062SN/A 2011062SN/A predictedTakenIncorrect 2021062SN/A .name(name() + ".predictedTakenIncorrect") 2031062SN/A .desc("Number of branches that were predicted taken incorrectly"); 2042292SN/A 2052292SN/A predictedNotTakenIncorrect 2062292SN/A .name(name() + ".predictedNotTakenIncorrect") 2072292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2082292SN/A 2092292SN/A branchMispredicts 2102292SN/A .name(name() + ".branchMispredicts") 2112292SN/A .desc("Number of branch mispredicts detected at execute"); 2122292SN/A 2132292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2142301SN/A 2152727Sktlim@umich.edu iewExecutedInsts 2162353SN/A .name(name() + ".iewExecutedInsts") 2172727Sktlim@umich.edu .desc("Number of executed instructions"); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu iewExecLoadInsts 2206221Snate@binkert.org .init(cpu->numThreads) 2212353SN/A .name(name() + ".iewExecLoadInsts") 2222727Sktlim@umich.edu .desc("Number of load instructions executed") 2232727Sktlim@umich.edu .flags(total); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecSquashedInsts 2262353SN/A .name(name() + ".iewExecSquashedInsts") 2272727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu iewExecutedSwp 2306221Snate@binkert.org .init(cpu->numThreads) 2318240Snate@binkert.org .name(name() + ".exec_swp") 2322301SN/A .desc("number of swp insts executed") 2332727Sktlim@umich.edu .flags(total); 2342301SN/A 2352727Sktlim@umich.edu iewExecutedNop 2366221Snate@binkert.org .init(cpu->numThreads) 2378240Snate@binkert.org .name(name() + ".exec_nop") 2382301SN/A .desc("number of nop insts executed") 2392727Sktlim@umich.edu .flags(total); 2402301SN/A 2412727Sktlim@umich.edu iewExecutedRefs 2426221Snate@binkert.org .init(cpu->numThreads) 2438240Snate@binkert.org .name(name() + ".exec_refs") 2442301SN/A .desc("number of memory reference insts executed") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472727Sktlim@umich.edu iewExecutedBranches 2486221Snate@binkert.org .init(cpu->numThreads) 2498240Snate@binkert.org .name(name() + ".exec_branches") 2502301SN/A .desc("Number of branches executed") 2512727Sktlim@umich.edu .flags(total); 2522301SN/A 2532301SN/A iewExecStoreInsts 2548240Snate@binkert.org .name(name() + ".exec_stores") 2552301SN/A .desc("Number of stores executed") 2562727Sktlim@umich.edu .flags(total); 2572727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2582727Sktlim@umich.edu 2592727Sktlim@umich.edu iewExecRate 2608240Snate@binkert.org .name(name() + ".exec_rate") 2612727Sktlim@umich.edu .desc("Inst execution rate") 2622727Sktlim@umich.edu .flags(total); 2632727Sktlim@umich.edu 2642727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2652301SN/A 2662301SN/A iewInstsToCommit 2676221Snate@binkert.org .init(cpu->numThreads) 2688240Snate@binkert.org .name(name() + ".wb_sent") 2692301SN/A .desc("cumulative count of insts sent to commit") 2702727Sktlim@umich.edu .flags(total); 2712301SN/A 2722326SN/A writebackCount 2736221Snate@binkert.org .init(cpu->numThreads) 2748240Snate@binkert.org .name(name() + ".wb_count") 2752301SN/A .desc("cumulative count of insts written-back") 2762727Sktlim@umich.edu .flags(total); 2772301SN/A 2782326SN/A producerInst 2796221Snate@binkert.org .init(cpu->numThreads) 2808240Snate@binkert.org .name(name() + ".wb_producers") 2812301SN/A .desc("num instructions producing a value") 2822727Sktlim@umich.edu .flags(total); 2832301SN/A 2842326SN/A consumerInst 2856221Snate@binkert.org .init(cpu->numThreads) 2868240Snate@binkert.org .name(name() + ".wb_consumers") 2872301SN/A .desc("num instructions consuming a value") 2882727Sktlim@umich.edu .flags(total); 2892301SN/A 2902326SN/A wbFanout 2918240Snate@binkert.org .name(name() + ".wb_fanout") 2922301SN/A .desc("average fanout of values written-back") 2932727Sktlim@umich.edu .flags(total); 2942301SN/A 2952326SN/A wbFanout = producerInst / consumerInst; 2962301SN/A 2972326SN/A wbRate 2988240Snate@binkert.org .name(name() + ".wb_rate") 2992301SN/A .desc("insts written-back per cycle") 3002727Sktlim@umich.edu .flags(total); 3012326SN/A wbRate = writebackCount / cpu->numCycles; 3021062SN/A} 3031062SN/A 3041681SN/Atemplate<class Impl> 3051060SN/Avoid 3069427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3071060SN/A{ 3086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3092292SN/A toRename->iewInfo[tid].usedIQ = true; 3102292SN/A toRename->iewInfo[tid].freeIQEntries = 3112292SN/A instQueue.numFreeEntries(tid); 3122292SN/A 3132292SN/A toRename->iewInfo[tid].usedLSQ = true; 31410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3162292SN/A } 3172292SN/A 3188887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3198733Sgeoffrey.blake@arm.com if (cpu->checker) { 3208850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3218887Sgeoffrey.blake@arm.com } 3228733Sgeoffrey.blake@arm.com 3232733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3241060SN/A} 3251060SN/A 3261681SN/Atemplate<class Impl> 3271060SN/Avoid 3282292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3291060SN/A{ 3301060SN/A timeBuffer = tb_ptr; 3311060SN/A 3321060SN/A // Setup wire to read information from time buffer, from commit. 3331060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3341060SN/A 3351060SN/A // Setup wire to write information back to previous stages. 3361060SN/A toRename = timeBuffer->getWire(0); 3371060SN/A 3382292SN/A toFetch = timeBuffer->getWire(0); 3392292SN/A 3401060SN/A // Instruction queue also needs main time buffer. 3411060SN/A instQueue.setTimeBuffer(tb_ptr); 3421060SN/A} 3431060SN/A 3441681SN/Atemplate<class Impl> 3451060SN/Avoid 3462292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3471060SN/A{ 3481060SN/A renameQueue = rq_ptr; 3491060SN/A 3501060SN/A // Setup wire to read information from rename queue. 3511060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3521060SN/A} 3531060SN/A 3541681SN/Atemplate<class Impl> 3551060SN/Avoid 3562292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3571060SN/A{ 3581060SN/A iewQueue = iq_ptr; 3591060SN/A 3601060SN/A // Setup wire to write instructions to commit. 3611060SN/A toCommit = iewQueue->getWire(0); 3621060SN/A} 3631060SN/A 3641681SN/Atemplate<class Impl> 3651060SN/Avoid 3666221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3671060SN/A{ 3682292SN/A activeThreads = at_ptr; 3692292SN/A 3702292SN/A ldstQueue.setActiveThreads(at_ptr); 3712292SN/A instQueue.setActiveThreads(at_ptr); 3721060SN/A} 3731060SN/A 3741681SN/Atemplate<class Impl> 3751060SN/Avoid 3762292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3771060SN/A{ 3782292SN/A scoreboard = sb_ptr; 3791060SN/A} 3801060SN/A 3812307SN/Atemplate <class Impl> 3822863Sktlim@umich.edubool 3839444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3842307SN/A{ 38510510Smitch.hayenga@arm.com bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3869444SAndreas.Sandberg@ARM.com 3879444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3889444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3899444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3909444SAndreas.Sandberg@ARM.com drained = false; 3919444SAndreas.Sandberg@ARM.com } 3929444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3939444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3949444SAndreas.Sandberg@ARM.com drained = false; 3959444SAndreas.Sandberg@ARM.com } 39611650Srekai.gonzalezalberquilla@arm.com drained = drained && dispatchStatus[tid] == Running; 3979444SAndreas.Sandberg@ARM.com } 3989444SAndreas.Sandberg@ARM.com 3999783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4009783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4019783Sandreas.hansson@arm.com // above 4029783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4039783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4049783Sandreas.hansson@arm.com drained = false; 4059783Sandreas.hansson@arm.com } 4069783Sandreas.hansson@arm.com 4079444SAndreas.Sandberg@ARM.com return drained; 4081681SN/A} 4091681SN/A 4102316SN/Atemplate <class Impl> 4111681SN/Avoid 4129444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4132843Sktlim@umich.edu{ 4149444SAndreas.Sandberg@ARM.com assert(isDrained()); 4152843Sktlim@umich.edu 4169444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4179444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4181681SN/A} 4191681SN/A 4202307SN/Atemplate <class Impl> 4211681SN/Avoid 4222307SN/ADefaultIEW<Impl>::takeOverFrom() 4231060SN/A{ 4242348SN/A // Reset all state. 4252307SN/A _status = Active; 4262307SN/A exeStatus = Running; 4272307SN/A wbStatus = Idle; 4281060SN/A 4292307SN/A instQueue.takeOverFrom(); 4302307SN/A ldstQueue.takeOverFrom(); 4319444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4321060SN/A 4339427SAndreas.Sandberg@ARM.com startupStage(); 4342307SN/A cpu->activityThisCycle(); 4351060SN/A 4366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4376221Snate@binkert.org dispatchStatus[tid] = Running; 4386221Snate@binkert.org fetchRedirect[tid] = false; 4392307SN/A } 4401060SN/A 4412307SN/A updateLSQNextCycle = false; 4422307SN/A 4432873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4442307SN/A issueToExecQueue.advance(); 4451060SN/A } 4461060SN/A} 4471060SN/A 4481681SN/Atemplate<class Impl> 4491060SN/Avoid 4506221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4512107SN/A{ 4526221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4532107SN/A 4542292SN/A // Tell the IQ to start squashing. 4552292SN/A instQueue.squash(tid); 4562107SN/A 4572292SN/A // Tell the LDSTQ to start squashing. 4582326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4592292SN/A updatedQueues = true; 4602107SN/A 4612292SN/A // Clear the skid buffer in case it has any data in it. 4622935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4634632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4642935Sksewell@umich.edu 4652292SN/A while (!skidBuffer[tid].empty()) { 46610239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 46710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 46810239Sbinhpham@cs.rutgers.edu } 46910239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isStore()) { 47010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4712292SN/A } 4722107SN/A 4732292SN/A toRename->iewInfo[tid].dispatched++; 4742107SN/A 4752292SN/A skidBuffer[tid].pop(); 4762292SN/A } 4772107SN/A 4782702Sktlim@umich.edu emptyRenameInsts(tid); 4792107SN/A} 4802107SN/A 4812107SN/Atemplate<class Impl> 4822107SN/Avoid 48313429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 4842292SN/A{ 4857720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4867720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4872292SN/A 48810231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 4897852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4907852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4917852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4927852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4932935Sksewell@umich.edu 4947852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4957852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4962292SN/A 4977852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4987852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4997852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5002292SN/A 5017852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5027852SMatt.Horsnell@arm.com } 5037852SMatt.Horsnell@arm.com 5042292SN/A} 5052292SN/A 5062292SN/Atemplate<class Impl> 5072292SN/Avoid 50813429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5092292SN/A{ 5108513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5118513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5128513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5138513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5148513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5158513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5168513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5178513SGiacomo.Gabrielli@arm.com // the squash. 51810231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5198513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5208513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5212292SN/A 5227852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5238513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5248137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5252292SN/A 5268513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5278513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5282292SN/A 5297852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5307852SMatt.Horsnell@arm.com } 5312292SN/A} 5322292SN/A 5332292SN/Atemplate<class Impl> 5342292SN/Avoid 5356221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5362292SN/A{ 5372292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5382292SN/A 5392292SN/A if (dispatchStatus[tid] != Blocked && 5402292SN/A dispatchStatus[tid] != Unblocking) { 5412292SN/A toRename->iewBlock[tid] = true; 5422292SN/A wroteToTimeBuffer = true; 5432292SN/A } 5442292SN/A 5452292SN/A // Add the current inputs to the skid buffer so they can be 5462292SN/A // reprocessed when this stage unblocks. 5472292SN/A skidInsert(tid); 5482292SN/A 5492292SN/A dispatchStatus[tid] = Blocked; 5502292SN/A} 5512292SN/A 5522292SN/Atemplate<class Impl> 5532292SN/Avoid 5546221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5552292SN/A{ 5562292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5572292SN/A "buffer %u.\n",tid, tid); 5582292SN/A 5592292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5602292SN/A // Also switch status to running. 5612292SN/A if (skidBuffer[tid].empty()) { 5622292SN/A toRename->iewUnblock[tid] = true; 5632292SN/A wroteToTimeBuffer = true; 5642292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5652292SN/A dispatchStatus[tid] = Running; 5662292SN/A } 5672292SN/A} 5682292SN/A 5692292SN/Atemplate<class Impl> 5702292SN/Avoid 57113429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5721060SN/A{ 5731681SN/A instQueue.wakeDependents(inst); 5741060SN/A} 5751060SN/A 5762292SN/Atemplate<class Impl> 5772292SN/Avoid 57813429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5792292SN/A{ 5802292SN/A instQueue.rescheduleMemInst(inst); 5812292SN/A} 5821681SN/A 5831681SN/Atemplate<class Impl> 5841060SN/Avoid 58513429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 5861060SN/A{ 5872292SN/A instQueue.replayMemInst(inst); 5882292SN/A} 5891060SN/A 5902292SN/Atemplate<class Impl> 5912292SN/Avoid 59213429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 59310333Smitch.hayenga@arm.com{ 59410333Smitch.hayenga@arm.com instQueue.blockMemInst(inst); 59510333Smitch.hayenga@arm.com} 59610333Smitch.hayenga@arm.com 59710333Smitch.hayenga@arm.comtemplate<class Impl> 59810333Smitch.hayenga@arm.comvoid 59910333Smitch.hayenga@arm.comDefaultIEW<Impl>::cacheUnblocked() 60010333Smitch.hayenga@arm.com{ 60110333Smitch.hayenga@arm.com instQueue.cacheUnblocked(); 60210333Smitch.hayenga@arm.com} 60310333Smitch.hayenga@arm.com 60410333Smitch.hayenga@arm.comtemplate<class Impl> 60510333Smitch.hayenga@arm.comvoid 60613429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6072292SN/A{ 6083221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6093221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6103221Sktlim@umich.edu // being added to the queue to commit without being processed by 6113221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6123221Sktlim@umich.edu 6132292SN/A // First check the time slot that this instruction will write 6142292SN/A // to. If there are free write ports at the time, then go ahead 6152292SN/A // and write the instruction to that time. If there are not, 6162292SN/A // keep looking back to see where's the first time there's a 6172326SN/A // free slot. 6182292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6192292SN/A ++wbNumInst; 6202820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6212292SN/A ++wbCycle; 6222292SN/A wbNumInst = 0; 6232292SN/A } 6242292SN/A } 6252292SN/A 6262353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6272353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6282292SN/A // Add finished instruction to queue to commit. 6292292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6302292SN/A (*iewQueue)[wbCycle].size++; 6312292SN/A} 6322292SN/A 6332292SN/Atemplate <class Impl> 6342292SN/Aunsigned 6352292SN/ADefaultIEW<Impl>::validInstsFromRename() 6362292SN/A{ 6372292SN/A unsigned inst_count = 0; 6382292SN/A 6392292SN/A for (int i=0; i<fromRename->size; i++) { 6402731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6412292SN/A inst_count++; 6422292SN/A } 6432292SN/A 6442292SN/A return inst_count; 6452292SN/A} 6462292SN/A 6472292SN/Atemplate<class Impl> 6482292SN/Avoid 6496221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6502292SN/A{ 6512292SN/A DynInstPtr inst = NULL; 6522292SN/A 6532292SN/A while (!insts[tid].empty()) { 6542292SN/A inst = insts[tid].front(); 6552292SN/A 6562292SN/A insts[tid].pop(); 6572292SN/A 6589937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6592292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6607720Sgblack@eecs.umich.edu inst->pcState(),tid); 6612292SN/A 6622292SN/A skidBuffer[tid].push(inst); 6632292SN/A } 6642292SN/A 6652292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6662292SN/A "Skidbuffer Exceeded Max Size"); 6672292SN/A} 6682292SN/A 6692292SN/Atemplate<class Impl> 6702292SN/Aint 6712292SN/ADefaultIEW<Impl>::skidCount() 6722292SN/A{ 6732292SN/A int max=0; 6742292SN/A 6756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6772292SN/A 6783867Sbinkertn@umich.edu while (threads != end) { 6796221Snate@binkert.org ThreadID tid = *threads++; 6803867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6812292SN/A if (max < thread_count) 6822292SN/A max = thread_count; 6832292SN/A } 6842292SN/A 6852292SN/A return max; 6862292SN/A} 6872292SN/A 6882292SN/Atemplate<class Impl> 6892292SN/Abool 6902292SN/ADefaultIEW<Impl>::skidsEmpty() 6912292SN/A{ 6926221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6936221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6942292SN/A 6953867Sbinkertn@umich.edu while (threads != end) { 6966221Snate@binkert.org ThreadID tid = *threads++; 6973867Sbinkertn@umich.edu 6983867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6992292SN/A return false; 7002292SN/A } 7012292SN/A 7022292SN/A return true; 7031062SN/A} 7041062SN/A 7051681SN/Atemplate <class Impl> 7061062SN/Avoid 7072292SN/ADefaultIEW<Impl>::updateStatus() 7081062SN/A{ 7092292SN/A bool any_unblocking = false; 7101062SN/A 7116221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7126221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7131062SN/A 7143867Sbinkertn@umich.edu while (threads != end) { 7156221Snate@binkert.org ThreadID tid = *threads++; 7161062SN/A 7172292SN/A if (dispatchStatus[tid] == Unblocking) { 7182292SN/A any_unblocking = true; 7192292SN/A break; 7202292SN/A } 7212292SN/A } 7221062SN/A 7232292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7242292SN/A // and there's no stores waiting to write back, and dispatch is not 7252292SN/A // unblocking, then there is no internal activity for the IEW stage. 7267897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7272292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7282292SN/A !ldstQueue.willWB() && !any_unblocking) { 7292292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7301062SN/A 7312292SN/A deactivateStage(); 7321062SN/A 7332292SN/A _status = Inactive; 7342292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7352292SN/A ldstQueue.willWB() || 7362292SN/A any_unblocking)) { 7372292SN/A // Otherwise there is internal activity. Set to active. 7382292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7391062SN/A 7402292SN/A activateStage(); 7411062SN/A 7422292SN/A _status = Active; 7431062SN/A } 7441062SN/A} 7451062SN/A 7461681SN/Atemplate <class Impl> 7472292SN/Abool 7486221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7492292SN/A{ 7502292SN/A bool ret_val(false); 7512292SN/A 75210328Smitch.hayenga@arm.com if (fromCommit->commitInfo[tid].robSquashing) { 7532292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7542292SN/A ret_val = true; 7552292SN/A } else if (instQueue.isFull(tid)) { 7562292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7572292SN/A ret_val = true; 7582292SN/A } 7592292SN/A 7602292SN/A return ret_val; 7612292SN/A} 7622292SN/A 7632292SN/Atemplate <class Impl> 7642292SN/Avoid 7656221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7662292SN/A{ 7672292SN/A // Check if there's a squash signal, squash if there is 7682292SN/A // Check stall signals, block if there is. 7692292SN/A // If status was Blocked 7702292SN/A // if so then go to unblocking 7712292SN/A // If status was Squashing 7722292SN/A // check if squashing is not high. Switch to running this cycle. 7732292SN/A 7742292SN/A if (fromCommit->commitInfo[tid].squash) { 7752292SN/A squash(tid); 7762292SN/A 7772292SN/A if (dispatchStatus[tid] == Blocked || 7782292SN/A dispatchStatus[tid] == Unblocking) { 7792292SN/A toRename->iewUnblock[tid] = true; 7802292SN/A wroteToTimeBuffer = true; 7812292SN/A } 7822292SN/A 7832292SN/A dispatchStatus[tid] = Squashing; 7842292SN/A fetchRedirect[tid] = false; 7852292SN/A return; 7862292SN/A } 7872292SN/A 7882292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7892702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7902292SN/A 7912292SN/A dispatchStatus[tid] = Squashing; 7922702Sktlim@umich.edu emptyRenameInsts(tid); 7932702Sktlim@umich.edu wroteToTimeBuffer = true; 7942292SN/A } 7952292SN/A 7962292SN/A if (checkStall(tid)) { 7972292SN/A block(tid); 7982292SN/A dispatchStatus[tid] = Blocked; 7992292SN/A return; 8002292SN/A } 8012292SN/A 8022292SN/A if (dispatchStatus[tid] == Blocked) { 8032292SN/A // Status from previous cycle was blocked, but there are no more stall 8042292SN/A // conditions. Switch over to unblocking. 8052292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8062292SN/A tid); 8072292SN/A 8082292SN/A dispatchStatus[tid] = Unblocking; 8092292SN/A 8102292SN/A unblock(tid); 8112292SN/A 8122292SN/A return; 8132292SN/A } 8142292SN/A 8152292SN/A if (dispatchStatus[tid] == Squashing) { 8162292SN/A // Switch status to running if rename isn't being told to block or 8172292SN/A // squash this cycle. 8182292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8192292SN/A tid); 8202292SN/A 8212292SN/A dispatchStatus[tid] = Running; 8222292SN/A 8232292SN/A return; 8242292SN/A } 8252292SN/A} 8262292SN/A 8272292SN/Atemplate <class Impl> 8282292SN/Avoid 8292292SN/ADefaultIEW<Impl>::sortInsts() 8302292SN/A{ 8312292SN/A int insts_from_rename = fromRename->size; 8322326SN/A#ifdef DEBUG 8336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8346221Snate@binkert.org assert(insts[tid].empty()); 8352326SN/A#endif 8362292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8372292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8382292SN/A } 8392292SN/A} 8402292SN/A 8412292SN/Atemplate <class Impl> 8422292SN/Avoid 8436221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8442702Sktlim@umich.edu{ 8454632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8462935Sksewell@umich.edu 8472702Sktlim@umich.edu while (!insts[tid].empty()) { 8482935Sksewell@umich.edu 84910239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 85010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 85110239Sbinhpham@cs.rutgers.edu } 85210239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isStore()) { 85310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 8542702Sktlim@umich.edu } 8552702Sktlim@umich.edu 8562702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8572702Sktlim@umich.edu 8582702Sktlim@umich.edu insts[tid].pop(); 8592702Sktlim@umich.edu } 8602702Sktlim@umich.edu} 8612702Sktlim@umich.edu 8622702Sktlim@umich.edutemplate <class Impl> 8632702Sktlim@umich.eduvoid 8642292SN/ADefaultIEW<Impl>::wakeCPU() 8652292SN/A{ 8662292SN/A cpu->wakeCPU(); 8672292SN/A} 8682292SN/A 8692292SN/Atemplate <class Impl> 8702292SN/Avoid 8712292SN/ADefaultIEW<Impl>::activityThisCycle() 8722292SN/A{ 8732292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8742292SN/A cpu->activityThisCycle(); 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Ainline void 8792292SN/ADefaultIEW<Impl>::activateStage() 8802292SN/A{ 8812292SN/A DPRINTF(Activity, "Activating stage.\n"); 8822733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8832292SN/A} 8842292SN/A 8852292SN/Atemplate <class Impl> 8862292SN/Ainline void 8872292SN/ADefaultIEW<Impl>::deactivateStage() 8882292SN/A{ 8892292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8902733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8912292SN/A} 8922292SN/A 8932292SN/Atemplate<class Impl> 8942292SN/Avoid 8956221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 8962292SN/A{ 8972292SN/A // If status is Running or idle, 8982292SN/A // call dispatchInsts() 8992292SN/A // If status is Unblocking, 9002292SN/A // buffer any instructions coming from rename 9012292SN/A // continue trying to empty skid buffer 9022292SN/A // check if stall conditions have passed 9032292SN/A 9042292SN/A if (dispatchStatus[tid] == Blocked) { 9052292SN/A ++iewBlockCycles; 9062292SN/A 9072292SN/A } else if (dispatchStatus[tid] == Squashing) { 9082292SN/A ++iewSquashCycles; 9092292SN/A } 9102292SN/A 9112292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9122292SN/A // will allow, as long as it is not currently blocked. 9132292SN/A if (dispatchStatus[tid] == Running || 9142292SN/A dispatchStatus[tid] == Idle) { 9152292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9162292SN/A "dispatch.\n", tid); 9172292SN/A 9182292SN/A dispatchInsts(tid); 9192292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9202292SN/A // Make sure that the skid buffer has something in it if the 9212292SN/A // status is unblocking. 9222292SN/A assert(!skidsEmpty()); 9232292SN/A 9242292SN/A // If the status was unblocking, then instructions from the skid 9252292SN/A // buffer were used. Remove those instructions and handle 9262292SN/A // the rest of unblocking. 9272292SN/A dispatchInsts(tid); 9282292SN/A 9292292SN/A ++iewUnblockCycles; 9302292SN/A 9315215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9322292SN/A // Add the current inputs to the skid buffer so they can be 9332292SN/A // reprocessed when this stage unblocks. 9342292SN/A skidInsert(tid); 9352292SN/A } 9362292SN/A 9372292SN/A unblock(tid); 9382292SN/A } 9392292SN/A} 9402292SN/A 9412292SN/Atemplate <class Impl> 9422292SN/Avoid 9436221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9442292SN/A{ 9452292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9462292SN/A // otherwise. 9472292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9482292SN/A dispatchStatus[tid] == Unblocking ? 9492292SN/A skidBuffer[tid] : insts[tid]; 9502292SN/A 9512292SN/A int insts_to_add = insts_to_dispatch.size(); 9522292SN/A 9532292SN/A DynInstPtr inst; 9542292SN/A bool add_to_iq = false; 9552292SN/A int dis_num_inst = 0; 9562292SN/A 9572292SN/A // Loop through the instructions, putting them in the instruction 9582292SN/A // queue. 9592292SN/A for ( ; dis_num_inst < insts_to_add && 9602820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9612292SN/A ++dis_num_inst) 9622292SN/A { 9632292SN/A inst = insts_to_dispatch.front(); 9642292SN/A 9652292SN/A if (dispatchStatus[tid] == Unblocking) { 9662292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9672292SN/A "buffer\n", tid); 9682292SN/A } 9692292SN/A 9702292SN/A // Make sure there's a valid instruction there. 9712292SN/A assert(inst); 9722292SN/A 9737720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9742292SN/A "IQ.\n", 9757720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9762292SN/A 9772292SN/A // Be sure to mark these instructions as ready so that the 9782292SN/A // commit stage can go ahead and execute them, and mark 9792292SN/A // them as issued so the IQ doesn't reprocess them. 9802292SN/A 9812292SN/A // Check for squashed instructions. 9822292SN/A if (inst->isSquashed()) { 9832292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9842292SN/A "not adding to IQ.\n", tid); 9852292SN/A 9862292SN/A ++iewDispSquashedInsts; 9872292SN/A 9882292SN/A insts_to_dispatch.pop(); 9892292SN/A 9902292SN/A //Tell Rename That An Instruction has been processed 99110239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 99210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 9932292SN/A } 99410239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 99510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 99610239Sbinhpham@cs.rutgers.edu } 99710239Sbinhpham@cs.rutgers.edu 9982292SN/A toRename->iewInfo[tid].dispatched++; 9992292SN/A 10002292SN/A continue; 10012292SN/A } 10022292SN/A 10032292SN/A // Check for full conditions. 10042292SN/A if (instQueue.isFull(tid)) { 10052292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10062292SN/A 10072292SN/A // Call function to start blocking. 10082292SN/A block(tid); 10092292SN/A 10102292SN/A // Set unblock to false. Special case where we are using 10112292SN/A // skidbuffer (unblocking) instructions but then we still 10122292SN/A // get full in the IQ. 10132292SN/A toRename->iewUnblock[tid] = false; 10142292SN/A 10152292SN/A ++iewIQFullEvents; 10162292SN/A break; 101710240Sbinhpham@cs.rutgers.edu } 101810240Sbinhpham@cs.rutgers.edu 101910240Sbinhpham@cs.rutgers.edu // Check LSQ if inst is LD/ST 102010240Sbinhpham@cs.rutgers.edu if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 102110240Sbinhpham@cs.rutgers.edu (inst->isStore() && ldstQueue.sqFull(tid))) { 102210240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 102310240Sbinhpham@cs.rutgers.edu inst->isLoad() ? "LQ" : "SQ"); 10242292SN/A 10252292SN/A // Call function to start blocking. 10262292SN/A block(tid); 10272292SN/A 10282292SN/A // Set unblock to false. Special case where we are using 10292292SN/A // skidbuffer (unblocking) instructions but then we still 10302292SN/A // get full in the IQ. 10312292SN/A toRename->iewUnblock[tid] = false; 10322292SN/A 10332292SN/A ++iewLSQFullEvents; 10342292SN/A break; 10352292SN/A } 10362292SN/A 10372292SN/A // Otherwise issue the instruction just fine. 10382292SN/A if (inst->isLoad()) { 10392292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10402292SN/A "encountered, adding to LSQ.\n", tid); 10412292SN/A 10422292SN/A // Reserve a spot in the load store queue for this 10432292SN/A // memory access. 10442292SN/A ldstQueue.insertLoad(inst); 10452292SN/A 10462292SN/A ++iewDispLoadInsts; 10472292SN/A 10482292SN/A add_to_iq = true; 10492292SN/A 105010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10512292SN/A } else if (inst->isStore()) { 10522292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10532292SN/A "encountered, adding to LSQ.\n", tid); 10542292SN/A 10552292SN/A ldstQueue.insertStore(inst); 10562292SN/A 10572292SN/A ++iewDispStoreInsts; 10582292SN/A 10592336SN/A if (inst->isStoreConditional()) { 10602336SN/A // Store conditionals need to be set as "canCommit()" 10612336SN/A // so that commit can process them when they reach the 10622336SN/A // head of commit. 10632348SN/A // @todo: This is somewhat specific to Alpha. 10642292SN/A inst->setCanCommit(); 10652292SN/A instQueue.insertNonSpec(inst); 10662292SN/A add_to_iq = false; 10672292SN/A 10682292SN/A ++iewDispNonSpecInsts; 10692292SN/A } else { 10702292SN/A add_to_iq = true; 10712292SN/A } 10722292SN/A 107310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 10742292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10752326SN/A // Same as non-speculative stores. 10762292SN/A inst->setCanCommit(); 10772292SN/A instQueue.insertBarrier(inst); 10782292SN/A add_to_iq = false; 10792292SN/A } else if (inst->isNop()) { 10802292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10812292SN/A "skipping.\n", tid); 10822292SN/A 10832292SN/A inst->setIssued(); 10842292SN/A inst->setExecuted(); 10852292SN/A inst->setCanCommit(); 10862292SN/A 10872326SN/A instQueue.recordProducer(inst); 10882292SN/A 10892727Sktlim@umich.edu iewExecutedNop[tid]++; 10902301SN/A 10912292SN/A add_to_iq = false; 10922292SN/A } else { 109310733Snilay@cs.wisc.edu assert(!inst->isExecuted()); 10942292SN/A add_to_iq = true; 10952292SN/A } 109610733Snilay@cs.wisc.edu 109712537Sandreas.sandberg@arm.com if (add_to_iq && inst->isNonSpeculative()) { 10984033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 10994033Sktlim@umich.edu "encountered, skipping.\n", tid); 11004033Sktlim@umich.edu 11014033Sktlim@umich.edu // Same as non-speculative stores. 11024033Sktlim@umich.edu inst->setCanCommit(); 11034033Sktlim@umich.edu 11044033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11054033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11064033Sktlim@umich.edu 11074033Sktlim@umich.edu ++iewDispNonSpecInsts; 11084033Sktlim@umich.edu 11094033Sktlim@umich.edu add_to_iq = false; 11104033Sktlim@umich.edu } 11112292SN/A 11122292SN/A // If the instruction queue is not full, then add the 11132292SN/A // instruction. 11142292SN/A if (add_to_iq) { 11152292SN/A instQueue.insert(inst); 11162292SN/A } 11172292SN/A 11182292SN/A insts_to_dispatch.pop(); 11192292SN/A 11202292SN/A toRename->iewInfo[tid].dispatched++; 11212292SN/A 11222292SN/A ++iewDispatchedInsts; 11238471SGiacomo.Gabrielli@arm.com 11248471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11259046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11268471SGiacomo.Gabrielli@arm.com#endif 112710023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11282292SN/A } 11292292SN/A 11302292SN/A if (!insts_to_dispatch.empty()) { 11312935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11322292SN/A block(tid); 11332292SN/A toRename->iewUnblock[tid] = false; 11342292SN/A } 11352292SN/A 11362292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11372292SN/A dispatchStatus[tid] = Running; 11382292SN/A 11392292SN/A updatedQueues = true; 11402292SN/A } 11412292SN/A 11422292SN/A dis_num_inst = 0; 11432292SN/A} 11442292SN/A 11452292SN/Atemplate <class Impl> 11462292SN/Avoid 11472292SN/ADefaultIEW<Impl>::printAvailableInsts() 11482292SN/A{ 11492292SN/A int inst = 0; 11502292SN/A 11512980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11522292SN/A 11532292SN/A while (fromIssue->insts[inst]) { 11542292SN/A 11552980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11562292SN/A 11577720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11582292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11592292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11602292SN/A 11612292SN/A inst++; 11622292SN/A 11632292SN/A } 11642292SN/A 11652980Sgblack@eecs.umich.edu std::cout << "\n"; 11662292SN/A} 11672292SN/A 11682292SN/Atemplate <class Impl> 11692292SN/Avoid 11702292SN/ADefaultIEW<Impl>::executeInsts() 11712292SN/A{ 11722292SN/A wbNumInst = 0; 11732292SN/A wbCycle = 0; 11742292SN/A 11756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 11766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 11772292SN/A 11783867Sbinkertn@umich.edu while (threads != end) { 11796221Snate@binkert.org ThreadID tid = *threads++; 11802292SN/A fetchRedirect[tid] = false; 11812292SN/A } 11822292SN/A 11832698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11847599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 11852698Sktlim@umich.edu// printAvailableInsts(); 11861062SN/A 11871062SN/A // Execute/writeback any instructions that are available. 11882333SN/A int insts_to_execute = fromIssue->size; 11892292SN/A int inst_num = 0; 11902333SN/A for (; inst_num < insts_to_execute; 11912326SN/A ++inst_num) { 11921062SN/A 11932292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11941062SN/A 11952333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11961062SN/A 11977720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 11987720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 11991062SN/A 120011246Sradhika.jagtap@ARM.com // Notify potential listeners that this instruction has started 120111246Sradhika.jagtap@ARM.com // executing 120211246Sradhika.jagtap@ARM.com ppExecute->notify(inst); 120311246Sradhika.jagtap@ARM.com 12041062SN/A // Check if the instruction is squashed; if so then skip it 12051062SN/A if (inst->isSquashed()) { 12068315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12078315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12088315Sgeoffrey.blake@arm.com inst->seqNum); 12091062SN/A 12101062SN/A // Consider this instruction executed so that commit can go 12111062SN/A // ahead and retire the instruction. 12121062SN/A inst->setExecuted(); 12131062SN/A 12142292SN/A // Not sure if I should set this here or just let commit try to 12152292SN/A // commit any squashed instructions. I like the latter a bit more. 12162292SN/A inst->setCanCommit(); 12171062SN/A 12181062SN/A ++iewExecSquashedInsts; 12191062SN/A 12201062SN/A continue; 12211062SN/A } 12221062SN/A 12232292SN/A Fault fault = NoFault; 12241062SN/A 12251062SN/A // Execute instruction. 12261062SN/A // Note that if the instruction faults, it will be handled 12271062SN/A // at the commit stage. 12287850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12292292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12301062SN/A "reference.\n"); 12311062SN/A 12321062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12331062SN/A if (inst->isLoad()) { 12342292SN/A // Loads will mark themselves as executed, and their writeback 12352292SN/A // event adds the instruction to the queue to commit 12362292SN/A fault = ldstQueue.executeLoad(inst); 12377944SGiacomo.Gabrielli@arm.com 12387944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12397944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12407944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12417944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12427944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12437944SGiacomo.Gabrielli@arm.com "load.\n"); 12447944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12457944SGiacomo.Gabrielli@arm.com continue; 12467944SGiacomo.Gabrielli@arm.com } 12477944SGiacomo.Gabrielli@arm.com 12487850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12498073SAli.Saidi@ARM.com inst->fault = NoFault; 12507850SMatt.Horsnell@arm.com } 12511062SN/A } else if (inst->isStore()) { 12522367SN/A fault = ldstQueue.executeStore(inst); 12531062SN/A 12547944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12557944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12567944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12577944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12587944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12597944SGiacomo.Gabrielli@arm.com "store.\n"); 12607944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12617944SGiacomo.Gabrielli@arm.com continue; 12627944SGiacomo.Gabrielli@arm.com } 12637944SGiacomo.Gabrielli@arm.com 12642292SN/A // If the store had a fault then it may not have a mem req 126510231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 12667782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12677782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12687782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12692367SN/A // Send this instruction to commit, also make sure iew stage 12702367SN/A // realizes there is activity. 12712367SN/A inst->setExecuted(); 12722367SN/A instToCommit(inst); 12732367SN/A activityThisCycle(); 12742292SN/A } 12752326SN/A 12762326SN/A // Store conditionals will mark themselves as 12772326SN/A // executed, and their writeback event will add the 12782326SN/A // instruction to the queue to commit. 12791062SN/A } else { 12802292SN/A panic("Unexpected memory type!\n"); 12811062SN/A } 12821062SN/A 12831062SN/A } else { 12847847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 12857847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 12867847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 12877847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 12887847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 12897847Sminkyu.jeong@arm.com inst->execute(); 129010231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 12917848SAli.Saidi@ARM.com inst->forwardOldRegs(); 12927847Sminkyu.jeong@arm.com } 12931062SN/A 12942292SN/A inst->setExecuted(); 12952292SN/A 12962292SN/A instToCommit(inst); 12971062SN/A } 12981062SN/A 12992301SN/A updateExeInstStats(inst); 13001681SN/A 13012326SN/A // Check if branch prediction was correct, if not then we need 13022326SN/A // to tell commit to squash in flight instructions. Only 13032326SN/A // handle this if there hasn't already been something that 13042107SN/A // redirects fetch in this group of instructions. 13051681SN/A 13062292SN/A // This probably needs to prioritize the redirects if a different 13072292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13082292SN/A // instruction first, so the branch resolution order will be correct. 13096221Snate@binkert.org ThreadID tid = inst->threadNumber; 13101062SN/A 13113732Sktlim@umich.edu if (!fetchRedirect[tid] || 13127852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13133732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13141062SN/A 13157856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13167856SMatt.Horsnell@arm.com // that have not been executed. 13177856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13187856SMatt.Horsnell@arm.com 13197856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13202292SN/A fetchRedirect[tid] = true; 13211062SN/A 13222292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13238674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13248674Snilay@cs.wisc.edu inst->readPredTarg()); 13257720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13268674Snilay@cs.wisc.edu inst->pcState()); 13271062SN/A // If incorrect, then signal the ROB that it must be squashed. 13282292SN/A squashDueToBranch(inst, tid); 13291062SN/A 133010023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 133110023Smatt.horsnell@ARM.com 13323795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13331062SN/A predictedTakenIncorrect++; 13342292SN/A } else { 13352292SN/A predictedNotTakenIncorrect++; 13361062SN/A } 13372292SN/A } else if (ldstQueue.violation(tid)) { 13384033Sktlim@umich.edu assert(inst->isMemRef()); 13392326SN/A // If there was an ordering violation, then get the 13402326SN/A // DynInst that caused the violation. Note that this 13412292SN/A // clears the violation signal. 13422292SN/A DynInstPtr violator; 13432292SN/A violator = ldstQueue.getMemDepViolator(tid); 13441062SN/A 13457720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13467720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13477720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 134813590Srekai.gonzalezalberquilla@arm.com inst->pcState(), inst->seqNum, inst->physEffAddr); 13497720Sgblack@eecs.umich.edu 13503732Sktlim@umich.edu fetchRedirect[tid] = true; 13513732Sktlim@umich.edu 13521062SN/A // Tell the instruction queue that a violation has occured. 13531062SN/A instQueue.violation(inst, violator); 13541062SN/A 13551062SN/A // Squash. 13568513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13571062SN/A 13581062SN/A ++memOrderViolationEvents; 13591062SN/A } 13604033Sktlim@umich.edu } else { 13614033Sktlim@umich.edu // Reset any state associated with redirects that will not 13624033Sktlim@umich.edu // be used. 13634033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13644033Sktlim@umich.edu assert(inst->isMemRef()); 13654033Sktlim@umich.edu 13664033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13674033Sktlim@umich.edu 13684033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13697720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13707720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 137113590Srekai.gonzalezalberquilla@arm.com inst->physEffAddr); 13724033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13734033Sktlim@umich.edu "already squashing\n"); 13744033Sktlim@umich.edu 13754033Sktlim@umich.edu ++memOrderViolationEvents; 13764033Sktlim@umich.edu } 13771062SN/A } 13781062SN/A } 13792292SN/A 13802348SN/A // Update and record activity if we processed any instructions. 13812292SN/A if (inst_num) { 13822292SN/A if (exeStatus == Idle) { 13832292SN/A exeStatus = Running; 13842292SN/A } 13852292SN/A 13862292SN/A updatedQueues = true; 13872292SN/A 13882292SN/A cpu->activityThisCycle(); 13892292SN/A } 13902292SN/A 13912292SN/A // Need to reset this in case a writeback event needs to write into the 13922292SN/A // iew queue. That way the writeback event will write into the correct 13932292SN/A // spot in the queue. 13942292SN/A wbNumInst = 0; 13957852SMatt.Horsnell@arm.com 13962107SN/A} 13972107SN/A 13982292SN/Atemplate <class Impl> 13992107SN/Avoid 14002292SN/ADefaultIEW<Impl>::writebackInsts() 14012107SN/A{ 14022326SN/A // Loop through the head of the time buffer and wake any 14032326SN/A // dependents. These instructions are about to write back. Also 14042326SN/A // mark scoreboard that this instruction is finally complete. 14052326SN/A // Either have IEW have direct access to scoreboard, or have this 14062326SN/A // as part of backwards communication. 14073958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14082292SN/A toCommit->insts[inst_num]; inst_num++) { 14092107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14106221Snate@binkert.org ThreadID tid = inst->threadNumber; 14112107SN/A 14127720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14137720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14142107SN/A 14152301SN/A iewInstsToCommit[tid]++; 141611246Sradhika.jagtap@ARM.com // Notify potential listeners that execution is complete for this 141711246Sradhika.jagtap@ARM.com // instruction. 141811246Sradhika.jagtap@ARM.com ppToCommit->notify(inst); 14192301SN/A 14202292SN/A // Some instructions will be sent to commit without having 14212292SN/A // executed because they need commit to handle them. 142210824SAndreas.Sandberg@ARM.com // E.g. Strictly ordered loads have not actually executed when they 14232292SN/A // are first sent to commit. Instead commit must tell the LSQ 142410824SAndreas.Sandberg@ARM.com // when it's ready to execute the strictly ordered load. 14252367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14262301SN/A int dependents = instQueue.wakeDependents(inst); 14272107SN/A 14282292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14292292SN/A //mark as Ready 143012105Snathanael.premillieu@arm.com DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 143112106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->index(), 143212106SRekai.GonzalezAlberquilla@arm.com inst->renamedDestRegIdx(i)->className()); 14332292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14342107SN/A } 14352301SN/A 14362348SN/A if (dependents) { 14372348SN/A producerInst[tid]++; 14382348SN/A consumerInst[tid]+= dependents; 14392348SN/A } 14402326SN/A writebackCount[tid]++; 14412107SN/A } 14422107SN/A } 14431060SN/A} 14441060SN/A 14451681SN/Atemplate<class Impl> 14461060SN/Avoid 14472292SN/ADefaultIEW<Impl>::tick() 14481060SN/A{ 14492292SN/A wbNumInst = 0; 14502292SN/A wbCycle = 0; 14511060SN/A 14522292SN/A wroteToTimeBuffer = false; 14532292SN/A updatedQueues = false; 14541060SN/A 145513590Srekai.gonzalezalberquilla@arm.com ldstQueue.tick(); 145613590Srekai.gonzalezalberquilla@arm.com 14572292SN/A sortInsts(); 14581060SN/A 14592326SN/A // Free function units marked as being freed this cycle. 14602326SN/A fuPool->processFreeUnits(); 14611062SN/A 14626221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14636221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14641060SN/A 14652326SN/A // Check stall and squash signals, dispatch any instructions. 14663867Sbinkertn@umich.edu while (threads != end) { 14676221Snate@binkert.org ThreadID tid = *threads++; 14681060SN/A 14692292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14701060SN/A 14712292SN/A checkSignalsAndUpdate(tid); 14722292SN/A dispatch(tid); 14731060SN/A } 14741060SN/A 14752292SN/A if (exeStatus != Squashing) { 14762292SN/A executeInsts(); 14771060SN/A 14782292SN/A writebackInsts(); 14792292SN/A 14802292SN/A // Have the instruction queue try to schedule any ready instructions. 14812292SN/A // (In actuality, this scheduling is for instructions that will 14822292SN/A // be executed next cycle.) 14832292SN/A instQueue.scheduleReadyInsts(); 14842292SN/A 14852292SN/A // Also should advance its own time buffers if the stage ran. 14862292SN/A // Not the best place for it, but this works (hopefully). 14872292SN/A issueToExecQueue.advance(); 14882292SN/A } 14892292SN/A 14902292SN/A bool broadcast_free_entries = false; 14912292SN/A 14922292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14932292SN/A exeStatus = Idle; 14942292SN/A updateLSQNextCycle = false; 14952292SN/A 14962292SN/A broadcast_free_entries = true; 14972292SN/A } 14982292SN/A 14992292SN/A // Writeback any stores using any leftover bandwidth. 15001681SN/A ldstQueue.writebackStores(); 15011681SN/A 15021061SN/A // Check the committed load/store signals to see if there's a load 15031061SN/A // or store to commit. Also check if it's being told to execute a 15041061SN/A // nonspeculative instruction. 15051681SN/A // This is pretty inefficient... 15062292SN/A 15073867Sbinkertn@umich.edu threads = activeThreads->begin(); 15083867Sbinkertn@umich.edu while (threads != end) { 15096221Snate@binkert.org ThreadID tid = (*threads++); 15102292SN/A 15112292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15122292SN/A 15132348SN/A // Update structures based on instructions committed. 15142292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15152292SN/A !fromCommit->commitInfo[tid].squash && 15162292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15172292SN/A 15182292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15192292SN/A 15202292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15212292SN/A 15222292SN/A updateLSQNextCycle = true; 15232292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15242292SN/A } 15252292SN/A 15262292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15272292SN/A 15282292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 152910824SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo[tid].strictlyOrdered) { 153010824SAndreas.Sandberg@ARM.com instQueue.replayMemInst( 153110824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad); 153210824SAndreas.Sandberg@ARM.com fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 15332292SN/A } else { 15342292SN/A instQueue.scheduleNonSpec( 15352292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15362292SN/A } 15372292SN/A } 15382292SN/A 15392292SN/A if (broadcast_free_entries) { 15402292SN/A toFetch->iewInfo[tid].iqCount = 15412292SN/A instQueue.getCount(tid); 15422292SN/A toFetch->iewInfo[tid].ldstqCount = 15432292SN/A ldstQueue.getCount(tid); 15442292SN/A 15452292SN/A toRename->iewInfo[tid].usedIQ = true; 15462292SN/A toRename->iewInfo[tid].freeIQEntries = 154710164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 15482292SN/A toRename->iewInfo[tid].usedLSQ = true; 154910239Sbinhpham@cs.rutgers.edu 155010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 155110239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 155210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 155310239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 15542292SN/A 15552292SN/A wroteToTimeBuffer = true; 15562292SN/A } 15572292SN/A 15582292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15592292SN/A tid, toRename->iewInfo[tid].dispatched); 15601061SN/A } 15611061SN/A 15622292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 156310239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 15642292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 156510239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 15662292SN/A 15672292SN/A updateStatus(); 15682292SN/A 15692292SN/A if (wroteToTimeBuffer) { 15702292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15712292SN/A cpu->activityThisCycle(); 15721061SN/A } 15731060SN/A} 15741060SN/A 15752301SN/Atemplate <class Impl> 15761060SN/Avoid 157713429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 15781060SN/A{ 15796221Snate@binkert.org ThreadID tid = inst->threadNumber; 15801060SN/A 15812669Sktlim@umich.edu iewExecutedInsts++; 15821060SN/A 15838471SGiacomo.Gabrielli@arm.com#if TRACING_ON 15849527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 15859527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 15869527SMatt.Horsnell@arm.com } 15878471SGiacomo.Gabrielli@arm.com#endif 15888471SGiacomo.Gabrielli@arm.com 15892301SN/A // 15902301SN/A // Control operations 15912301SN/A // 15922301SN/A if (inst->isControl()) 15936221Snate@binkert.org iewExecutedBranches[tid]++; 15941060SN/A 15952301SN/A // 15962301SN/A // Memory operations 15972301SN/A // 15982301SN/A if (inst->isMemRef()) { 15996221Snate@binkert.org iewExecutedRefs[tid]++; 16001060SN/A 16012301SN/A if (inst->isLoad()) { 16026221Snate@binkert.org iewExecLoadInsts[tid]++; 16031060SN/A } 16041060SN/A } 16051060SN/A} 16067598Sminkyu.jeong@arm.com 16077598Sminkyu.jeong@arm.comtemplate <class Impl> 16087598Sminkyu.jeong@arm.comvoid 160913429Srekai.gonzalezalberquilla@arm.comDefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 16107598Sminkyu.jeong@arm.com{ 16117598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16127598Sminkyu.jeong@arm.com 16137598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16147852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16157598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16167598Sminkyu.jeong@arm.com 16177598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16187598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16197598Sminkyu.jeong@arm.com 16207598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16217598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16227720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16237598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16247720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16257720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16267598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16277598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16287598Sminkyu.jeong@arm.com 16297598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16307598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16317598Sminkyu.jeong@arm.com } else { 16327598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16337598Sminkyu.jeong@arm.com } 16347598Sminkyu.jeong@arm.com } 16357598Sminkyu.jeong@arm.com } 16367598Sminkyu.jeong@arm.com} 16379944Smatt.horsnell@ARM.com 16389944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1639