iew_impl.hh revision 13453
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2010-2013 ARM Limited 37598Sminkyu.jeong@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 142326SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 411689SN/A * Authors: Kevin Lim 421689SN/A */ 431060SN/A 441060SN/A#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 451689SN/A#define __CPU_O3_IEW_IMPL_IMPL_HH__ 461060SN/A 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 498230Snate@binkert.org// communication happens simultaneously. 506658Snate@binkert.org 512292SN/A#include <queue> 521717SN/A 538229Snate@binkert.org#include "arch/utility.hh" 548232Snate@binkert.org#include "config/the_isa.hh" 558232Snate@binkert.org#include "cpu/checker/cpu.hh" 568232Snate@binkert.org#include "cpu/o3/fu_pool.hh" 575529Snate@binkert.org#include "cpu/o3/iew.hh" 581060SN/A#include "cpu/timebuf.hh" 596221Snate@binkert.org#include "debug/Activity.hh" 606221Snate@binkert.org#include "debug/Drain.hh" 611681SN/A#include "debug/IEW.hh" 625529Snate@binkert.org#include "debug/O3PipeView.hh" 632873Sktlim@umich.edu#include "params/DerivO3CPU.hh" 644329Sktlim@umich.edu 654329Sktlim@umich.eduusing namespace std; 664329Sktlim@umich.edu 672292SN/Atemplate<class Impl> 682292SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692292SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 702292SN/A cpu(_cpu), 712820Sktlim@umich.edu instQueue(_cpu, this, params), 722292SN/A ldstQueue(_cpu, this, params), 732820Sktlim@umich.edu fuPool(params->fuPool), 742820Sktlim@umich.edu commitToIEWDelay(params->commitToIEWDelay), 755529Snate@binkert.org renameToIEWDelay(params->renameToIEWDelay), 762307SN/A issueToExecuteDelay(params->issueToExecuteDelay), 771060SN/A dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 792292SN/A wbNumInst(0), 802292SN/A wbCycle(0), 811060SN/A wbWidth(params->wbWidth), 821060SN/A numThreads(params->numThreads) 831060SN/A{ 841060SN/A if (dispatchWidth > Impl::MaxWidth) 851060SN/A fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 861060SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 871681SN/A dispatchWidth, static_cast<int>(Impl::MaxWidth)); 886221Snate@binkert.org if (issueWidth > Impl::MaxWidth) 896221Snate@binkert.org fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 906221Snate@binkert.org "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 916221Snate@binkert.org issueWidth, static_cast<int>(Impl::MaxWidth)); 922292SN/A if (wbWidth > Impl::MaxWidth) 932292SN/A fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 942820Sktlim@umich.edu "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 952820Sktlim@umich.edu wbWidth, static_cast<int>(Impl::MaxWidth)); 962292SN/A 972292SN/A _status = Active; 982820Sktlim@umich.edu exeStatus = Running; 992820Sktlim@umich.edu wbStatus = Idle; 1002292SN/A 1012292SN/A // Setup wire to read instructions coming from issue. 1022292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1032292SN/A 1042292SN/A // Instruction queue needs the queue between issue and execute. 1052292SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1062292SN/A 1072292SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1081060SN/A dispatchStatus[tid] = Running; 1091060SN/A fetchRedirect[tid] = false; 1101681SN/A } 1111062SN/A 1122292SN/A updateLSQNextCycle = false; 1131062SN/A 1142301SN/A skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1152301SN/A} 1161062SN/A 1172727Sktlim@umich.edutemplate <class Impl> 1181062SN/Astd::string 1191062SN/ADefaultIEW<Impl>::name() const 1201062SN/A{ 1211062SN/A return cpu->name() + ".iew"; 1221062SN/A} 1231062SN/A 1241062SN/Atemplate <class Impl> 1251062SN/Avoid 1261062SN/ADefaultIEW<Impl>::regProbePoints() 1271062SN/A{ 1281062SN/A ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1291062SN/A ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1301062SN/A /** 1311062SN/A * Probe point with dynamic instruction as the argument used to probe when 1321062SN/A * an instruction starts to execute. 1331062SN/A */ 1341062SN/A ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1351062SN/A "Execute"); 1361062SN/A /** 1371062SN/A * Probe point with dynamic instruction as the argument used to probe when 1381062SN/A * an instruction execution completes and it is marked ready to commit. 1391062SN/A */ 1401062SN/A ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), 1411062SN/A "ToCommit"); 1421062SN/A} 1431062SN/A 1441062SN/Atemplate <class Impl> 1451062SN/Avoid 1461062SN/ADefaultIEW<Impl>::regStats() 1471062SN/A{ 1481062SN/A using namespace Stats; 1491062SN/A 1501062SN/A instQueue.regStats(); 1511062SN/A ldstQueue.regStats(); 1521062SN/A 1531062SN/A iewIdleCycles 1541062SN/A .name(name() + ".iewIdleCycles") 1551062SN/A .desc("Number of cycles IEW is idle"); 1561062SN/A 1571062SN/A iewSquashCycles 1581062SN/A .name(name() + ".iewSquashCycles") 1592292SN/A .desc("Number of cycles IEW is squashing"); 1602292SN/A 1612292SN/A iewBlockCycles 1622292SN/A .name(name() + ".iewBlockCycles") 1631062SN/A .desc("Number of cycles IEW is blocking"); 1641062SN/A 1651062SN/A iewUnblockCycles 1661062SN/A .name(name() + ".iewUnblockCycles") 1671062SN/A .desc("Number of cycles IEW is unblocking"); 1681062SN/A 1691062SN/A iewDispatchedInsts 1702292SN/A .name(name() + ".iewDispatchedInsts") 1712292SN/A .desc("Number of instructions dispatched to IQ"); 1722292SN/A 1732292SN/A iewDispSquashedInsts 1742292SN/A .name(name() + ".iewDispSquashedInsts") 1752292SN/A .desc("Number of squashed instructions skipped by dispatch"); 1762292SN/A 1772292SN/A iewDispLoadInsts 1782292SN/A .name(name() + ".iewDispLoadInsts") 1792292SN/A .desc("Number of dispatched load instructions"); 1802301SN/A 1812727Sktlim@umich.edu iewDispStoreInsts 1822353SN/A .name(name() + ".iewDispStoreInsts") 1832727Sktlim@umich.edu .desc("Number of dispatched store instructions"); 1842727Sktlim@umich.edu 1852727Sktlim@umich.edu iewDispNonSpecInsts 1866221Snate@binkert.org .name(name() + ".iewDispNonSpecInsts") 1872353SN/A .desc("Number of dispatched non-speculative instructions"); 1882727Sktlim@umich.edu 1892727Sktlim@umich.edu iewIQFullEvents 1902727Sktlim@umich.edu .name(name() + ".iewIQFullEvents") 1912727Sktlim@umich.edu .desc("Number of times the IQ has become full, causing a stall"); 1922353SN/A 1932727Sktlim@umich.edu iewLSQFullEvents 1942727Sktlim@umich.edu .name(name() + ".iewLSQFullEvents") 1952727Sktlim@umich.edu .desc("Number of times the LSQ has become full, causing a stall"); 1966221Snate@binkert.org 1978240Snate@binkert.org memOrderViolationEvents 1982301SN/A .name(name() + ".memOrderViolationEvents") 1992727Sktlim@umich.edu .desc("Number of memory order violations"); 2002301SN/A 2012727Sktlim@umich.edu predictedTakenIncorrect 2026221Snate@binkert.org .name(name() + ".predictedTakenIncorrect") 2038240Snate@binkert.org .desc("Number of branches that were predicted taken incorrectly"); 2042301SN/A 2052727Sktlim@umich.edu predictedNotTakenIncorrect 2062301SN/A .name(name() + ".predictedNotTakenIncorrect") 2072727Sktlim@umich.edu .desc("Number of branches that were predicted not taken incorrectly"); 2086221Snate@binkert.org 2098240Snate@binkert.org branchMispredicts 2102301SN/A .name(name() + ".branchMispredicts") 2112727Sktlim@umich.edu .desc("Number of branch mispredicts detected at execute"); 2122301SN/A 2132727Sktlim@umich.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2146221Snate@binkert.org 2158240Snate@binkert.org iewExecutedInsts 2162301SN/A .name(name() + ".iewExecutedInsts") 2172727Sktlim@umich.edu .desc("Number of executed instructions"); 2182301SN/A 2192301SN/A iewExecLoadInsts 2208240Snate@binkert.org .init(cpu->numThreads) 2212301SN/A .name(name() + ".iewExecLoadInsts") 2222727Sktlim@umich.edu .desc("Number of load instructions executed") 2232727Sktlim@umich.edu .flags(total); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu iewExecSquashedInsts 2268240Snate@binkert.org .name(name() + ".iewExecSquashedInsts") 2272727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu iewExecutedSwp 2302727Sktlim@umich.edu .init(cpu->numThreads) 2312301SN/A .name(name() + ".exec_swp") 2322301SN/A .desc("number of swp insts executed") 2336221Snate@binkert.org .flags(total); 2348240Snate@binkert.org 2352301SN/A iewExecutedNop 2362727Sktlim@umich.edu .init(cpu->numThreads) 2372301SN/A .name(name() + ".exec_nop") 2382326SN/A .desc("number of nop insts executed") 2396221Snate@binkert.org .flags(total); 2408240Snate@binkert.org 2412301SN/A iewExecutedRefs 2422727Sktlim@umich.edu .init(cpu->numThreads) 2432301SN/A .name(name() + ".exec_refs") 2442326SN/A .desc("number of memory reference insts executed") 2456221Snate@binkert.org .flags(total); 2468240Snate@binkert.org 2472301SN/A iewExecutedBranches 2482727Sktlim@umich.edu .init(cpu->numThreads) 2492301SN/A .name(name() + ".exec_branches") 2502326SN/A .desc("Number of branches executed") 2516221Snate@binkert.org .flags(total); 2528240Snate@binkert.org 2532301SN/A iewExecStoreInsts 2542727Sktlim@umich.edu .name(name() + ".exec_stores") 2552301SN/A .desc("Number of stores executed") 2562326SN/A .flags(total); 2576221Snate@binkert.org iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2588240Snate@binkert.org 2592301SN/A iewExecRate 2602727Sktlim@umich.edu .name(name() + ".exec_rate") 2612301SN/A .desc("Inst execution rate") 2622326SN/A .flags(total); 2638240Snate@binkert.org 2642301SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2652727Sktlim@umich.edu 2662301SN/A iewInstsToCommit 2672326SN/A .init(cpu->numThreads) 2682301SN/A .name(name() + ".wb_sent") 2692326SN/A .desc("cumulative count of insts sent to commit") 2708240Snate@binkert.org .flags(total); 2712301SN/A 2722727Sktlim@umich.edu writebackCount 2732301SN/A .init(cpu->numThreads) 2742326SN/A .name(name() + ".wb_count") 2752301SN/A .desc("cumulative count of insts written-back") 2762326SN/A .flags(total); 2778240Snate@binkert.org 2782301SN/A producerInst 2792727Sktlim@umich.edu .init(cpu->numThreads) 2802326SN/A .name(name() + ".wb_producers") 2811062SN/A .desc("num instructions producing a value") 2821062SN/A .flags(total); 2831681SN/A 2841060SN/A consumerInst 2852292SN/A .init(cpu->numThreads) 2861060SN/A .name(name() + ".wb_consumers") 2876221Snate@binkert.org .desc("num instructions consuming a value") 2882292SN/A .flags(total); 2892292SN/A 2902292SN/A wbFanout 2912292SN/A .name(name() + ".wb_fanout") 2922292SN/A .desc("average fanout of values written-back") 2932292SN/A .flags(total); 2942292SN/A 2952292SN/A wbFanout = producerInst / consumerInst; 2962292SN/A 2972733Sktlim@umich.edu wbRate 2981060SN/A .name(name() + ".wb_rate") 2991060SN/A .desc("insts written-back per cycle") 3001681SN/A .flags(total); 3011060SN/A wbRate = writebackCount / cpu->numCycles; 3022292SN/A} 3031060SN/A 3041060SN/Atemplate<class Impl> 3051060SN/Avoid 3061060SN/ADefaultIEW<Impl>::startupStage() 3071060SN/A{ 3081060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3091060SN/A toRename->iewInfo[tid].usedIQ = true; 3101060SN/A toRename->iewInfo[tid].freeIQEntries = 3111060SN/A instQueue.numFreeEntries(tid); 3122292SN/A 3132292SN/A toRename->iewInfo[tid].usedLSQ = true; 3141060SN/A toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 3151060SN/A toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3161060SN/A } 3171060SN/A 3181681SN/A // Initialize the checker's dcache port here 3191060SN/A if (cpu->checker) { 3202292SN/A cpu->checker->setDcachePort(&cpu->getDataPort()); 3211060SN/A } 3221060SN/A 3231060SN/A cpu->activateStage(O3CPU::IEWIdx); 3241060SN/A} 3251060SN/A 3261060SN/Atemplate<class Impl> 3271060SN/Avoid 3281681SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3291060SN/A{ 3302292SN/A timeBuffer = tb_ptr; 3311060SN/A 3321060SN/A // Setup wire to read information from time buffer, from commit. 3331060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3341060SN/A 3351060SN/A // Setup wire to write information back to previous stages. 3361060SN/A toRename = timeBuffer->getWire(0); 3371060SN/A 3381681SN/A toFetch = timeBuffer->getWire(0); 3391060SN/A 3406221Snate@binkert.org // Instruction queue also needs main time buffer. 3411060SN/A instQueue.setTimeBuffer(tb_ptr); 3422292SN/A} 3432292SN/A 3442292SN/Atemplate<class Impl> 3452292SN/Avoid 3461060SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3471060SN/A{ 3481681SN/A renameQueue = rq_ptr; 3491060SN/A 3502292SN/A // Setup wire to read information from rename queue. 3511060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3522292SN/A} 3531060SN/A 3541060SN/Atemplate<class Impl> 3552307SN/Avoid 3562863Sktlim@umich.eduDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3572843Sktlim@umich.edu{ 3582307SN/A iewQueue = iq_ptr; 3592843Sktlim@umich.edu 3602843Sktlim@umich.edu // Setup wire to write instructions to commit. 3612863Sktlim@umich.edu toCommit = iewQueue->getWire(0); 3621681SN/A} 3631681SN/A 3642316SN/Atemplate<class Impl> 3651681SN/Avoid 3662843Sktlim@umich.eduDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3672843Sktlim@umich.edu{ 3682843Sktlim@umich.edu activeThreads = at_ptr; 3692843Sktlim@umich.edu 3702843Sktlim@umich.edu ldstQueue.setActiveThreads(at_ptr); 3712843Sktlim@umich.edu instQueue.setActiveThreads(at_ptr); 3722843Sktlim@umich.edu} 3731681SN/A 3742348SN/Atemplate<class Impl> 3752307SN/Avoid 3762367SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3772367SN/A{ 3781681SN/A scoreboard = sb_ptr; 3792307SN/A} 3802307SN/A 3812307SN/Atemplate <class Impl> 3822307SN/Abool 3836221Snate@binkert.orgDefaultIEW<Impl>::isDrained() const 3846221Snate@binkert.org{ 3856221Snate@binkert.org bool drained = ldstQueue.isDrained() && instQueue.isDrained(); 3866221Snate@binkert.org 3876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3882307SN/A if (!insts[tid].empty()) { 3891681SN/A DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3901681SN/A drained = false; 3912307SN/A } 3921681SN/A if (!skidBuffer[tid].empty()) { 3932307SN/A DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3941060SN/A drained = false; 3952348SN/A } 3962307SN/A drained = drained && dispatchStatus[tid] == Running; 3972307SN/A } 3982307SN/A 3992307SN/A // Also check the FU pool as instructions are "stored" in FU 4001060SN/A // completion events until they are done and not accounted for 4012307SN/A // above 4022307SN/A if (drained && !fuPool->isDrained()) { 4032307SN/A DPRINTF(Drain, "FU pool still busy.\n"); 4041060SN/A drained = false; 4052307SN/A } 4062307SN/A 4071060SN/A return drained; 4086221Snate@binkert.org} 4096221Snate@binkert.org 4106221Snate@binkert.orgtemplate <class Impl> 4116221Snate@binkert.orgvoid 4122307SN/ADefaultIEW<Impl>::drainSanityCheck() const 4131060SN/A{ 4142307SN/A assert(isDrained()); 4152307SN/A 4162873Sktlim@umich.edu instQueue.drainSanityCheck(); 4172307SN/A ldstQueue.drainSanityCheck(); 4181060SN/A} 4191060SN/A 4201060SN/Atemplate <class Impl> 4211681SN/Avoid 4221060SN/ADefaultIEW<Impl>::takeOverFrom() 4236221Snate@binkert.org{ 4242107SN/A // Reset all state. 4256221Snate@binkert.org _status = Active; 4262107SN/A exeStatus = Running; 4272292SN/A wbStatus = Idle; 4282292SN/A 4292107SN/A instQueue.takeOverFrom(); 4302292SN/A ldstQueue.takeOverFrom(); 4312326SN/A fuPool->takeOverFrom(); 4322292SN/A 4332107SN/A startupStage(); 4342292SN/A cpu->activityThisCycle(); 4352935Sksewell@umich.edu 4364632Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 4372935Sksewell@umich.edu dispatchStatus[tid] = Running; 4382292SN/A fetchRedirect[tid] = false; 4392292SN/A } 4402292SN/A 4412292SN/A updateLSQNextCycle = false; 4422292SN/A 4432107SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4442292SN/A issueToExecQueue.advance(); 4452107SN/A } 4462292SN/A} 4472292SN/A 4482107SN/Atemplate<class Impl> 4492702Sktlim@umich.eduvoid 4502107SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4512107SN/A{ 4522107SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4532107SN/A 4546221Snate@binkert.org // Tell the IQ to start squashing. 4552292SN/A instQueue.squash(tid); 4567720Sgblack@eecs.umich.edu 4577720Sgblack@eecs.umich.edu // Tell the LDSTQ to start squashing. 4582292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4597852SMatt.Horsnell@arm.com updatedQueues = true; 4607852SMatt.Horsnell@arm.com 4617852SMatt.Horsnell@arm.com // Clear the skid buffer in case it has any data in it. 4627852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4637852SMatt.Horsnell@arm.com tid, fromCommit->commitInfo[tid].doneSeqNum); 4642935Sksewell@umich.edu 4657852SMatt.Horsnell@arm.com while (!skidBuffer[tid].empty()) { 4667852SMatt.Horsnell@arm.com if (skidBuffer[tid].front()->isLoad()) { 4672292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 4687852SMatt.Horsnell@arm.com } 4697852SMatt.Horsnell@arm.com if (skidBuffer[tid].front()->isStore()) { 4707852SMatt.Horsnell@arm.com toRename->iewInfo[tid].dispatchedToSQ++; 4712292SN/A } 4727852SMatt.Horsnell@arm.com 4737852SMatt.Horsnell@arm.com toRename->iewInfo[tid].dispatched++; 4747852SMatt.Horsnell@arm.com 4752292SN/A skidBuffer[tid].pop(); 4762292SN/A } 4772292SN/A 4782292SN/A emptyRenameInsts(tid); 4796221Snate@binkert.org} 4802292SN/A 4812292SN/Atemplate<class Impl> 4827720Sgblack@eecs.umich.eduvoid 4832292SN/ADefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) 4847852SMatt.Horsnell@arm.com{ 4857852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4867852SMatt.Horsnell@arm.com "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4877852SMatt.Horsnell@arm.com 4888298Sgeoffrey.blake@arm.com if (!toCommit->squash[tid] || 4898298Sgeoffrey.blake@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4908298Sgeoffrey.blake@arm.com toCommit->squash[tid] = true; 4918298Sgeoffrey.blake@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4928298Sgeoffrey.blake@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4938298Sgeoffrey.blake@arm.com 4948298Sgeoffrey.blake@arm.com TheISA::PCState pc = inst->pcState(); 4958298Sgeoffrey.blake@arm.com TheISA::advancePC(pc, inst->staticInst); 4968298Sgeoffrey.blake@arm.com 4978298Sgeoffrey.blake@arm.com toCommit->pc[tid] = pc; 4987852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4998137SAli.Saidi@ARM.com toCommit->includeSquashInst[tid] = false; 5002292SN/A 5017852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5022292SN/A } 5037852SMatt.Horsnell@arm.com 5047852SMatt.Horsnell@arm.com} 5052292SN/A 5062292SN/Atemplate<class Impl> 5072292SN/Avoid 5082292SN/ADefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) 5096221Snate@binkert.org{ 5102292SN/A DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5112292SN/A "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5127720Sgblack@eecs.umich.edu // Need to include inst->seqNum in the following comparison to cover the 5137852SMatt.Horsnell@arm.com // corner case when a branch misprediction and a memory violation for the 5147852SMatt.Horsnell@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5157852SMatt.Horsnell@arm.com // case the memory violator should take precedence over the branch 5162292SN/A // misprediction because it requires the violator itself to be included in 5177852SMatt.Horsnell@arm.com // the squash. 5187852SMatt.Horsnell@arm.com if (!toCommit->squash[tid] || 5198137SAli.Saidi@ARM.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5202292SN/A toCommit->squash[tid] = true; 5217852SMatt.Horsnell@arm.com 5227852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5232292SN/A toCommit->pc[tid] = inst->pcState(); 5247852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = NULL; 5252292SN/A 5267852SMatt.Horsnell@arm.com // Must include the memory violator in the squash. 5277852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5282292SN/A 5292292SN/A wroteToTimeBuffer = true; 5302292SN/A } 5312292SN/A} 5326221Snate@binkert.org 5332292SN/Atemplate<class Impl> 5342292SN/Avoid 5352292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5362292SN/A{ 5372292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5382292SN/A 5392292SN/A if (dispatchStatus[tid] != Blocked && 5402292SN/A dispatchStatus[tid] != Unblocking) { 5412292SN/A toRename->iewBlock[tid] = true; 5422292SN/A wroteToTimeBuffer = true; 5432292SN/A } 5442292SN/A 5452292SN/A // Add the current inputs to the skid buffer so they can be 5462292SN/A // reprocessed when this stage unblocks. 5472292SN/A skidInsert(tid); 5482292SN/A 5492292SN/A dispatchStatus[tid] = Blocked; 5502292SN/A} 5516221Snate@binkert.org 5522292SN/Atemplate<class Impl> 5532292SN/Avoid 5542292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5552292SN/A{ 5562292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5572292SN/A "buffer %u.\n",tid, tid); 5582292SN/A 5592292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5602292SN/A // Also switch status to running. 5612292SN/A if (skidBuffer[tid].empty()) { 5622292SN/A toRename->iewUnblock[tid] = true; 5632292SN/A wroteToTimeBuffer = true; 5642292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5652292SN/A dispatchStatus[tid] = Running; 5662292SN/A } 5672292SN/A} 5682292SN/A 5691060SN/Atemplate<class Impl> 5701681SN/Avoid 5711060SN/ADefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst) 5721060SN/A{ 5732292SN/A instQueue.wakeDependents(inst); 5742292SN/A} 5752292SN/A 5762292SN/Atemplate<class Impl> 5772292SN/Avoid 5782292SN/ADefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst) 5791681SN/A{ 5801681SN/A instQueue.rescheduleMemInst(inst); 5811060SN/A} 5822292SN/A 5831060SN/Atemplate<class Impl> 5842292SN/Avoid 5852292SN/ADefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst) 5861060SN/A{ 5872292SN/A instQueue.replayMemInst(inst); 5882292SN/A} 5892292SN/A 5902292SN/Atemplate<class Impl> 5913221Sktlim@umich.eduvoid 5923221Sktlim@umich.eduDefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst) 5933221Sktlim@umich.edu{ 5943221Sktlim@umich.edu instQueue.blockMemInst(inst); 5953221Sktlim@umich.edu} 5962292SN/A 5972292SN/Atemplate<class Impl> 5982292SN/Avoid 5992292SN/ADefaultIEW<Impl>::cacheUnblocked() 6002326SN/A{ 6012292SN/A instQueue.cacheUnblocked(); 6022292SN/A} 6032820Sktlim@umich.edu 6042292SN/Atemplate<class Impl> 6052292SN/Avoid 6062292SN/ADefaultIEW<Impl>::instToCommit(const DynInstPtr& inst) 6072292SN/A{ 6082353SN/A // This function should not be called after writebackInsts in a 6092292SN/A // single cycle. That will cause problems with an instruction 6102292SN/A // being added to the queue to commit without being processed by 6112353SN/A // writebackInsts prior to being sent to commit. 6122353SN/A 6132292SN/A // First check the time slot that this instruction will write 6142292SN/A // to. If there are free write ports at the time, then go ahead 6152292SN/A // and write the instruction to that time. If there are not, 6162292SN/A // keep looking back to see where's the first time there's a 6172292SN/A // free slot. 6182292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6192292SN/A ++wbNumInst; 6202292SN/A if (wbNumInst == wbWidth) { 6212292SN/A ++wbCycle; 6222292SN/A wbNumInst = 0; 6232292SN/A } 6242292SN/A } 6252731Sktlim@umich.edu 6262292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6272292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6282292SN/A // Add finished instruction to queue to commit. 6292292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6302292SN/A (*iewQueue)[wbCycle].size++; 6312292SN/A} 6322292SN/A 6332292SN/Atemplate <class Impl> 6346221Snate@binkert.orgunsigned 6352292SN/ADefaultIEW<Impl>::validInstsFromRename() 6362292SN/A{ 6372292SN/A unsigned inst_count = 0; 6382292SN/A 6392292SN/A for (int i=0; i<fromRename->size; i++) { 6402292SN/A if (!fromRename->insts[i]->isSquashed()) 6412292SN/A inst_count++; 6422292SN/A } 6437720Sgblack@eecs.umich.edu 6442292SN/A return inst_count; 6457720Sgblack@eecs.umich.edu} 6462292SN/A 6472292SN/Atemplate<class Impl> 6482292SN/Avoid 6492292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6502292SN/A{ 6512292SN/A DynInstPtr inst = NULL; 6522292SN/A 6532292SN/A while (!insts[tid].empty()) { 6542292SN/A inst = insts[tid].front(); 6552292SN/A 6562292SN/A insts[tid].pop(); 6572292SN/A 6582292SN/A DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6592292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6606221Snate@binkert.org inst->pcState(),tid); 6616221Snate@binkert.org 6622292SN/A skidBuffer[tid].push(inst); 6633867Sbinkertn@umich.edu } 6646221Snate@binkert.org 6653867Sbinkertn@umich.edu assert(skidBuffer[tid].size() <= skidBufferMax && 6662292SN/A "Skidbuffer Exceeded Max Size"); 6672292SN/A} 6682292SN/A 6692292SN/Atemplate<class Impl> 6702292SN/Aint 6712292SN/ADefaultIEW<Impl>::skidCount() 6722292SN/A{ 6732292SN/A int max=0; 6742292SN/A 6752292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6762292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6776221Snate@binkert.org 6786221Snate@binkert.org while (threads != end) { 6792292SN/A ThreadID tid = *threads++; 6803867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6816221Snate@binkert.org if (max < thread_count) 6823867Sbinkertn@umich.edu max = thread_count; 6833867Sbinkertn@umich.edu } 6842292SN/A 6852292SN/A return max; 6862292SN/A} 6872292SN/A 6881062SN/Atemplate<class Impl> 6891062SN/Abool 6901681SN/ADefaultIEW<Impl>::skidsEmpty() 6911062SN/A{ 6922292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6931062SN/A list<ThreadID>::iterator end = activeThreads->end(); 6942292SN/A 6951062SN/A while (threads != end) { 6966221Snate@binkert.org ThreadID tid = *threads++; 6976221Snate@binkert.org 6981062SN/A if (!skidBuffer[tid].empty()) 6993867Sbinkertn@umich.edu return false; 7006221Snate@binkert.org } 7011062SN/A 7022292SN/A return true; 7032292SN/A} 7042292SN/A 7052292SN/Atemplate <class Impl> 7062292SN/Avoid 7071062SN/ADefaultIEW<Impl>::updateStatus() 7082292SN/A{ 7092292SN/A bool any_unblocking = false; 7102292SN/A 7117897Shestness@cs.utexas.edu list<ThreadID>::iterator threads = activeThreads->begin(); 7122292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7132292SN/A 7142292SN/A while (threads != end) { 7151062SN/A ThreadID tid = *threads++; 7162292SN/A 7171062SN/A if (dispatchStatus[tid] == Unblocking) { 7182292SN/A any_unblocking = true; 7192292SN/A break; 7202292SN/A } 7212292SN/A } 7222292SN/A 7232292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7241062SN/A // and there's no stores waiting to write back, and dispatch is not 7252292SN/A // unblocking, then there is no internal activity for the IEW stage. 7261062SN/A instQueue.intInstQueueReads++; 7272292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7281062SN/A !ldstQueue.willWB() && !any_unblocking) { 7291062SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7301062SN/A 7311681SN/A deactivateStage(); 7321062SN/A 7332292SN/A _status = Inactive; 7341062SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7352292SN/A ldstQueue.willWB() || 7362292SN/A any_unblocking)) { 7372292SN/A // Otherwise there is internal activity. Set to active. 7381062SN/A DPRINTF(IEW, "IEW switching to active\n"); 7392292SN/A 7402292SN/A activateStage(); 7416221Snate@binkert.org 7422292SN/A _status = Active; 7432292SN/A } 7442292SN/A} 7452292SN/A 7461062SN/Atemplate <class Impl> 7472292SN/Avoid 7482292SN/ADefaultIEW<Impl>::resetEntries() 7492292SN/A{ 7502292SN/A instQueue.resetEntries(); 7512292SN/A ldstQueue.resetEntries(); 7522292SN/A} 7532292SN/A 7542292SN/Atemplate <class Impl> 7556221Snate@binkert.orgbool 7562292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7572292SN/A{ 7582292SN/A bool ret_val(false); 7592292SN/A 7602292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7612292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7622292SN/A ret_val = true; 7632292SN/A } else if (instQueue.isFull(tid)) { 7642292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7652292SN/A ret_val = true; 7662292SN/A } 7672292SN/A 7682292SN/A return ret_val; 7692292SN/A} 7702292SN/A 7712292SN/Atemplate <class Impl> 7722292SN/Avoid 7732292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7742292SN/A{ 7752292SN/A // Check if there's a squash signal, squash if there is 7762292SN/A // Check stall signals, block if there is. 7772292SN/A // If status was Blocked 7782292SN/A // if so then go to unblocking 7792292SN/A // If status was Squashing 7802292SN/A // check if squashing is not high. Switch to running this cycle. 7812292SN/A 7822292SN/A if (fromCommit->commitInfo[tid].squash) { 7832292SN/A squash(tid); 7842292SN/A 7852292SN/A if (dispatchStatus[tid] == Blocked || 7862292SN/A dispatchStatus[tid] == Unblocking) { 7872292SN/A toRename->iewUnblock[tid] = true; 7882292SN/A wroteToTimeBuffer = true; 7892292SN/A } 7902292SN/A 7916221Snate@binkert.org dispatchStatus[tid] = Squashing; 7922292SN/A fetchRedirect[tid] = false; 7932292SN/A return; 7942292SN/A } 7952292SN/A 7962292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7972292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7982292SN/A 7992292SN/A dispatchStatus[tid] = Squashing; 8002292SN/A emptyRenameInsts(tid); 8012292SN/A wroteToTimeBuffer = true; 8022292SN/A } 8032292SN/A 8042292SN/A if (checkStall(tid)) { 8052292SN/A block(tid); 8062292SN/A dispatchStatus[tid] = Blocked; 8072292SN/A return; 8082292SN/A } 8092292SN/A 8102292SN/A if (dispatchStatus[tid] == Blocked) { 8112292SN/A // Status from previous cycle was blocked, but there are no more stall 8122292SN/A // conditions. Switch over to unblocking. 8132292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8142292SN/A tid); 8152292SN/A 8162292SN/A dispatchStatus[tid] = Unblocking; 8172702Sktlim@umich.edu 8182292SN/A unblock(tid); 8192292SN/A 8202702Sktlim@umich.edu return; 8212702Sktlim@umich.edu } 8222292SN/A 8232292SN/A if (dispatchStatus[tid] == Squashing) { 8242292SN/A // Switch status to running if rename isn't being told to block or 8252292SN/A // squash this cycle. 8262292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8272292SN/A tid); 8282292SN/A 8292292SN/A dispatchStatus[tid] = Running; 8302292SN/A 8312292SN/A return; 8322292SN/A } 8332292SN/A} 8342292SN/A 8352292SN/Atemplate <class Impl> 8362292SN/Avoid 8372292SN/ADefaultIEW<Impl>::sortInsts() 8382292SN/A{ 8392292SN/A int insts_from_rename = fromRename->size; 8402292SN/A#ifdef DEBUG 8412292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8422292SN/A assert(insts[tid].empty()); 8432292SN/A#endif 8442292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8452292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8462292SN/A } 8472292SN/A} 8482292SN/A 8492292SN/Atemplate <class Impl> 8502292SN/Avoid 8512292SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8522292SN/A{ 8532292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8542292SN/A 8552292SN/A while (!insts[tid].empty()) { 8562292SN/A 8572292SN/A if (insts[tid].front()->isLoad()) { 8582292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 8592292SN/A } 8602292SN/A if (insts[tid].front()->isStore()) { 8612326SN/A toRename->iewInfo[tid].dispatchedToSQ++; 8626221Snate@binkert.org } 8636221Snate@binkert.org 8642326SN/A toRename->iewInfo[tid].dispatched++; 8652292SN/A 8662292SN/A insts[tid].pop(); 8672292SN/A } 8682292SN/A} 8692292SN/A 8702292SN/Atemplate <class Impl> 8712292SN/Avoid 8726221Snate@binkert.orgDefaultIEW<Impl>::wakeCPU() 8732702Sktlim@umich.edu{ 8744632Sgblack@eecs.umich.edu cpu->wakeCPU(); 8752935Sksewell@umich.edu} 8762702Sktlim@umich.edu 8772935Sksewell@umich.edutemplate <class Impl> 8782702Sktlim@umich.eduvoid 8792702Sktlim@umich.eduDefaultIEW<Impl>::activityThisCycle() 8802702Sktlim@umich.edu{ 8812702Sktlim@umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 8822702Sktlim@umich.edu cpu->activityThisCycle(); 8832702Sktlim@umich.edu} 8842702Sktlim@umich.edu 8852702Sktlim@umich.edutemplate <class Impl> 8862702Sktlim@umich.eduinline void 8872702Sktlim@umich.eduDefaultIEW<Impl>::activateStage() 8882702Sktlim@umich.edu{ 8892702Sktlim@umich.edu DPRINTF(Activity, "Activating stage.\n"); 8902702Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8912292SN/A} 8922292SN/A 8932292SN/Atemplate <class Impl> 8942292SN/Ainline void 8952292SN/ADefaultIEW<Impl>::deactivateStage() 8962292SN/A{ 8972292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8982292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 8992292SN/A} 9002292SN/A 9012292SN/Atemplate<class Impl> 9022292SN/Avoid 9032292SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9042292SN/A{ 9052292SN/A // If status is Running or idle, 9062292SN/A // call dispatchInsts() 9072292SN/A // If status is Unblocking, 9082292SN/A // buffer any instructions coming from rename 9092733Sktlim@umich.edu // continue trying to empty skid buffer 9102292SN/A // check if stall conditions have passed 9112292SN/A 9122292SN/A if (dispatchStatus[tid] == Blocked) { 9132292SN/A ++iewBlockCycles; 9142292SN/A 9152292SN/A } else if (dispatchStatus[tid] == Squashing) { 9162292SN/A ++iewSquashCycles; 9172733Sktlim@umich.edu } 9182292SN/A 9192292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9202292SN/A // will allow, as long as it is not currently blocked. 9212292SN/A if (dispatchStatus[tid] == Running || 9226221Snate@binkert.org dispatchStatus[tid] == Idle) { 9232292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9242292SN/A "dispatch.\n", tid); 9252292SN/A 9262292SN/A dispatchInsts(tid); 9272292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9282292SN/A // Make sure that the skid buffer has something in it if the 9292292SN/A // status is unblocking. 9302292SN/A assert(!skidsEmpty()); 9312292SN/A 9322292SN/A // If the status was unblocking, then instructions from the skid 9332292SN/A // buffer were used. Remove those instructions and handle 9342292SN/A // the rest of unblocking. 9352292SN/A dispatchInsts(tid); 9362292SN/A 9372292SN/A ++iewUnblockCycles; 9382292SN/A 9392292SN/A if (validInstsFromRename()) { 9402292SN/A // Add the current inputs to the skid buffer so they can be 9412292SN/A // reprocessed when this stage unblocks. 9422292SN/A skidInsert(tid); 9432292SN/A } 9442292SN/A 9452292SN/A unblock(tid); 9462292SN/A } 9472292SN/A} 9482292SN/A 9492292SN/Atemplate <class Impl> 9502292SN/Avoid 9512292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9522292SN/A{ 9532292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9542292SN/A // otherwise. 9552292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9562292SN/A dispatchStatus[tid] == Unblocking ? 9572292SN/A skidBuffer[tid] : insts[tid]; 9585215Sgblack@eecs.umich.edu 9592292SN/A int insts_to_add = insts_to_dispatch.size(); 9602292SN/A 9612292SN/A DynInstPtr inst; 9622292SN/A bool add_to_iq = false; 9632292SN/A int dis_num_inst = 0; 9642292SN/A 9652292SN/A // Loop through the instructions, putting them in the instruction 9662292SN/A // queue. 9672292SN/A for ( ; dis_num_inst < insts_to_add && 9682292SN/A dis_num_inst < dispatchWidth; 9692292SN/A ++dis_num_inst) 9706221Snate@binkert.org { 9712292SN/A inst = insts_to_dispatch.front(); 9722292SN/A 9732292SN/A if (dispatchStatus[tid] == Unblocking) { 9742292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9752292SN/A "buffer\n", tid); 9762292SN/A } 9772292SN/A 9782292SN/A // Make sure there's a valid instruction there. 9792292SN/A assert(inst); 9802292SN/A 9812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9822292SN/A "IQ.\n", 9832292SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9842292SN/A 9852292SN/A // Be sure to mark these instructions as ready so that the 9862292SN/A // commit stage can go ahead and execute them, and mark 9872820Sktlim@umich.edu // them as issued so the IQ doesn't reprocess them. 9882292SN/A 9892292SN/A // Check for squashed instructions. 9902292SN/A if (inst->isSquashed()) { 9912292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9922292SN/A "not adding to IQ.\n", tid); 9932292SN/A 9942292SN/A ++iewDispSquashedInsts; 9952292SN/A 9962292SN/A insts_to_dispatch.pop(); 9972292SN/A 9982292SN/A //Tell Rename That An Instruction has been processed 9992292SN/A if (inst->isLoad()) { 10007720Sgblack@eecs.umich.edu toRename->iewInfo[tid].dispatchedToLQ++; 10012292SN/A } 10027720Sgblack@eecs.umich.edu if (inst->isStore()) { 10032292SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10042292SN/A } 10052292SN/A 10062292SN/A toRename->iewInfo[tid].dispatched++; 10072292SN/A 10082292SN/A continue; 10092292SN/A } 10102292SN/A 10112292SN/A // Check for full conditions. 10122292SN/A if (instQueue.isFull(tid)) { 10132292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10142292SN/A 10152292SN/A // Call function to start blocking. 10162292SN/A block(tid); 10172292SN/A 10182292SN/A // Set unblock to false. Special case where we are using 10192292SN/A // skidbuffer (unblocking) instructions but then we still 10202292SN/A // get full in the IQ. 10212292SN/A toRename->iewUnblock[tid] = false; 10222292SN/A 10232292SN/A ++iewIQFullEvents; 10242292SN/A break; 10252292SN/A } 10262292SN/A 10272292SN/A // Check LSQ if inst is LD/ST 10282292SN/A if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 10292292SN/A (inst->isStore() && ldstQueue.sqFull(tid))) { 10302292SN/A DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 10312292SN/A inst->isLoad() ? "LQ" : "SQ"); 10322292SN/A 10332292SN/A // Call function to start blocking. 10342292SN/A block(tid); 10352292SN/A 10362292SN/A // Set unblock to false. Special case where we are using 10372292SN/A // skidbuffer (unblocking) instructions but then we still 10382292SN/A // get full in the IQ. 10392292SN/A toRename->iewUnblock[tid] = false; 10402292SN/A 10412292SN/A ++iewLSQFullEvents; 10422292SN/A break; 10432292SN/A } 10442292SN/A 10452292SN/A // Otherwise issue the instruction just fine. 10462292SN/A if (inst->isLoad()) { 10472292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10482292SN/A "encountered, adding to LSQ.\n", tid); 10492292SN/A 10502292SN/A // Reserve a spot in the load store queue for this 10512292SN/A // memory access. 10522292SN/A ldstQueue.insertLoad(inst); 10532292SN/A 10542292SN/A ++iewDispLoadInsts; 10552292SN/A 10562292SN/A add_to_iq = true; 10572292SN/A 10582292SN/A toRename->iewInfo[tid].dispatchedToLQ++; 10592292SN/A } else if (inst->isStore()) { 10602292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10612292SN/A "encountered, adding to LSQ.\n", tid); 10622292SN/A 10632292SN/A ldstQueue.insertStore(inst); 10642292SN/A 10652292SN/A ++iewDispStoreInsts; 10662292SN/A 10672292SN/A if (inst->isStoreConditional()) { 10682292SN/A // Store conditionals need to be set as "canCommit()" 10692292SN/A // so that commit can process them when they reach the 10702292SN/A // head of commit. 10712292SN/A // @todo: This is somewhat specific to Alpha. 10722292SN/A inst->setCanCommit(); 10732292SN/A instQueue.insertNonSpec(inst); 10742292SN/A add_to_iq = false; 10752292SN/A 10762292SN/A ++iewDispNonSpecInsts; 10772336SN/A } else { 10782336SN/A add_to_iq = true; 10792336SN/A } 10802336SN/A 10812348SN/A toRename->iewInfo[tid].dispatchedToSQ++; 10822292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10832292SN/A // Same as non-speculative stores. 10842292SN/A inst->setCanCommit(); 10852292SN/A instQueue.insertBarrier(inst); 10862292SN/A add_to_iq = false; 10872292SN/A } else if (inst->isNop()) { 10882292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10892292SN/A "skipping.\n", tid); 10902292SN/A 10912292SN/A inst->setIssued(); 10922292SN/A inst->setExecuted(); 10932326SN/A inst->setCanCommit(); 10942292SN/A 10952292SN/A instQueue.recordProducer(inst); 10962292SN/A 10972292SN/A iewExecutedNop[tid]++; 10982292SN/A 10992292SN/A add_to_iq = false; 11002292SN/A } else { 11012292SN/A assert(!inst->isExecuted()); 11022292SN/A add_to_iq = true; 11032292SN/A } 11042292SN/A 11052326SN/A if (add_to_iq && inst->isNonSpeculative()) { 11062292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11072727Sktlim@umich.edu "encountered, skipping.\n", tid); 11082301SN/A 11092292SN/A // Same as non-speculative stores. 11102292SN/A inst->setCanCommit(); 11112292SN/A 11122292SN/A // Specifically insert it as nonspeculative. 11132292SN/A instQueue.insertNonSpec(inst); 11142292SN/A 11152292SN/A ++iewDispNonSpecInsts; 11162292SN/A 11172292SN/A add_to_iq = false; 11182326SN/A } 11192292SN/A 11202292SN/A // If the instruction queue is not full, then add the 11212292SN/A // instruction. 11222292SN/A if (add_to_iq) { 11232292SN/A instQueue.insert(inst); 11244033Sktlim@umich.edu } 11254033Sktlim@umich.edu 11264033Sktlim@umich.edu insts_to_dispatch.pop(); 11274033Sktlim@umich.edu 11284033Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 11294033Sktlim@umich.edu 11304033Sktlim@umich.edu ++iewDispatchedInsts; 11314033Sktlim@umich.edu 11324033Sktlim@umich.edu#if TRACING_ON 11334033Sktlim@umich.edu inst->dispatchTick = curTick() - inst->fetchTick; 11344033Sktlim@umich.edu#endif 11354033Sktlim@umich.edu ppDispatch->notify(inst); 11364033Sktlim@umich.edu } 11374033Sktlim@umich.edu 11382292SN/A if (!insts_to_dispatch.empty()) { 11392292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11402292SN/A block(tid); 11412292SN/A toRename->iewUnblock[tid] = false; 11422292SN/A } 11432292SN/A 11442292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11452292SN/A dispatchStatus[tid] = Running; 11462292SN/A 11472292SN/A updatedQueues = true; 11482292SN/A } 11492292SN/A 11508471SGiacomo.Gabrielli@arm.com dis_num_inst = 0; 11518471SGiacomo.Gabrielli@arm.com} 11528471SGiacomo.Gabrielli@arm.com 11538471SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11542292SN/Avoid 11552292SN/ADefaultIEW<Impl>::printAvailableInsts() 11562292SN/A{ 11572935Sksewell@umich.edu int inst = 0; 11582292SN/A 11592292SN/A std::cout << "Available Instructions: "; 11602292SN/A 11612292SN/A while (fromIssue->insts[inst]) { 11622292SN/A 11632292SN/A if (inst%3==0) std::cout << "\n\t"; 11642292SN/A 11652292SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11662292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11672292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11682292SN/A 11692292SN/A inst++; 11702292SN/A 11712292SN/A } 11722292SN/A 11732292SN/A std::cout << "\n"; 11742292SN/A} 11752292SN/A 11762292SN/Atemplate <class Impl> 11772980Sgblack@eecs.umich.eduvoid 11782292SN/ADefaultIEW<Impl>::executeInsts() 11792292SN/A{ 11802292SN/A wbNumInst = 0; 11812980Sgblack@eecs.umich.edu wbCycle = 0; 11822292SN/A 11837720Sgblack@eecs.umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 11842292SN/A list<ThreadID>::iterator end = activeThreads->end(); 11852292SN/A 11862292SN/A while (threads != end) { 11872292SN/A ThreadID tid = *threads++; 11882292SN/A fetchRedirect[tid] = false; 11892292SN/A } 11902292SN/A 11912980Sgblack@eecs.umich.edu // Uncomment this if you want to see all available instructions. 11922292SN/A // @todo This doesn't actually work anymore, we should fix it. 11932292SN/A// printAvailableInsts(); 11942292SN/A 11952292SN/A // Execute/writeback any instructions that are available. 11962292SN/A int insts_to_execute = fromIssue->size; 11972292SN/A int inst_num = 0; 11982292SN/A for (; inst_num < insts_to_execute; 11992292SN/A ++inst_num) { 12002292SN/A 12016221Snate@binkert.org DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12026221Snate@binkert.org 12032292SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12043867Sbinkertn@umich.edu 12056221Snate@binkert.org DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12062292SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12072292SN/A 12082292SN/A // Notify potential listeners that this instruction has started 12092698Sktlim@umich.edu // executing 12107599Sminkyu.jeong@arm.com ppExecute->notify(inst); 12112698Sktlim@umich.edu 12121062SN/A // Check if the instruction is squashed; if so then skip it 12131062SN/A if (inst->isSquashed()) { 12142333SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12152292SN/A " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12162333SN/A inst->seqNum); 12172326SN/A 12181062SN/A // Consider this instruction executed so that commit can go 12192292SN/A // ahead and retire the instruction. 12201062SN/A inst->setExecuted(); 12212333SN/A 12221062SN/A // Not sure if I should set this here or just let commit try to 12237720Sgblack@eecs.umich.edu // commit any squashed instructions. I like the latter a bit more. 12247720Sgblack@eecs.umich.edu inst->setCanCommit(); 12251062SN/A 12261062SN/A ++iewExecSquashedInsts; 12271062SN/A 12288315Sgeoffrey.blake@arm.com continue; 12298315Sgeoffrey.blake@arm.com } 12308315Sgeoffrey.blake@arm.com 12311062SN/A Fault fault = NoFault; 12321062SN/A 12331062SN/A // Execute instruction. 12341062SN/A // Note that if the instruction faults, it will be handled 12351062SN/A // at the commit stage. 12362292SN/A if (inst->isMemRef()) { 12372292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12382292SN/A "reference.\n"); 12391062SN/A 12401062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12411062SN/A if (inst->isLoad()) { 12422820Sktlim@umich.edu // Loads will mark themselves as executed, and their writeback 12431062SN/A // event adds the instruction to the queue to commit 12441062SN/A fault = ldstQueue.executeLoad(inst); 12451062SN/A 12462292SN/A if (inst->isTranslationDelayed() && 12471062SN/A fault == NoFault) { 12481062SN/A // A hw page table walk is currently going on; the 12491062SN/A // instruction must be deferred. 12501062SN/A DPRINTF(IEW, "Execute: Delayed translation, deferring " 12517850SMatt.Horsnell@arm.com "load.\n"); 12522292SN/A instQueue.deferMemInst(inst); 12531062SN/A continue; 12541062SN/A } 12551062SN/A 12561062SN/A if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12572292SN/A inst->fault = NoFault; 12582292SN/A } 12592292SN/A } else if (inst->isStore()) { 12607944SGiacomo.Gabrielli@arm.com fault = ldstQueue.executeStore(inst); 12617944SGiacomo.Gabrielli@arm.com 12627944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12637944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12647944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12657944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12667944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12677944SGiacomo.Gabrielli@arm.com "store.\n"); 12687944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12697944SGiacomo.Gabrielli@arm.com continue; 12707944SGiacomo.Gabrielli@arm.com } 12717850SMatt.Horsnell@arm.com 12728073SAli.Saidi@ARM.com // If the store had a fault then it may not have a mem req 12737850SMatt.Horsnell@arm.com if (fault != NoFault || !inst->readPredicate() || 12741062SN/A !inst->isStoreConditional()) { 12752367SN/A // If the instruction faulted, then we need to send it along 12761062SN/A // to commit without the instruction completing. 12777944SGiacomo.Gabrielli@arm.com // Send this instruction to commit, also make sure iew stage 12787944SGiacomo.Gabrielli@arm.com // realizes there is activity. 12797944SGiacomo.Gabrielli@arm.com inst->setExecuted(); 12807944SGiacomo.Gabrielli@arm.com instToCommit(inst); 12817944SGiacomo.Gabrielli@arm.com activityThisCycle(); 12827944SGiacomo.Gabrielli@arm.com } 12837944SGiacomo.Gabrielli@arm.com 12847944SGiacomo.Gabrielli@arm.com // Store conditionals will mark themselves as 12857944SGiacomo.Gabrielli@arm.com // executed, and their writeback event will add the 12867944SGiacomo.Gabrielli@arm.com // instruction to the queue to commit. 12872292SN/A } else { 12887782Sminkyu.jeong@arm.com panic("Unexpected memory type!\n"); 12897782Sminkyu.jeong@arm.com } 12907782Sminkyu.jeong@arm.com 12917782Sminkyu.jeong@arm.com } else { 12922367SN/A // If the instruction has already faulted, then skip executing it. 12932367SN/A // Such case can happen when it faulted during ITLB translation. 12942367SN/A // If we execute the instruction (even if it's a nop) the fault 12952367SN/A // will be replaced and we will lose it. 12962367SN/A if (inst->getFault() == NoFault) { 12972292SN/A inst->execute(); 12982326SN/A if (!inst->readPredicate()) 12992326SN/A inst->forwardOldRegs(); 13002326SN/A } 13012326SN/A 13021062SN/A inst->setExecuted(); 13032292SN/A 13041062SN/A instToCommit(inst); 13051062SN/A } 13061062SN/A 13077847Sminkyu.jeong@arm.com updateExeInstStats(inst); 13087847Sminkyu.jeong@arm.com 13097847Sminkyu.jeong@arm.com // Check if branch prediction was correct, if not then we need 13107847Sminkyu.jeong@arm.com // to tell commit to squash in flight instructions. Only 13117847Sminkyu.jeong@arm.com // handle this if there hasn't already been something that 13127847Sminkyu.jeong@arm.com // redirects fetch in this group of instructions. 13137848SAli.Saidi@ARM.com 13147848SAli.Saidi@ARM.com // This probably needs to prioritize the redirects if a different 13157847Sminkyu.jeong@arm.com // scheduler is used. Currently the scheduler schedules the oldest 13161062SN/A // instruction first, so the branch resolution order will be correct. 13172292SN/A ThreadID tid = inst->threadNumber; 13182292SN/A 13192292SN/A if (!fetchRedirect[tid] || 13201062SN/A !toCommit->squash[tid] || 13211062SN/A toCommit->squashedSeqNum[tid] > inst->seqNum) { 13222301SN/A 13231681SN/A // Prevent testing for misprediction on load instructions, 13242326SN/A // that have not been executed. 13252326SN/A bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13262326SN/A 13272107SN/A if (inst->mispredicted() && !loadNotExecuted) { 13281681SN/A fetchRedirect[tid] = true; 13292292SN/A 13302292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13312292SN/A DPRINTF(IEW, "Predicted target was PC: %s.\n", 13326221Snate@binkert.org inst->readPredTarg()); 13331062SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13343732Sktlim@umich.edu inst->pcState()); 13357852SMatt.Horsnell@arm.com // If incorrect, then signal the ROB that it must be squashed. 13363732Sktlim@umich.edu squashDueToBranch(inst, tid); 13371062SN/A 13387856SMatt.Horsnell@arm.com ppMispredict->notify(inst); 13397856SMatt.Horsnell@arm.com 13407856SMatt.Horsnell@arm.com if (inst->readPredTaken()) { 13417856SMatt.Horsnell@arm.com predictedTakenIncorrect++; 13427856SMatt.Horsnell@arm.com } else { 13432292SN/A predictedNotTakenIncorrect++; 13441062SN/A } 13452292SN/A } else if (ldstQueue.violation(tid)) { 13466036Sksewell@umich.edu assert(inst->isMemRef()); 13477720Sgblack@eecs.umich.edu // If there was an ordering violation, then get the 13487720Sgblack@eecs.umich.edu // DynInst that caused the violation. Note that this 13497720Sgblack@eecs.umich.edu // clears the violation signal. 13501062SN/A DynInstPtr violator; 13512292SN/A violator = ldstQueue.getMemDepViolator(tid); 13521062SN/A 13533795Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13541062SN/A "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13552292SN/A violator->pcState(), violator->seqNum, 13562292SN/A inst->pcState(), inst->seqNum, inst->physEffAddrLow); 13571062SN/A 13582292SN/A fetchRedirect[tid] = true; 13594033Sktlim@umich.edu 13602326SN/A // Tell the instruction queue that a violation has occured. 13612326SN/A instQueue.violation(inst, violator); 13622292SN/A 13632292SN/A // Squash. 13642292SN/A squashDueToMemOrder(violator, tid); 13651062SN/A 13667720Sgblack@eecs.umich.edu ++memOrderViolationEvents; 13677720Sgblack@eecs.umich.edu } 13687720Sgblack@eecs.umich.edu } else { 13697720Sgblack@eecs.umich.edu // Reset any state associated with redirects that will not 13707720Sgblack@eecs.umich.edu // be used. 13713732Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13723732Sktlim@umich.edu assert(inst->isMemRef()); 13731062SN/A 13741062SN/A DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13751062SN/A 13761062SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13772292SN/A "%s, inst PC: %s. Addr is: %#x.\n", 13781062SN/A violator->pcState(), inst->pcState(), 13791062SN/A inst->physEffAddrLow); 13802292SN/A DPRINTF(IEW, "Violation will not be handled because " 13812292SN/A "already squashing\n"); 13822292SN/A 13832292SN/A ++memOrderViolationEvents; 13842292SN/A } 13857720Sgblack@eecs.umich.edu } 13867720Sgblack@eecs.umich.edu } 13872292SN/A 13882292SN/A // Update and record activity if we processed any instructions. 13891062SN/A if (inst_num) { 13904033Sktlim@umich.edu if (exeStatus == Idle) { 13914033Sktlim@umich.edu exeStatus = Running; 13924033Sktlim@umich.edu } 13934033Sktlim@umich.edu 13944033Sktlim@umich.edu updatedQueues = true; 13954033Sktlim@umich.edu 13964033Sktlim@umich.edu cpu->activityThisCycle(); 13974033Sktlim@umich.edu } 13984033Sktlim@umich.edu 13997720Sgblack@eecs.umich.edu // Need to reset this in case a writeback event needs to write into the 14007720Sgblack@eecs.umich.edu // iew queue. That way the writeback event will write into the correct 14017720Sgblack@eecs.umich.edu // spot in the queue. 14024033Sktlim@umich.edu wbNumInst = 0; 14034033Sktlim@umich.edu 14044033Sktlim@umich.edu} 14054033Sktlim@umich.edu 14064033Sktlim@umich.edutemplate <class Impl> 14074033Sktlim@umich.eduvoid 14084033Sktlim@umich.eduDefaultIEW<Impl>::writebackInsts() 14094033Sktlim@umich.edu{ 14107720Sgblack@eecs.umich.edu // Loop through the head of the time buffer and wake any 14117720Sgblack@eecs.umich.edu // dependents. These instructions are about to write back. Also 14124033Sktlim@umich.edu // mark scoreboard that this instruction is finally complete. 14134033Sktlim@umich.edu // Either have IEW have direct access to scoreboard, or have this 14144033Sktlim@umich.edu // as part of backwards communication. 14154033Sktlim@umich.edu for (int inst_num = 0; inst_num < wbWidth && 14164033Sktlim@umich.edu toCommit->insts[inst_num]; inst_num++) { 14174033Sktlim@umich.edu DynInstPtr inst = toCommit->insts[inst_num]; 14181062SN/A ThreadID tid = inst->threadNumber; 14191062SN/A 14202292SN/A DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14212348SN/A inst->seqNum, inst->pcState()); 14222292SN/A 14232292SN/A iewInstsToCommit[tid]++; 14242292SN/A // Notify potential listeners that execution is complete for this 14252292SN/A // instruction. 14262292SN/A ppToCommit->notify(inst); 14272292SN/A 14282292SN/A // Some instructions will be sent to commit without having 14292292SN/A // executed because they need commit to handle them. 14302292SN/A // E.g. Strictly ordered loads have not actually executed when they 14312292SN/A // are first sent to commit. Instead commit must tell the LSQ 14322292SN/A // when it's ready to execute the strictly ordered load. 14332292SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14342292SN/A int dependents = instQueue.wakeDependents(inst); 14352292SN/A 14367852SMatt.Horsnell@arm.com for (int i = 0; i < inst->numDestRegs(); i++) { 14372107SN/A //mark as Ready 14382107SN/A DPRINTF(IEW,"Setting Destination Register %i (%s)\n", 14392292SN/A inst->renamedDestRegIdx(i)->index(), 14402107SN/A inst->renamedDestRegIdx(i)->className()); 14412292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14422107SN/A } 14432326SN/A 14442326SN/A if (dependents) { 14452326SN/A producerInst[tid]++; 14462326SN/A consumerInst[tid]+= dependents; 14472326SN/A } 14483958Sgblack@eecs.umich.edu writebackCount[tid]++; 14492292SN/A } 14502107SN/A } 14516221Snate@binkert.org} 14522107SN/A 14537720Sgblack@eecs.umich.edutemplate<class Impl> 14547720Sgblack@eecs.umich.eduvoid 14552107SN/ADefaultIEW<Impl>::tick() 14562301SN/A{ 14572301SN/A wbNumInst = 0; 14582292SN/A wbCycle = 0; 14592292SN/A 14602292SN/A wroteToTimeBuffer = false; 14612292SN/A updatedQueues = false; 14622292SN/A 14632367SN/A sortInsts(); 14642301SN/A 14652107SN/A // Free function units marked as being freed this cycle. 14662292SN/A fuPool->processFreeUnits(); 14672292SN/A 14682292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 14692292SN/A list<ThreadID>::iterator end = activeThreads->end(); 14702292SN/A 14712107SN/A // Check stall and squash signals, dispatch any instructions. 14722301SN/A while (threads != end) { 14732348SN/A ThreadID tid = *threads++; 14742348SN/A 14752348SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14762348SN/A 14772326SN/A checkSignalsAndUpdate(tid); 14782107SN/A dispatch(tid); 14792820Sktlim@umich.edu } 14802820Sktlim@umich.edu 14812107SN/A if (exeStatus != Squashing) { 14821060SN/A executeInsts(); 14831060SN/A 14841681SN/A writebackInsts(); 14851060SN/A 14862292SN/A // Have the instruction queue try to schedule any ready instructions. 14871060SN/A // (In actuality, this scheduling is for instructions that will 14882292SN/A // be executed next cycle.) 14892292SN/A instQueue.scheduleReadyInsts(); 14901060SN/A 14912292SN/A // Also should advance its own time buffers if the stage ran. 14922292SN/A // Not the best place for it, but this works (hopefully). 14931060SN/A issueToExecQueue.advance(); 14942292SN/A } 14951060SN/A 14962326SN/A bool broadcast_free_entries = false; 14972326SN/A 14981062SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14996221Snate@binkert.org exeStatus = Idle; 15006221Snate@binkert.org updateLSQNextCycle = false; 15011060SN/A 15022326SN/A broadcast_free_entries = true; 15033867Sbinkertn@umich.edu } 15046221Snate@binkert.org 15051060SN/A // Writeback any stores using any leftover bandwidth. 15062292SN/A ldstQueue.writebackStores(); 15071060SN/A 15082292SN/A // Check the committed load/store signals to see if there's a load 15092292SN/A // or store to commit. Also check if it's being told to execute a 15101060SN/A // nonspeculative instruction. 15111060SN/A // This is pretty inefficient... 15122292SN/A 15132292SN/A threads = activeThreads->begin(); 15141060SN/A while (threads != end) { 15152292SN/A ThreadID tid = (*threads++); 15162292SN/A 15172292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15182292SN/A 15192292SN/A // Update structures based on instructions committed. 15202292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15212292SN/A !fromCommit->commitInfo[tid].squash && 15222292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15232292SN/A 15242292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15252292SN/A 15262292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15272292SN/A 15282292SN/A updateLSQNextCycle = true; 15292292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15302292SN/A } 15312292SN/A 15322292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15332292SN/A 15342292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15352292SN/A if (fromCommit->commitInfo[tid].strictlyOrdered) { 15362292SN/A instQueue.replayMemInst( 15371681SN/A fromCommit->commitInfo[tid].strictlyOrderedLoad); 15381681SN/A fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); 15391061SN/A } else { 15401061SN/A instQueue.scheduleNonSpec( 15411061SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15421681SN/A } 15432292SN/A } 15443867Sbinkertn@umich.edu 15453867Sbinkertn@umich.edu if (broadcast_free_entries) { 15466221Snate@binkert.org toFetch->iewInfo[tid].iqCount = 15472292SN/A instQueue.getCount(tid); 15482292SN/A toFetch->iewInfo[tid].ldstqCount = 15492292SN/A ldstQueue.getCount(tid); 15502348SN/A 15512292SN/A toRename->iewInfo[tid].usedIQ = true; 15522292SN/A toRename->iewInfo[tid].freeIQEntries = 15532292SN/A instQueue.numFreeEntries(tid); 15542292SN/A toRename->iewInfo[tid].usedLSQ = true; 15552292SN/A 15562292SN/A toRename->iewInfo[tid].freeLQEntries = 15572292SN/A ldstQueue.numFreeLoadEntries(tid); 15582292SN/A toRename->iewInfo[tid].freeSQEntries = 15592292SN/A ldstQueue.numFreeStoreEntries(tid); 15602292SN/A 15612292SN/A wroteToTimeBuffer = true; 15622292SN/A } 15632292SN/A 15642292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15652292SN/A tid, toRename->iewInfo[tid].dispatched); 15662292SN/A } 15672292SN/A 15684033Sktlim@umich.edu DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15692292SN/A "LQ has %i free entries. SQ has %i free entries.\n", 15702292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15712292SN/A ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 15722292SN/A 15732292SN/A updateStatus(); 15742292SN/A 15752292SN/A if (wroteToTimeBuffer) { 15762292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15772292SN/A cpu->activityThisCycle(); 15782292SN/A } 15792292SN/A} 15802292SN/A 15812292SN/Atemplate <class Impl> 15822292SN/Avoid 15832292SN/ADefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst) 15842292SN/A{ 15852292SN/A ThreadID tid = inst->threadNumber; 15862292SN/A 15872292SN/A iewExecutedInsts++; 15882292SN/A 15892292SN/A#if TRACING_ON 15902292SN/A if (DTRACE(O3PipeView)) { 15912292SN/A inst->completeTick = curTick() - inst->fetchTick; 15922292SN/A } 15931061SN/A#endif 15941061SN/A 15952292SN/A // 15962292SN/A // Control operations 15972292SN/A // 15982292SN/A if (inst->isControl()) 15992292SN/A iewExecutedBranches[tid]++; 16002292SN/A 16012292SN/A // 16022292SN/A // Memory operations 16032292SN/A // 16042292SN/A if (inst->isMemRef()) { 16051061SN/A iewExecutedRefs[tid]++; 16061060SN/A 16071060SN/A if (inst->isLoad()) { 16082301SN/A iewExecLoadInsts[tid]++; 16091060SN/A } 16102301SN/A } 16111060SN/A} 16126221Snate@binkert.org 16131060SN/Atemplate <class Impl> 16142301SN/Avoid 16152301SN/ADefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst) 16162301SN/A{ 16172301SN/A ThreadID tid = inst->threadNumber; 16182301SN/A 16196221Snate@binkert.org if (!fetchRedirect[tid] || 16202301SN/A !toCommit->squash[tid] || 16212727Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 16222301SN/A 16232669Sktlim@umich.edu if (inst->mispredicted()) { 16242301SN/A fetchRedirect[tid] = true; 16251060SN/A 16268471SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16278471SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16288471SGiacomo.Gabrielli@arm.com inst->predInstAddr(), inst->predNextInstAddr()); 16298471SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16302301SN/A " NPC: %#x.\n", inst->nextInstAddr(), 16312301SN/A inst->nextInstAddr()); 16322301SN/A // If incorrect, then signal the ROB that it must be squashed. 16332301SN/A squashDueToBranch(inst, tid); 16346221Snate@binkert.org 16351060SN/A if (inst->readPredTaken()) { 16362301SN/A predictedTakenIncorrect++; 16372301SN/A } else { 16382301SN/A predictedNotTakenIncorrect++; 16392301SN/A } 16406221Snate@binkert.org } 16411060SN/A } 16422301SN/A} 16436221Snate@binkert.org 16441060SN/A#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 16451060SN/A