iew_impl.hh revision 1060
11689SN/A// @todo: Fix the instantaneous communication among all the stages within 210715SRekai.GonzalezAlberquilla@arm.com// iew. There's a clear delay between issue and execute, yet backwards 39913Ssteve.reinhardt@amd.com// communication happens simultaneously. Might not be that bad really... 47854SAli.Saidi@ARM.com// it might skew stats a bit though. Issue would otherwise try to issue 57854SAli.Saidi@ARM.com// instructions that would never be executed if there were a delay; without 67854SAli.Saidi@ARM.com// it issue will simply squash. Make this stage block properly. Make this 77854SAli.Saidi@ARM.com// stage delay after a squash properly. Update the statuses for each stage. 87854SAli.Saidi@ARM.com// Actually read instructions out of the skid buffer. 97854SAli.Saidi@ARM.com 107854SAli.Saidi@ARM.com#include <queue> 117854SAli.Saidi@ARM.com 127854SAli.Saidi@ARM.com#include "base/timebuf.hh" 137854SAli.Saidi@ARM.com#include "cpu/beta_cpu/iew.hh" 147854SAli.Saidi@ARM.com 152329SN/Atemplate<class Impl, class IQ> 161689SN/ASimpleIEW<Impl, IQ>::SimpleIEW(Params ¶ms) 171689SN/A : // Just make this time buffer really big for now 181689SN/A issueToExecQueue(20, 20), 191689SN/A instQueue(params), 201689SN/A commitToIEWDelay(params.commitToIEWDelay), 211689SN/A renameToIEWDelay(params.renameToIEWDelay), 221689SN/A issueToExecuteDelay(params.issueToExecuteDelay), 231689SN/A issueReadWidth(params.issueWidth), 241689SN/A issueWidth(params.issueWidth), 251689SN/A executeWidth(params.executeWidth) 261689SN/A{ 271689SN/A DPRINTF(IEW, "IEW: executeIntWidth: %i.\n", params.executeIntWidth); 281689SN/A _status = Idle; 291689SN/A _issueStatus = Idle; 301689SN/A _exeStatus = Idle; 311689SN/A _wbStatus = Idle; 321689SN/A 331689SN/A // Setup wire to read instructions coming from issue. 341689SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 351689SN/A 361689SN/A // Instruction queue needs the queue between issue and execute. 371689SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 381689SN/A} 391689SN/A 402665Ssaidi@eecs.umich.edutemplate<class Impl, class IQ> 412665Ssaidi@eecs.umich.eduvoid 422935Sksewell@umich.eduSimpleIEW<Impl, IQ>::setCPU(FullCPU *cpu_ptr) 431689SN/A{ 441689SN/A DPRINTF(IEW, "IEW: Setting CPU pointer.\n"); 459944Smatt.horsnell@ARM.com cpu = cpu_ptr; 469944Smatt.horsnell@ARM.com 479944Smatt.horsnell@ARM.com instQueue.setCPU(cpu_ptr); 481060SN/A} 491060SN/A 503773Sgblack@eecs.umich.edutemplate<class Impl, class IQ> 516329Sgblack@eecs.umich.eduvoid 526658Snate@binkert.orgSimpleIEW<Impl, IQ>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 531717SN/A{ 549913Ssteve.reinhardt@amd.com DPRINTF(IEW, "IEW: Setting time buffer pointer.\n"); 558232Snate@binkert.org timeBuffer = tb_ptr; 568232Snate@binkert.org 579527SMatt.Horsnell@arm.com // Setup wire to read information from time buffer, from commit. 585529Snate@binkert.org fromCommit = timeBuffer->getWire(-commitToIEWDelay); 591060SN/A 606221Snate@binkert.org // Setup wire to write information back to previous stages. 616221Snate@binkert.org toRename = timeBuffer->getWire(0); 621061SN/A 635529Snate@binkert.org // Instruction queue also needs main time buffer. 644329Sktlim@umich.edu instQueue.setTimeBuffer(tb_ptr); 654329Sktlim@umich.edu} 662292SN/A 672292SN/Atemplate<class Impl, class IQ> 682292SN/Avoid 692292SN/ASimpleIEW<Impl, IQ>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 705529Snate@binkert.org{ 719920Syasuko.eckert@amd.com DPRINTF(IEW, "IEW: Setting rename queue pointer.\n"); 7210935Snilay@cs.wisc.edu renameQueue = rq_ptr; 731060SN/A 7410172Sdam.sunwoo@arm.com // Setup wire to read information from rename queue. 7510172Sdam.sunwoo@arm.com fromRename = renameQueue->getWire(-renameToIEWDelay); 7610172Sdam.sunwoo@arm.com} 7710172Sdam.sunwoo@arm.com 7810172Sdam.sunwoo@arm.comtemplate<class Impl, class IQ> 792292SN/Avoid 8010328Smitch.hayenga@arm.comSimpleIEW<Impl, IQ>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 812292SN/A{ 822292SN/A DPRINTF(IEW, "IEW: Setting IEW queue pointer.\n"); 832292SN/A iewQueue = iq_ptr; 842292SN/A 852292SN/A // Setup wire to write instructions to commit. 862292SN/A toCommit = iewQueue->getWire(0); 872292SN/A} 881060SN/A 891060SN/Atemplate<class Impl, class IQ> 901061SN/Avoid 911060SN/ASimpleIEW<Impl, IQ>::setRenameMap(RenameMap *rm_ptr) 922292SN/A{ 931062SN/A DPRINTF(IEW, "IEW: Setting rename map pointer.\n"); 941062SN/A renameMap = rm_ptr; 958240Snate@binkert.org} 961062SN/A 971062SN/Atemplate<class Impl, class IQ> 981062SN/Avoid 998240Snate@binkert.orgSimpleIEW<Impl, IQ>::wakeDependents(DynInst *inst) 1001062SN/A{ 1011062SN/A instQueue.wakeDependents(inst); 1021062SN/A} 1038240Snate@binkert.org 1041062SN/Atemplate<class Impl, class IQ> 1051062SN/Avoid 1062301SN/ASimpleIEW<Impl, IQ>::block() 1078240Snate@binkert.org{ 1082301SN/A DPRINTF(IEW, "IEW: Blocking.\n"); 1092301SN/A // Set the status to Blocked. 1102292SN/A _status = Blocked; 1118240Snate@binkert.org 1122292SN/A // Add the current inputs to the skid buffer so they can be 1132292SN/A // reprocessed when this stage unblocks. 1141062SN/A skidBuffer.push(*fromRename); 1158240Snate@binkert.org 1161062SN/A // Note that this stage only signals previous stages to stall when 1171062SN/A // it is the cause of the stall originates at this stage. Otherwise 1181062SN/A // the previous stages are expected to check all possible stall signals. 1198240Snate@binkert.org} 1201062SN/A 1211062SN/Atemplate<class Impl, class IQ> 1221062SN/Ainline void 1238240Snate@binkert.orgSimpleIEW<Impl, IQ>::unblock() 1241062SN/A{ 1251062SN/A // Check if there's information in the skid buffer. If there is, then 1261062SN/A // set status to unblocking, otherwise set it directly to running. 1278240Snate@binkert.org DPRINTF(IEW, "IEW: Reading instructions out of the skid " 1282292SN/A "buffer.\n"); 1291062SN/A // Remove the now processed instructions from the skid buffer. 1301062SN/A skidBuffer.pop(); 1318240Snate@binkert.org 1322292SN/A // If there's still information in the skid buffer, then 1331062SN/A // continue to tell previous stages to stall. They will be 13410239Sbinhpham@cs.rutgers.edu // able to restart once the skid buffer is empty. 13510239Sbinhpham@cs.rutgers.edu if (!skidBuffer.empty()) { 13610239Sbinhpham@cs.rutgers.edu toRename->iewInfo.stall = true; 13710239Sbinhpham@cs.rutgers.edu } else { 13810239Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "IEW: Stage is done unblocking.\n"); 13910239Sbinhpham@cs.rutgers.edu _status = Running; 14010239Sbinhpham@cs.rutgers.edu } 14110239Sbinhpham@cs.rutgers.edu} 1421062SN/A 1438240Snate@binkert.orgtemplate<class Impl, class IQ> 1441062SN/Avoid 1451062SN/ASimpleIEW<Impl, IQ>::squash() 1461062SN/A{ 1478240Snate@binkert.org DPRINTF(IEW, "IEW: Squashing all instructions.\n"); 1481062SN/A _status = Squashing; 1491062SN/A 1501062SN/A // Tell the IQ to start squashing. 1518240Snate@binkert.org instQueue.squash(); 1521062SN/A 1531062SN/A // Tell rename to squash through the time buffer. 1541062SN/A // This communication may be redundant depending upon where squash() 1558240Snate@binkert.org // is called. 1561062SN/A// toRename->iewInfo.squash = true; 1571062SN/A} 1581062SN/A 1598240Snate@binkert.orgtemplate<class Impl, class IQ> 1601062SN/Avoid 1611062SN/ASimpleIEW<Impl, IQ>::squash(DynInst *inst) 1622301SN/A{ 1638240Snate@binkert.org DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC:%#x.\n", 1642301SN/A inst->PC); 1652301SN/A // Perhaps leave the squashing up to the ROB stage to tell it when to 1662301SN/A // squash? 1672301SN/A _status = Squashing; 1688240Snate@binkert.org 1692301SN/A // Tell rename to squash through the time buffer. 1702301SN/A toRename->iewInfo.squash = true; 1712301SN/A // Also send PC update information back to prior stages. 1722307SN/A toRename->iewInfo.squashedSeqNum = inst->seqNum; 1738240Snate@binkert.org toRename->iewInfo.nextPC = inst->readCalcTarg(); 1742307SN/A toRename->iewInfo.predIncorrect = true; 1752307SN/A} 1762307SN/A 1777897Shestness@cs.utexas.edutemplate<class Impl, class IQ> 1788240Snate@binkert.orgvoid 1797897Shestness@cs.utexas.eduSimpleIEW<Impl, IQ>::tick() 1807897Shestness@cs.utexas.edu{ 1817897Shestness@cs.utexas.edu // Considering putting all the state-determining stuff in this section. 1828240Snate@binkert.org 1837897Shestness@cs.utexas.edu // Try to fill up issue queue with as many instructions as bandwidth 1847897Shestness@cs.utexas.edu // allows. 1851062SN/A // Decode should try to execute as many instructions as its bandwidth 1861062SN/A // will allow, as long as it is not currently blocked. 1871062SN/A 1881062SN/A // Check if the stage is in a running status. 18911246Sradhika.jagtap@ARM.com if (_status != Blocked && _status != Squashing) { 19011246Sradhika.jagtap@ARM.com DPRINTF(IEW, "IEW: Status is not blocked, attempting to run " 19111246Sradhika.jagtap@ARM.com "stage.\n"); 19211246Sradhika.jagtap@ARM.com iew(); 19311246Sradhika.jagtap@ARM.com 19411246Sradhika.jagtap@ARM.com // If it's currently unblocking, check to see if it should switch 19511246Sradhika.jagtap@ARM.com // to running. 19611246Sradhika.jagtap@ARM.com if (_status == Unblocking) { 19711246Sradhika.jagtap@ARM.com unblock(); 1982292SN/A } 1991060SN/A } else if (_status == Squashing) { 2001060SN/A 2011060SN/A DPRINTF(IEW, "IEW: Still squashing.\n"); 2021060SN/A 2031060SN/A // Check if stage should remain squashing. Stop squashing if the 2041060SN/A // squash signal clears. 2051060SN/A if (!fromCommit->commitInfo.squash && 2061060SN/A !fromCommit->commitInfo.robSquashing) { 2071060SN/A DPRINTF(IEW, "IEW: Done squashing, changing status to " 2081060SN/A "running.\n"); 2091060SN/A 2101060SN/A _status = Running; 2111060SN/A instQueue.stopSquash(); 2121061SN/A } else { 2131060SN/A instQueue.doSquash(); 2142292SN/A } 2151060SN/A 2161060SN/A // Also should advance its own time buffers if the stage ran. 2171060SN/A // Not sure about this... 2181060SN/A// issueToExecQueue.advance(); 2191060SN/A } else if (_status == Blocked) { 2201060SN/A // Continue to tell previous stage to stall. 2211060SN/A toRename->iewInfo.stall = true; 2221061SN/A 2231060SN/A // Check if possible stall conditions have cleared. 2242292SN/A if (!fromCommit->commitInfo.stall && 2251060SN/A !instQueue.isFull()) { 2261060SN/A DPRINTF(IEW, "IEW: Stall signals cleared, going to unblock.\n"); 2271060SN/A _status = Unblocking; 2281060SN/A } 2291060SN/A 2301060SN/A // If there's still instructions coming from rename, continue to 2311060SN/A // put them on the skid buffer. 2321061SN/A if (fromRename->insts[0] != NULL) { 2331060SN/A block(); 2349427SAndreas.Sandberg@ARM.com } 2351060SN/A 2369444SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo.squash || 2379444SAndreas.Sandberg@ARM.com fromCommit->commitInfo.robSquashing) { 2389444SAndreas.Sandberg@ARM.com squash(); 2399444SAndreas.Sandberg@ARM.com } 2409444SAndreas.Sandberg@ARM.com } 2419444SAndreas.Sandberg@ARM.com 2429444SAndreas.Sandberg@ARM.com // @todo: Maybe put these at the beginning, so if it's idle it can 2439444SAndreas.Sandberg@ARM.com // return early. 2449444SAndreas.Sandberg@ARM.com // Write back number of free IQ entries here. 2459444SAndreas.Sandberg@ARM.com toRename->iewInfo.freeIQEntries = instQueue.numFreeEntries(); 2469444SAndreas.Sandberg@ARM.com 2479444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "IEW: IQ has %i free entries.\n", 2482329SN/A instQueue.numFreeEntries()); 2496221Snate@binkert.org} 2509444SAndreas.Sandberg@ARM.com 2519444SAndreas.Sandberg@ARM.comtemplate<class Impl, class IQ> 2522292SN/Avoid 25310239Sbinhpham@cs.rutgers.eduSimpleIEW<Impl, IQ>::iew() 25410239Sbinhpham@cs.rutgers.edu{ 2552292SN/A // Might want to put all state checks in the tick() function. 2562292SN/A // Check if being told to stall from commit. 2579444SAndreas.Sandberg@ARM.com if (fromCommit->commitInfo.stall) { 2589444SAndreas.Sandberg@ARM.com block(); 2599444SAndreas.Sandberg@ARM.com return; 2609444SAndreas.Sandberg@ARM.com } else if (fromCommit->commitInfo.squash || 2619444SAndreas.Sandberg@ARM.com fromCommit->commitInfo.robSquashing) { 26210239Sbinhpham@cs.rutgers.edu // Also check if commit is telling this stage to squash. 26310239Sbinhpham@cs.rutgers.edu squash(); 2649444SAndreas.Sandberg@ARM.com return; 2659444SAndreas.Sandberg@ARM.com } 2662292SN/A 2671060SN/A //////////////////////////////////////// 2681060SN/A //ISSUE stage 2692292SN/A //////////////////////////////////////// 2702292SN/A 2716221Snate@binkert.org //Put into its own function? 2722292SN/A //Add instructions to IQ if there are any instructions there 2732292SN/A 2742292SN/A // Check if there are any instructions coming from rename, and we're. 2752292SN/A // not squashing. 2762292SN/A if (fromRename->insts[0] != NULL && _status != Squashing) { 2771061SN/A 2781060SN/A // Loop through the instructions, putting them in the instruction 2792292SN/A // queue. 2801060SN/A for (int inst_num = 0; inst_num < issueReadWidth; ++inst_num) 2816221Snate@binkert.org { 2826221Snate@binkert.org DynInst *inst = fromRename->insts[inst_num]; 2831060SN/A 2841060SN/A // Make sure there's a valid instruction there. 2851061SN/A if (inst == NULL) 2861060SN/A break; 2872292SN/A 2881060SN/A DPRINTF(IEW, "IEW: Issue: Adding PC %#x to IQ.\n", 2892292SN/A inst->readPC()); 2902292SN/A 2911060SN/A // If it's a memory reference, don't put it in the 2922292SN/A // instruction queue. These will only be executed at commit. 2932292SN/A // Do the same for nonspeculative instructions and nops. 2942292SN/A // Be sure to mark these instructions as ready so that the 2952292SN/A // commit stage can go ahead and execute them, and mark 2962292SN/A // them as issued so the IQ doesn't reprocess them. 2971060SN/A if (inst->isMemRef()) { 2981060SN/A DPRINTF(IEW, "IEW: Issue: Memory instruction " 2991061SN/A "encountered, skipping.\n"); 3002863Sktlim@umich.edu 3019444SAndreas.Sandberg@ARM.com inst->setIssued(); 3021060SN/A inst->setExecuted(); 3039444SAndreas.Sandberg@ARM.com inst->setCanCommit(); 3049444SAndreas.Sandberg@ARM.com 3059444SAndreas.Sandberg@ARM.com instQueue.advanceTail(inst); 3069444SAndreas.Sandberg@ARM.com continue; 30711650Srekai.gonzalezalberquilla@arm.com } else if (inst->isNonSpeculative()) { 30811650Srekai.gonzalezalberquilla@arm.com DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction " 3099444SAndreas.Sandberg@ARM.com "encountered, skipping.\n"); 3109444SAndreas.Sandberg@ARM.com 3112863Sktlim@umich.edu inst->setIssued(); 3122316SN/A inst->setExecuted(); 3131060SN/A inst->setCanCommit(); 3142316SN/A 3152316SN/A instQueue.advanceTail(inst); 3162307SN/A continue; 3171060SN/A } else if (inst->isNop()) { 3189444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "IEW: Issue: Nop instruction encountered " 3199444SAndreas.Sandberg@ARM.com ", skipping.\n"); 3201060SN/A 3219444SAndreas.Sandberg@ARM.com inst->setIssued(); 3229444SAndreas.Sandberg@ARM.com inst->setExecuted(); 3239444SAndreas.Sandberg@ARM.com inst->setCanCommit(); 3249444SAndreas.Sandberg@ARM.com 3256221Snate@binkert.org instQueue.advanceTail(inst); 3269444SAndreas.Sandberg@ARM.com continue; 3279444SAndreas.Sandberg@ARM.com } else if (instQueue.isFull()) { 3289444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "IEW: Issue: IQ has become full.\n"); 3299444SAndreas.Sandberg@ARM.com // Call function to start blocking. 3302307SN/A block(); 3312307SN/A // Tell previous stage to stall. 3322307SN/A toRename->iewInfo.stall = true; 3332307SN/A break; 3342307SN/A } 3356221Snate@binkert.org 3361858SN/A // If the instruction queue is not full, then add the 3372292SN/A // instruction. 3381858SN/A instQueue.insert(fromRename->insts[inst_num]); 3392292SN/A } 3402292SN/A } 3412292SN/A 3422292SN/A // Have the instruction queue try to schedule any ready instructions. 3433788Sgblack@eecs.umich.edu instQueue.scheduleReadyInsts(); 3442292SN/A 3452698Sktlim@umich.edu //////////////////////////////////////// 3463788Sgblack@eecs.umich.edu //EXECUTE/WRITEBACK stage 3472301SN/A //////////////////////////////////////// 3483788Sgblack@eecs.umich.edu 3493788Sgblack@eecs.umich.edu //Put into its own function? 3503788Sgblack@eecs.umich.edu //Similarly should probably have separate execution for int vs FP. 3513788Sgblack@eecs.umich.edu // Above comment is handled by the issue queue only issuing a valid 3523788Sgblack@eecs.umich.edu // mix of int/fp instructions. 3533788Sgblack@eecs.umich.edu //Actually okay to just have one execution, buuuuuut will need 3543788Sgblack@eecs.umich.edu //somewhere that defines the execution latency of all instructions. 3553788Sgblack@eecs.umich.edu // @todo: Move to the FU pool used in the current full cpu. 3563788Sgblack@eecs.umich.edu 3573788Sgblack@eecs.umich.edu int fu_usage = 0; 3583788Sgblack@eecs.umich.edu 3592292SN/A // Execute/writeback any instructions that are available. 3602292SN/A for (int inst_num = 0; 3612292SN/A fu_usage < executeWidth && /* Haven't exceeded available FU's. */ 3622292SN/A inst_num < issueWidth && /* Haven't exceeded issue width. */ 3632292SN/A fromIssue->insts[inst_num]; /* There are available instructions. */ 3642329SN/A ++inst_num) { 3652292SN/A DPRINTF(IEW, "IEW: Execute: Executing instructions from IQ.\n"); 3662935Sksewell@umich.edu 3672935Sksewell@umich.edu // Get instruction from issue's queue. 3682731Sktlim@umich.edu DynInst *inst = fromIssue->insts[inst_num]; 3692292SN/A 3702292SN/A DPRINTF(IEW, "IEW: Execute: Processing PC %#x.\n", inst->readPC()); 3712935Sksewell@umich.edu 3722292SN/A inst->setExecuted(); 3732292SN/A 3742935Sksewell@umich.edu // Check if the instruction is squashed; if so then skip it 3754632Sgblack@eecs.umich.edu // and don't count it towards the FU usage. 3763093Sksewell@umich.edu if (inst->isSquashed()) { 3772292SN/A DPRINTF(IEW, "IEW: Execute: Instruction was squashed.\n"); 3782292SN/A continue; 3793093Sksewell@umich.edu } 3804632Sgblack@eecs.umich.edu 3812935Sksewell@umich.edu // If an instruction is executed, then count it towards FU usage. 3822292SN/A ++fu_usage; 3832292SN/A 3842292SN/A // Execute instruction. 3852292SN/A // Note that if the instruction faults, it will be handled 3862292SN/A // at the commit stage. 3872292SN/A inst->execute(); 3882292SN/A 3892292SN/A // First check the time slot that this instruction will write 3902292SN/A // to. If there are free write ports at the time, then go ahead 3912292SN/A // and write the instruction to that time. If there are not, 3922292SN/A // keep looking back to see where's the first time there's a 3932292SN/A // free slot. What happens if you run out of free spaces? 3942292SN/A // For now naively assume that all instructions take one cycle. 3952292SN/A // Otherwise would have to look into the time buffer based on the 3962292SN/A // latency of the instruction. 3972292SN/A 3986221Snate@binkert.org // Add finished instruction to queue to commit. 3996221Snate@binkert.org toCommit->insts[inst_num] = inst; 4002292SN/A 4012292SN/A // Check if branch was correct. This check happens after the 4023867Sbinkertn@umich.edu // instruction is added to the queue because even if the branch 4036221Snate@binkert.org // is mispredicted, the branch instruction itself is still valid. 4042292SN/A if (inst->mispredicted()) { 4052292SN/A DPRINTF(IEW, "IEW: Execute: Branch mispredict detected.\n"); 4062292SN/A DPRINTF(IEW, "IEW: Execute: Redirecting fetch to PC: %#x.\n", 4072292SN/A inst->nextPC); 4082292SN/A 4092292SN/A // If incorrect, then signal the ROB that it must be squashed. 4102292SN/A squash(inst); 4112292SN/A 4122292SN/A // Not sure it really needs to break. 4132292SN/A// break; 4142292SN/A } 4152292SN/A } 4162292SN/A 4172292SN/A // Loop through the head of the time buffer and wake any dependents. 4182292SN/A // These instructions are about to write back. In the simple model 4192292SN/A // this loop can really happen within the previous loop, but when 4202292SN/A // instructions have actual latencies, this loop must be separate. 4213867Sbinkertn@umich.edu // Also mark scoreboard that this instruction is finally complete. 4222292SN/A // Either have IEW have direct access to rename map, or have this as 4233867Sbinkertn@umich.edu // part of backwards communication. 4246221Snate@binkert.org for (int inst_num = 0; inst_num < executeWidth && 4252292SN/A toCommit->insts[inst_num] != NULL; inst_num++) 4262292SN/A { 4272292SN/A DynInst *inst = toCommit->insts[inst_num]; 4282292SN/A 4292292SN/A DPRINTF(IEW, "IEW: Sending instructions to commit, PC %#x.\n", 4302292SN/A inst->readPC()); 4312292SN/A 4322292SN/A instQueue.wakeDependents(inst); 4332292SN/A 4342292SN/A for (int i = 0; i < inst->numDestRegs(); i++) 4352292SN/A { 4362292SN/A renameMap->markAsReady(inst->renamedDestRegIdx(i)); 4376221Snate@binkert.org } 4382292SN/A } 43910239Sbinhpham@cs.rutgers.edu 44010239Sbinhpham@cs.rutgers.edu // Also should advance its own time buffers if the stage ran. 44110239Sbinhpham@cs.rutgers.edu // Not the best place for it, but this works (hopefully). 44210239Sbinhpham@cs.rutgers.edu issueToExecQueue.advance(); 4432292SN/A} 4442292SN/A