iew_impl.hh revision 10328
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 792820Sktlim@umich.edu wbWidth(params->wbWidth), 809444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 811060SN/A{ 8210172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8310172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8510172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8610172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8710172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 8810172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8910172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9010172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9110172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9210172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9310172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9410172Sdam.sunwoo@arm.com 952292SN/A _status = Active; 962292SN/A exeStatus = Running; 972292SN/A wbStatus = Idle; 981060SN/A 991060SN/A // Setup wire to read instructions coming from issue. 1001060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1011060SN/A 1021060SN/A // Instruction queue needs the queue between issue and execute. 1031060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1041681SN/A 1056221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1066221Snate@binkert.org dispatchStatus[tid] = Running; 1076221Snate@binkert.org fetchRedirect[tid] = false; 1082292SN/A } 1092292SN/A 1102292SN/A updateLSQNextCycle = false; 1112292SN/A 11210328Smitch.hayenga@arm.com skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth; 1132292SN/A} 1142292SN/A 1152292SN/Atemplate <class Impl> 1162292SN/Astd::string 1172292SN/ADefaultIEW<Impl>::name() const 1182292SN/A{ 1192292SN/A return cpu->name() + ".iew"; 1201060SN/A} 1211060SN/A 1221681SN/Atemplate <class Impl> 1231062SN/Avoid 12410023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 12510023Smatt.horsnell@ARM.com{ 12610023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 12710023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 12810023Smatt.horsnell@ARM.com} 12910023Smatt.horsnell@ARM.com 13010023Smatt.horsnell@ARM.comtemplate <class Impl> 13110023Smatt.horsnell@ARM.comvoid 1322292SN/ADefaultIEW<Impl>::regStats() 1331062SN/A{ 1342301SN/A using namespace Stats; 1352301SN/A 1361062SN/A instQueue.regStats(); 1372727Sktlim@umich.edu ldstQueue.regStats(); 1381062SN/A 1391062SN/A iewIdleCycles 1401062SN/A .name(name() + ".iewIdleCycles") 1411062SN/A .desc("Number of cycles IEW is idle"); 1421062SN/A 1431062SN/A iewSquashCycles 1441062SN/A .name(name() + ".iewSquashCycles") 1451062SN/A .desc("Number of cycles IEW is squashing"); 1461062SN/A 1471062SN/A iewBlockCycles 1481062SN/A .name(name() + ".iewBlockCycles") 1491062SN/A .desc("Number of cycles IEW is blocking"); 1501062SN/A 1511062SN/A iewUnblockCycles 1521062SN/A .name(name() + ".iewUnblockCycles") 1531062SN/A .desc("Number of cycles IEW is unblocking"); 1541062SN/A 1551062SN/A iewDispatchedInsts 1561062SN/A .name(name() + ".iewDispatchedInsts") 1571062SN/A .desc("Number of instructions dispatched to IQ"); 1581062SN/A 1591062SN/A iewDispSquashedInsts 1601062SN/A .name(name() + ".iewDispSquashedInsts") 1611062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1621062SN/A 1631062SN/A iewDispLoadInsts 1641062SN/A .name(name() + ".iewDispLoadInsts") 1651062SN/A .desc("Number of dispatched load instructions"); 1661062SN/A 1671062SN/A iewDispStoreInsts 1681062SN/A .name(name() + ".iewDispStoreInsts") 1691062SN/A .desc("Number of dispatched store instructions"); 1701062SN/A 1711062SN/A iewDispNonSpecInsts 1721062SN/A .name(name() + ".iewDispNonSpecInsts") 1731062SN/A .desc("Number of dispatched non-speculative instructions"); 1741062SN/A 1751062SN/A iewIQFullEvents 1761062SN/A .name(name() + ".iewIQFullEvents") 1771062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1781062SN/A 1792292SN/A iewLSQFullEvents 1802292SN/A .name(name() + ".iewLSQFullEvents") 1812292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1822292SN/A 1831062SN/A memOrderViolationEvents 1841062SN/A .name(name() + ".memOrderViolationEvents") 1851062SN/A .desc("Number of memory order violations"); 1861062SN/A 1871062SN/A predictedTakenIncorrect 1881062SN/A .name(name() + ".predictedTakenIncorrect") 1891062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1902292SN/A 1912292SN/A predictedNotTakenIncorrect 1922292SN/A .name(name() + ".predictedNotTakenIncorrect") 1932292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1942292SN/A 1952292SN/A branchMispredicts 1962292SN/A .name(name() + ".branchMispredicts") 1972292SN/A .desc("Number of branch mispredicts detected at execute"); 1982292SN/A 1992292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2002301SN/A 2012727Sktlim@umich.edu iewExecutedInsts 2022353SN/A .name(name() + ".iewExecutedInsts") 2032727Sktlim@umich.edu .desc("Number of executed instructions"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu iewExecLoadInsts 2066221Snate@binkert.org .init(cpu->numThreads) 2072353SN/A .name(name() + ".iewExecLoadInsts") 2082727Sktlim@umich.edu .desc("Number of load instructions executed") 2092727Sktlim@umich.edu .flags(total); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu iewExecSquashedInsts 2122353SN/A .name(name() + ".iewExecSquashedInsts") 2132727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2142727Sktlim@umich.edu 2152727Sktlim@umich.edu iewExecutedSwp 2166221Snate@binkert.org .init(cpu->numThreads) 2178240Snate@binkert.org .name(name() + ".exec_swp") 2182301SN/A .desc("number of swp insts executed") 2192727Sktlim@umich.edu .flags(total); 2202301SN/A 2212727Sktlim@umich.edu iewExecutedNop 2226221Snate@binkert.org .init(cpu->numThreads) 2238240Snate@binkert.org .name(name() + ".exec_nop") 2242301SN/A .desc("number of nop insts executed") 2252727Sktlim@umich.edu .flags(total); 2262301SN/A 2272727Sktlim@umich.edu iewExecutedRefs 2286221Snate@binkert.org .init(cpu->numThreads) 2298240Snate@binkert.org .name(name() + ".exec_refs") 2302301SN/A .desc("number of memory reference insts executed") 2312727Sktlim@umich.edu .flags(total); 2322301SN/A 2332727Sktlim@umich.edu iewExecutedBranches 2346221Snate@binkert.org .init(cpu->numThreads) 2358240Snate@binkert.org .name(name() + ".exec_branches") 2362301SN/A .desc("Number of branches executed") 2372727Sktlim@umich.edu .flags(total); 2382301SN/A 2392301SN/A iewExecStoreInsts 2408240Snate@binkert.org .name(name() + ".exec_stores") 2412301SN/A .desc("Number of stores executed") 2422727Sktlim@umich.edu .flags(total); 2432727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2442727Sktlim@umich.edu 2452727Sktlim@umich.edu iewExecRate 2468240Snate@binkert.org .name(name() + ".exec_rate") 2472727Sktlim@umich.edu .desc("Inst execution rate") 2482727Sktlim@umich.edu .flags(total); 2492727Sktlim@umich.edu 2502727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2512301SN/A 2522301SN/A iewInstsToCommit 2536221Snate@binkert.org .init(cpu->numThreads) 2548240Snate@binkert.org .name(name() + ".wb_sent") 2552301SN/A .desc("cumulative count of insts sent to commit") 2562727Sktlim@umich.edu .flags(total); 2572301SN/A 2582326SN/A writebackCount 2596221Snate@binkert.org .init(cpu->numThreads) 2608240Snate@binkert.org .name(name() + ".wb_count") 2612301SN/A .desc("cumulative count of insts written-back") 2622727Sktlim@umich.edu .flags(total); 2632301SN/A 2642326SN/A producerInst 2656221Snate@binkert.org .init(cpu->numThreads) 2668240Snate@binkert.org .name(name() + ".wb_producers") 2672301SN/A .desc("num instructions producing a value") 2682727Sktlim@umich.edu .flags(total); 2692301SN/A 2702326SN/A consumerInst 2716221Snate@binkert.org .init(cpu->numThreads) 2728240Snate@binkert.org .name(name() + ".wb_consumers") 2732301SN/A .desc("num instructions consuming a value") 2742727Sktlim@umich.edu .flags(total); 2752301SN/A 2762326SN/A wbPenalized 2776221Snate@binkert.org .init(cpu->numThreads) 2788240Snate@binkert.org .name(name() + ".wb_penalized") 2792301SN/A .desc("number of instrctions required to write to 'other' IQ") 2802727Sktlim@umich.edu .flags(total); 2812301SN/A 2822326SN/A wbPenalizedRate 2838240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2842301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2852727Sktlim@umich.edu .flags(total); 2862301SN/A 2872326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2882301SN/A 2892326SN/A wbFanout 2908240Snate@binkert.org .name(name() + ".wb_fanout") 2912301SN/A .desc("average fanout of values written-back") 2922727Sktlim@umich.edu .flags(total); 2932301SN/A 2942326SN/A wbFanout = producerInst / consumerInst; 2952301SN/A 2962326SN/A wbRate 2978240Snate@binkert.org .name(name() + ".wb_rate") 2982301SN/A .desc("insts written-back per cycle") 2992727Sktlim@umich.edu .flags(total); 3002326SN/A wbRate = writebackCount / cpu->numCycles; 3011062SN/A} 3021062SN/A 3031681SN/Atemplate<class Impl> 3041060SN/Avoid 3059427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3061060SN/A{ 3076221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3082292SN/A toRename->iewInfo[tid].usedIQ = true; 3092292SN/A toRename->iewInfo[tid].freeIQEntries = 3102292SN/A instQueue.numFreeEntries(tid); 3112292SN/A 3122292SN/A toRename->iewInfo[tid].usedLSQ = true; 31310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 31410239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3152292SN/A } 3162292SN/A 3178887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3188733Sgeoffrey.blake@arm.com if (cpu->checker) { 3198850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3208887Sgeoffrey.blake@arm.com } 3218733Sgeoffrey.blake@arm.com 3222733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3231060SN/A} 3241060SN/A 3251681SN/Atemplate<class Impl> 3261060SN/Avoid 3272292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3281060SN/A{ 3291060SN/A timeBuffer = tb_ptr; 3301060SN/A 3311060SN/A // Setup wire to read information from time buffer, from commit. 3321060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3331060SN/A 3341060SN/A // Setup wire to write information back to previous stages. 3351060SN/A toRename = timeBuffer->getWire(0); 3361060SN/A 3372292SN/A toFetch = timeBuffer->getWire(0); 3382292SN/A 3391060SN/A // Instruction queue also needs main time buffer. 3401060SN/A instQueue.setTimeBuffer(tb_ptr); 3411060SN/A} 3421060SN/A 3431681SN/Atemplate<class Impl> 3441060SN/Avoid 3452292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3461060SN/A{ 3471060SN/A renameQueue = rq_ptr; 3481060SN/A 3491060SN/A // Setup wire to read information from rename queue. 3501060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3511060SN/A} 3521060SN/A 3531681SN/Atemplate<class Impl> 3541060SN/Avoid 3552292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3561060SN/A{ 3571060SN/A iewQueue = iq_ptr; 3581060SN/A 3591060SN/A // Setup wire to write instructions to commit. 3601060SN/A toCommit = iewQueue->getWire(0); 3611060SN/A} 3621060SN/A 3631681SN/Atemplate<class Impl> 3641060SN/Avoid 3656221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3661060SN/A{ 3672292SN/A activeThreads = at_ptr; 3682292SN/A 3692292SN/A ldstQueue.setActiveThreads(at_ptr); 3702292SN/A instQueue.setActiveThreads(at_ptr); 3711060SN/A} 3721060SN/A 3731681SN/Atemplate<class Impl> 3741060SN/Avoid 3752292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3761060SN/A{ 3772292SN/A scoreboard = sb_ptr; 3781060SN/A} 3791060SN/A 3802307SN/Atemplate <class Impl> 3812863Sktlim@umich.edubool 3829444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3832307SN/A{ 3849444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3859444SAndreas.Sandberg@ARM.com 3869444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3879444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3889444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3899444SAndreas.Sandberg@ARM.com drained = false; 3909444SAndreas.Sandberg@ARM.com } 3919444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3929444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3939444SAndreas.Sandberg@ARM.com drained = false; 3949444SAndreas.Sandberg@ARM.com } 3959444SAndreas.Sandberg@ARM.com } 3969444SAndreas.Sandberg@ARM.com 3979783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 3989783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 3999783Sandreas.hansson@arm.com // above 4009783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4019783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4029783Sandreas.hansson@arm.com drained = false; 4039783Sandreas.hansson@arm.com } 4049783Sandreas.hansson@arm.com 4059444SAndreas.Sandberg@ARM.com return drained; 4061681SN/A} 4071681SN/A 4082316SN/Atemplate <class Impl> 4091681SN/Avoid 4109444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4112843Sktlim@umich.edu{ 4129444SAndreas.Sandberg@ARM.com assert(isDrained()); 4132843Sktlim@umich.edu 4149444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4159444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4161681SN/A} 4171681SN/A 4182307SN/Atemplate <class Impl> 4191681SN/Avoid 4202307SN/ADefaultIEW<Impl>::takeOverFrom() 4211060SN/A{ 4222348SN/A // Reset all state. 4232307SN/A _status = Active; 4242307SN/A exeStatus = Running; 4252307SN/A wbStatus = Idle; 4261060SN/A 4272307SN/A instQueue.takeOverFrom(); 4282307SN/A ldstQueue.takeOverFrom(); 4299444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4301060SN/A 4319427SAndreas.Sandberg@ARM.com startupStage(); 4322307SN/A cpu->activityThisCycle(); 4331060SN/A 4346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4356221Snate@binkert.org dispatchStatus[tid] = Running; 4366221Snate@binkert.org fetchRedirect[tid] = false; 4372307SN/A } 4381060SN/A 4392307SN/A updateLSQNextCycle = false; 4402307SN/A 4412873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4422307SN/A issueToExecQueue.advance(); 4431060SN/A } 4441060SN/A} 4451060SN/A 4461681SN/Atemplate<class Impl> 4471060SN/Avoid 4486221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4492107SN/A{ 4506221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4512107SN/A 4522292SN/A // Tell the IQ to start squashing. 4532292SN/A instQueue.squash(tid); 4542107SN/A 4552292SN/A // Tell the LDSTQ to start squashing. 4562326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4572292SN/A updatedQueues = true; 4582107SN/A 4592292SN/A // Clear the skid buffer in case it has any data in it. 4602935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4614632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4622935Sksewell@umich.edu 4632292SN/A while (!skidBuffer[tid].empty()) { 46410239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 46510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 46610239Sbinhpham@cs.rutgers.edu } 46710239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isStore()) { 46810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4692292SN/A } 4702107SN/A 4712292SN/A toRename->iewInfo[tid].dispatched++; 4722107SN/A 4732292SN/A skidBuffer[tid].pop(); 4742292SN/A } 4752107SN/A 4762702Sktlim@umich.edu emptyRenameInsts(tid); 4772107SN/A} 4782107SN/A 4792107SN/Atemplate<class Impl> 4802107SN/Avoid 4816221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4822292SN/A{ 4837720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4847720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4852292SN/A 48610231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 4877852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4887852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4897852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4907852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4912935Sksewell@umich.edu 4927852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4937852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4942292SN/A 4957852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4967852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4977852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4982292SN/A 4997852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5007852SMatt.Horsnell@arm.com } 5017852SMatt.Horsnell@arm.com 5022292SN/A} 5032292SN/A 5042292SN/Atemplate<class Impl> 5052292SN/Avoid 5066221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5072292SN/A{ 5088513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5098513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5108513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5118513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5128513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5138513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5148513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5158513SGiacomo.Gabrielli@arm.com // the squash. 51610231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5178513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5188513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5192292SN/A 5207852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5218513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5228137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5232292SN/A 5248513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5258513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5262292SN/A 5277852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5287852SMatt.Horsnell@arm.com } 5292292SN/A} 5302292SN/A 5312292SN/Atemplate<class Impl> 5322292SN/Avoid 5336221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5342292SN/A{ 5352292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5367720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 53710231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5387852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5397852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5402292SN/A 5417852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5427852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5438137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5442292SN/A 5457852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5467852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5472292SN/A 5487852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5492292SN/A 5507852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5517852SMatt.Horsnell@arm.com } 5522292SN/A} 5532292SN/A 5542292SN/Atemplate<class Impl> 5552292SN/Avoid 5566221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5572292SN/A{ 5582292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5592292SN/A 5602292SN/A if (dispatchStatus[tid] != Blocked && 5612292SN/A dispatchStatus[tid] != Unblocking) { 5622292SN/A toRename->iewBlock[tid] = true; 5632292SN/A wroteToTimeBuffer = true; 5642292SN/A } 5652292SN/A 5662292SN/A // Add the current inputs to the skid buffer so they can be 5672292SN/A // reprocessed when this stage unblocks. 5682292SN/A skidInsert(tid); 5692292SN/A 5702292SN/A dispatchStatus[tid] = Blocked; 5712292SN/A} 5722292SN/A 5732292SN/Atemplate<class Impl> 5742292SN/Avoid 5756221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5762292SN/A{ 5772292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5782292SN/A "buffer %u.\n",tid, tid); 5792292SN/A 5802292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5812292SN/A // Also switch status to running. 5822292SN/A if (skidBuffer[tid].empty()) { 5832292SN/A toRename->iewUnblock[tid] = true; 5842292SN/A wroteToTimeBuffer = true; 5852292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5862292SN/A dispatchStatus[tid] = Running; 5872292SN/A } 5882292SN/A} 5892292SN/A 5902292SN/Atemplate<class Impl> 5912292SN/Avoid 5922292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5931060SN/A{ 5941681SN/A instQueue.wakeDependents(inst); 5951060SN/A} 5961060SN/A 5972292SN/Atemplate<class Impl> 5982292SN/Avoid 5992292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6002292SN/A{ 6012292SN/A instQueue.rescheduleMemInst(inst); 6022292SN/A} 6031681SN/A 6041681SN/Atemplate<class Impl> 6051060SN/Avoid 6062292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6071060SN/A{ 6082292SN/A instQueue.replayMemInst(inst); 6092292SN/A} 6101060SN/A 6112292SN/Atemplate<class Impl> 6122292SN/Avoid 6132292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6142292SN/A{ 6153221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6163221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6173221Sktlim@umich.edu // being added to the queue to commit without being processed by 6183221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6193221Sktlim@umich.edu 6202292SN/A // First check the time slot that this instruction will write 6212292SN/A // to. If there are free write ports at the time, then go ahead 6222292SN/A // and write the instruction to that time. If there are not, 6232292SN/A // keep looking back to see where's the first time there's a 6242326SN/A // free slot. 6252292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6262292SN/A ++wbNumInst; 6272820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6282292SN/A ++wbCycle; 6292292SN/A wbNumInst = 0; 6302292SN/A } 6312292SN/A } 6322292SN/A 6332353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6342353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6352292SN/A // Add finished instruction to queue to commit. 6362292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6372292SN/A (*iewQueue)[wbCycle].size++; 6382292SN/A} 6392292SN/A 6402292SN/Atemplate <class Impl> 6412292SN/Aunsigned 6422292SN/ADefaultIEW<Impl>::validInstsFromRename() 6432292SN/A{ 6442292SN/A unsigned inst_count = 0; 6452292SN/A 6462292SN/A for (int i=0; i<fromRename->size; i++) { 6472731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6482292SN/A inst_count++; 6492292SN/A } 6502292SN/A 6512292SN/A return inst_count; 6522292SN/A} 6532292SN/A 6542292SN/Atemplate<class Impl> 6552292SN/Avoid 6566221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6572292SN/A{ 6582292SN/A DynInstPtr inst = NULL; 6592292SN/A 6602292SN/A while (!insts[tid].empty()) { 6612292SN/A inst = insts[tid].front(); 6622292SN/A 6632292SN/A insts[tid].pop(); 6642292SN/A 6659937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6662292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6677720Sgblack@eecs.umich.edu inst->pcState(),tid); 6682292SN/A 6692292SN/A skidBuffer[tid].push(inst); 6702292SN/A } 6712292SN/A 6722292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6732292SN/A "Skidbuffer Exceeded Max Size"); 6742292SN/A} 6752292SN/A 6762292SN/Atemplate<class Impl> 6772292SN/Aint 6782292SN/ADefaultIEW<Impl>::skidCount() 6792292SN/A{ 6802292SN/A int max=0; 6812292SN/A 6826221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6836221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6842292SN/A 6853867Sbinkertn@umich.edu while (threads != end) { 6866221Snate@binkert.org ThreadID tid = *threads++; 6873867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6882292SN/A if (max < thread_count) 6892292SN/A max = thread_count; 6902292SN/A } 6912292SN/A 6922292SN/A return max; 6932292SN/A} 6942292SN/A 6952292SN/Atemplate<class Impl> 6962292SN/Abool 6972292SN/ADefaultIEW<Impl>::skidsEmpty() 6982292SN/A{ 6996221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7006221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7012292SN/A 7023867Sbinkertn@umich.edu while (threads != end) { 7036221Snate@binkert.org ThreadID tid = *threads++; 7043867Sbinkertn@umich.edu 7053867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7062292SN/A return false; 7072292SN/A } 7082292SN/A 7092292SN/A return true; 7101062SN/A} 7111062SN/A 7121681SN/Atemplate <class Impl> 7131062SN/Avoid 7142292SN/ADefaultIEW<Impl>::updateStatus() 7151062SN/A{ 7162292SN/A bool any_unblocking = false; 7171062SN/A 7186221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7196221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7201062SN/A 7213867Sbinkertn@umich.edu while (threads != end) { 7226221Snate@binkert.org ThreadID tid = *threads++; 7231062SN/A 7242292SN/A if (dispatchStatus[tid] == Unblocking) { 7252292SN/A any_unblocking = true; 7262292SN/A break; 7272292SN/A } 7282292SN/A } 7291062SN/A 7302292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7312292SN/A // and there's no stores waiting to write back, and dispatch is not 7322292SN/A // unblocking, then there is no internal activity for the IEW stage. 7337897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7342292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7352292SN/A !ldstQueue.willWB() && !any_unblocking) { 7362292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7371062SN/A 7382292SN/A deactivateStage(); 7391062SN/A 7402292SN/A _status = Inactive; 7412292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7422292SN/A ldstQueue.willWB() || 7432292SN/A any_unblocking)) { 7442292SN/A // Otherwise there is internal activity. Set to active. 7452292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7461062SN/A 7472292SN/A activateStage(); 7481062SN/A 7492292SN/A _status = Active; 7501062SN/A } 7511062SN/A} 7521062SN/A 7531681SN/Atemplate <class Impl> 7541062SN/Avoid 7552292SN/ADefaultIEW<Impl>::resetEntries() 7561062SN/A{ 7572292SN/A instQueue.resetEntries(); 7582292SN/A ldstQueue.resetEntries(); 7592292SN/A} 7601062SN/A 7612292SN/Atemplate <class Impl> 7622292SN/Abool 7636221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7642292SN/A{ 7652292SN/A bool ret_val(false); 7662292SN/A 76710328Smitch.hayenga@arm.com if (fromCommit->commitInfo[tid].robSquashing) { 7682292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7692292SN/A ret_val = true; 7702292SN/A } else if (instQueue.isFull(tid)) { 7712292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7722292SN/A ret_val = true; 7732292SN/A } 7742292SN/A 7752292SN/A return ret_val; 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7806221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7812292SN/A{ 7822292SN/A // Check if there's a squash signal, squash if there is 7832292SN/A // Check stall signals, block if there is. 7842292SN/A // If status was Blocked 7852292SN/A // if so then go to unblocking 7862292SN/A // If status was Squashing 7872292SN/A // check if squashing is not high. Switch to running this cycle. 7882292SN/A 7892292SN/A if (fromCommit->commitInfo[tid].squash) { 7902292SN/A squash(tid); 7912292SN/A 7922292SN/A if (dispatchStatus[tid] == Blocked || 7932292SN/A dispatchStatus[tid] == Unblocking) { 7942292SN/A toRename->iewUnblock[tid] = true; 7952292SN/A wroteToTimeBuffer = true; 7962292SN/A } 7972292SN/A 7982292SN/A dispatchStatus[tid] = Squashing; 7992292SN/A fetchRedirect[tid] = false; 8002292SN/A return; 8012292SN/A } 8022292SN/A 8032292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8042702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8052292SN/A 8062292SN/A dispatchStatus[tid] = Squashing; 8072702Sktlim@umich.edu emptyRenameInsts(tid); 8082702Sktlim@umich.edu wroteToTimeBuffer = true; 8092292SN/A } 8102292SN/A 8112292SN/A if (checkStall(tid)) { 8122292SN/A block(tid); 8132292SN/A dispatchStatus[tid] = Blocked; 8142292SN/A return; 8152292SN/A } 8162292SN/A 8172292SN/A if (dispatchStatus[tid] == Blocked) { 8182292SN/A // Status from previous cycle was blocked, but there are no more stall 8192292SN/A // conditions. Switch over to unblocking. 8202292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8212292SN/A tid); 8222292SN/A 8232292SN/A dispatchStatus[tid] = Unblocking; 8242292SN/A 8252292SN/A unblock(tid); 8262292SN/A 8272292SN/A return; 8282292SN/A } 8292292SN/A 8302292SN/A if (dispatchStatus[tid] == Squashing) { 8312292SN/A // Switch status to running if rename isn't being told to block or 8322292SN/A // squash this cycle. 8332292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8342292SN/A tid); 8352292SN/A 8362292SN/A dispatchStatus[tid] = Running; 8372292SN/A 8382292SN/A return; 8392292SN/A } 8402292SN/A} 8412292SN/A 8422292SN/Atemplate <class Impl> 8432292SN/Avoid 8442292SN/ADefaultIEW<Impl>::sortInsts() 8452292SN/A{ 8462292SN/A int insts_from_rename = fromRename->size; 8472326SN/A#ifdef DEBUG 8486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8496221Snate@binkert.org assert(insts[tid].empty()); 8502326SN/A#endif 8512292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8522292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8532292SN/A } 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Avoid 8586221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8592702Sktlim@umich.edu{ 8604632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8612935Sksewell@umich.edu 8622702Sktlim@umich.edu while (!insts[tid].empty()) { 8632935Sksewell@umich.edu 86410239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 86510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 86610239Sbinhpham@cs.rutgers.edu } 86710239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isStore()) { 86810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 8692702Sktlim@umich.edu } 8702702Sktlim@umich.edu 8712702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8722702Sktlim@umich.edu 8732702Sktlim@umich.edu insts[tid].pop(); 8742702Sktlim@umich.edu } 8752702Sktlim@umich.edu} 8762702Sktlim@umich.edu 8772702Sktlim@umich.edutemplate <class Impl> 8782702Sktlim@umich.eduvoid 8792292SN/ADefaultIEW<Impl>::wakeCPU() 8802292SN/A{ 8812292SN/A cpu->wakeCPU(); 8822292SN/A} 8832292SN/A 8842292SN/Atemplate <class Impl> 8852292SN/Avoid 8862292SN/ADefaultIEW<Impl>::activityThisCycle() 8872292SN/A{ 8882292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8892292SN/A cpu->activityThisCycle(); 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932292SN/Ainline void 8942292SN/ADefaultIEW<Impl>::activateStage() 8952292SN/A{ 8962292SN/A DPRINTF(Activity, "Activating stage.\n"); 8972733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Ainline void 9022292SN/ADefaultIEW<Impl>::deactivateStage() 9032292SN/A{ 9042292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9052733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9062292SN/A} 9072292SN/A 9082292SN/Atemplate<class Impl> 9092292SN/Avoid 9106221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9112292SN/A{ 9122292SN/A // If status is Running or idle, 9132292SN/A // call dispatchInsts() 9142292SN/A // If status is Unblocking, 9152292SN/A // buffer any instructions coming from rename 9162292SN/A // continue trying to empty skid buffer 9172292SN/A // check if stall conditions have passed 9182292SN/A 9192292SN/A if (dispatchStatus[tid] == Blocked) { 9202292SN/A ++iewBlockCycles; 9212292SN/A 9222292SN/A } else if (dispatchStatus[tid] == Squashing) { 9232292SN/A ++iewSquashCycles; 9242292SN/A } 9252292SN/A 9262292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9272292SN/A // will allow, as long as it is not currently blocked. 9282292SN/A if (dispatchStatus[tid] == Running || 9292292SN/A dispatchStatus[tid] == Idle) { 9302292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9312292SN/A "dispatch.\n", tid); 9322292SN/A 9332292SN/A dispatchInsts(tid); 9342292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9352292SN/A // Make sure that the skid buffer has something in it if the 9362292SN/A // status is unblocking. 9372292SN/A assert(!skidsEmpty()); 9382292SN/A 9392292SN/A // If the status was unblocking, then instructions from the skid 9402292SN/A // buffer were used. Remove those instructions and handle 9412292SN/A // the rest of unblocking. 9422292SN/A dispatchInsts(tid); 9432292SN/A 9442292SN/A ++iewUnblockCycles; 9452292SN/A 9465215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9472292SN/A // Add the current inputs to the skid buffer so they can be 9482292SN/A // reprocessed when this stage unblocks. 9492292SN/A skidInsert(tid); 9502292SN/A } 9512292SN/A 9522292SN/A unblock(tid); 9532292SN/A } 9542292SN/A} 9552292SN/A 9562292SN/Atemplate <class Impl> 9572292SN/Avoid 9586221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9592292SN/A{ 9602292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9612292SN/A // otherwise. 9622292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9632292SN/A dispatchStatus[tid] == Unblocking ? 9642292SN/A skidBuffer[tid] : insts[tid]; 9652292SN/A 9662292SN/A int insts_to_add = insts_to_dispatch.size(); 9672292SN/A 9682292SN/A DynInstPtr inst; 9692292SN/A bool add_to_iq = false; 9702292SN/A int dis_num_inst = 0; 9712292SN/A 9722292SN/A // Loop through the instructions, putting them in the instruction 9732292SN/A // queue. 9742292SN/A for ( ; dis_num_inst < insts_to_add && 9752820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9762292SN/A ++dis_num_inst) 9772292SN/A { 9782292SN/A inst = insts_to_dispatch.front(); 9792292SN/A 9802292SN/A if (dispatchStatus[tid] == Unblocking) { 9812292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9822292SN/A "buffer\n", tid); 9832292SN/A } 9842292SN/A 9852292SN/A // Make sure there's a valid instruction there. 9862292SN/A assert(inst); 9872292SN/A 9887720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 9892292SN/A "IQ.\n", 9907720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 9912292SN/A 9922292SN/A // Be sure to mark these instructions as ready so that the 9932292SN/A // commit stage can go ahead and execute them, and mark 9942292SN/A // them as issued so the IQ doesn't reprocess them. 9952292SN/A 9962292SN/A // Check for squashed instructions. 9972292SN/A if (inst->isSquashed()) { 9982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9992292SN/A "not adding to IQ.\n", tid); 10002292SN/A 10012292SN/A ++iewDispSquashedInsts; 10022292SN/A 10032292SN/A insts_to_dispatch.pop(); 10042292SN/A 10052292SN/A //Tell Rename That An Instruction has been processed 100610239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 100710239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10082292SN/A } 100910239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 101010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 101110239Sbinhpham@cs.rutgers.edu } 101210239Sbinhpham@cs.rutgers.edu 10132292SN/A toRename->iewInfo[tid].dispatched++; 10142292SN/A 10152292SN/A continue; 10162292SN/A } 10172292SN/A 10182292SN/A // Check for full conditions. 10192292SN/A if (instQueue.isFull(tid)) { 10202292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10212292SN/A 10222292SN/A // Call function to start blocking. 10232292SN/A block(tid); 10242292SN/A 10252292SN/A // Set unblock to false. Special case where we are using 10262292SN/A // skidbuffer (unblocking) instructions but then we still 10272292SN/A // get full in the IQ. 10282292SN/A toRename->iewUnblock[tid] = false; 10292292SN/A 10302292SN/A ++iewIQFullEvents; 10312292SN/A break; 103210240Sbinhpham@cs.rutgers.edu } 103310240Sbinhpham@cs.rutgers.edu 103410240Sbinhpham@cs.rutgers.edu // Check LSQ if inst is LD/ST 103510240Sbinhpham@cs.rutgers.edu if ((inst->isLoad() && ldstQueue.lqFull(tid)) || 103610240Sbinhpham@cs.rutgers.edu (inst->isStore() && ldstQueue.sqFull(tid))) { 103710240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, 103810240Sbinhpham@cs.rutgers.edu inst->isLoad() ? "LQ" : "SQ"); 10392292SN/A 10402292SN/A // Call function to start blocking. 10412292SN/A block(tid); 10422292SN/A 10432292SN/A // Set unblock to false. Special case where we are using 10442292SN/A // skidbuffer (unblocking) instructions but then we still 10452292SN/A // get full in the IQ. 10462292SN/A toRename->iewUnblock[tid] = false; 10472292SN/A 10482292SN/A ++iewLSQFullEvents; 10492292SN/A break; 10502292SN/A } 10512292SN/A 10522292SN/A // Otherwise issue the instruction just fine. 10532292SN/A if (inst->isLoad()) { 10542292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10552292SN/A "encountered, adding to LSQ.\n", tid); 10562292SN/A 10572292SN/A // Reserve a spot in the load store queue for this 10582292SN/A // memory access. 10592292SN/A ldstQueue.insertLoad(inst); 10602292SN/A 10612292SN/A ++iewDispLoadInsts; 10622292SN/A 10632292SN/A add_to_iq = true; 10642292SN/A 106510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10662292SN/A } else if (inst->isStore()) { 10672292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10682292SN/A "encountered, adding to LSQ.\n", tid); 10692292SN/A 10702292SN/A ldstQueue.insertStore(inst); 10712292SN/A 10722292SN/A ++iewDispStoreInsts; 10732292SN/A 10742336SN/A if (inst->isStoreConditional()) { 10752336SN/A // Store conditionals need to be set as "canCommit()" 10762336SN/A // so that commit can process them when they reach the 10772336SN/A // head of commit. 10782348SN/A // @todo: This is somewhat specific to Alpha. 10792292SN/A inst->setCanCommit(); 10802292SN/A instQueue.insertNonSpec(inst); 10812292SN/A add_to_iq = false; 10822292SN/A 10832292SN/A ++iewDispNonSpecInsts; 10842292SN/A } else { 10852292SN/A add_to_iq = true; 10862292SN/A } 10872292SN/A 108810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 10892292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10902326SN/A // Same as non-speculative stores. 10912292SN/A inst->setCanCommit(); 10922292SN/A instQueue.insertBarrier(inst); 10932292SN/A add_to_iq = false; 10942292SN/A } else if (inst->isNop()) { 10952292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10962292SN/A "skipping.\n", tid); 10972292SN/A 10982292SN/A inst->setIssued(); 10992292SN/A inst->setExecuted(); 11002292SN/A inst->setCanCommit(); 11012292SN/A 11022326SN/A instQueue.recordProducer(inst); 11032292SN/A 11042727Sktlim@umich.edu iewExecutedNop[tid]++; 11052301SN/A 11062292SN/A add_to_iq = false; 11072292SN/A } else if (inst->isExecuted()) { 11082292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11092292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11102292SN/A "skipping.\n"); 11112292SN/A 11122292SN/A inst->setIssued(); 11132292SN/A inst->setCanCommit(); 11142292SN/A 11152326SN/A instQueue.recordProducer(inst); 11162292SN/A 11172292SN/A add_to_iq = false; 11182292SN/A } else { 11192292SN/A add_to_iq = true; 11202292SN/A } 11214033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11224033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11234033Sktlim@umich.edu "encountered, skipping.\n", tid); 11244033Sktlim@umich.edu 11254033Sktlim@umich.edu // Same as non-speculative stores. 11264033Sktlim@umich.edu inst->setCanCommit(); 11274033Sktlim@umich.edu 11284033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11294033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11304033Sktlim@umich.edu 11314033Sktlim@umich.edu ++iewDispNonSpecInsts; 11324033Sktlim@umich.edu 11334033Sktlim@umich.edu add_to_iq = false; 11344033Sktlim@umich.edu } 11352292SN/A 11362292SN/A // If the instruction queue is not full, then add the 11372292SN/A // instruction. 11382292SN/A if (add_to_iq) { 11392292SN/A instQueue.insert(inst); 11402292SN/A } 11412292SN/A 11422292SN/A insts_to_dispatch.pop(); 11432292SN/A 11442292SN/A toRename->iewInfo[tid].dispatched++; 11452292SN/A 11462292SN/A ++iewDispatchedInsts; 11478471SGiacomo.Gabrielli@arm.com 11488471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11499046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11508471SGiacomo.Gabrielli@arm.com#endif 115110023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11522292SN/A } 11532292SN/A 11542292SN/A if (!insts_to_dispatch.empty()) { 11552935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11562292SN/A block(tid); 11572292SN/A toRename->iewUnblock[tid] = false; 11582292SN/A } 11592292SN/A 11602292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11612292SN/A dispatchStatus[tid] = Running; 11622292SN/A 11632292SN/A updatedQueues = true; 11642292SN/A } 11652292SN/A 11662292SN/A dis_num_inst = 0; 11672292SN/A} 11682292SN/A 11692292SN/Atemplate <class Impl> 11702292SN/Avoid 11712292SN/ADefaultIEW<Impl>::printAvailableInsts() 11722292SN/A{ 11732292SN/A int inst = 0; 11742292SN/A 11752980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11762292SN/A 11772292SN/A while (fromIssue->insts[inst]) { 11782292SN/A 11792980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11802292SN/A 11817720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11822292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11832292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11842292SN/A 11852292SN/A inst++; 11862292SN/A 11872292SN/A } 11882292SN/A 11892980Sgblack@eecs.umich.edu std::cout << "\n"; 11902292SN/A} 11912292SN/A 11922292SN/Atemplate <class Impl> 11932292SN/Avoid 11942292SN/ADefaultIEW<Impl>::executeInsts() 11952292SN/A{ 11962292SN/A wbNumInst = 0; 11972292SN/A wbCycle = 0; 11982292SN/A 11996221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12006221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12012292SN/A 12023867Sbinkertn@umich.edu while (threads != end) { 12036221Snate@binkert.org ThreadID tid = *threads++; 12042292SN/A fetchRedirect[tid] = false; 12052292SN/A } 12062292SN/A 12072698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12087599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12092698Sktlim@umich.edu// printAvailableInsts(); 12101062SN/A 12111062SN/A // Execute/writeback any instructions that are available. 12122333SN/A int insts_to_execute = fromIssue->size; 12132292SN/A int inst_num = 0; 12142333SN/A for (; inst_num < insts_to_execute; 12152326SN/A ++inst_num) { 12161062SN/A 12172292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12181062SN/A 12192333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12201062SN/A 12217720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12227720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12231062SN/A 12241062SN/A // Check if the instruction is squashed; if so then skip it 12251062SN/A if (inst->isSquashed()) { 12268315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12278315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12288315Sgeoffrey.blake@arm.com inst->seqNum); 12291062SN/A 12301062SN/A // Consider this instruction executed so that commit can go 12311062SN/A // ahead and retire the instruction. 12321062SN/A inst->setExecuted(); 12331062SN/A 12342292SN/A // Not sure if I should set this here or just let commit try to 12352292SN/A // commit any squashed instructions. I like the latter a bit more. 12362292SN/A inst->setCanCommit(); 12371062SN/A 12381062SN/A ++iewExecSquashedInsts; 12391062SN/A 12401062SN/A continue; 12411062SN/A } 12421062SN/A 12432292SN/A Fault fault = NoFault; 12441062SN/A 12451062SN/A // Execute instruction. 12461062SN/A // Note that if the instruction faults, it will be handled 12471062SN/A // at the commit stage. 12487850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12492292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12501062SN/A "reference.\n"); 12511062SN/A 12521062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12531062SN/A if (inst->isLoad()) { 12542292SN/A // Loads will mark themselves as executed, and their writeback 12552292SN/A // event adds the instruction to the queue to commit 12562292SN/A fault = ldstQueue.executeLoad(inst); 12577944SGiacomo.Gabrielli@arm.com 12587944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12597944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12607944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12617944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12627944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12637944SGiacomo.Gabrielli@arm.com "load.\n"); 12647944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12657944SGiacomo.Gabrielli@arm.com continue; 12667944SGiacomo.Gabrielli@arm.com } 12677944SGiacomo.Gabrielli@arm.com 12687850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12698073SAli.Saidi@ARM.com inst->fault = NoFault; 12707850SMatt.Horsnell@arm.com } 12711062SN/A } else if (inst->isStore()) { 12722367SN/A fault = ldstQueue.executeStore(inst); 12731062SN/A 12747944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12757944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12767944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12777944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12787944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12797944SGiacomo.Gabrielli@arm.com "store.\n"); 12807944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12817944SGiacomo.Gabrielli@arm.com continue; 12827944SGiacomo.Gabrielli@arm.com } 12837944SGiacomo.Gabrielli@arm.com 12842292SN/A // If the store had a fault then it may not have a mem req 128510231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 12867782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12877782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12887782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12892367SN/A // Send this instruction to commit, also make sure iew stage 12902367SN/A // realizes there is activity. 12912367SN/A inst->setExecuted(); 12922367SN/A instToCommit(inst); 12932367SN/A activityThisCycle(); 12942292SN/A } 12952326SN/A 12962326SN/A // Store conditionals will mark themselves as 12972326SN/A // executed, and their writeback event will add the 12982326SN/A // instruction to the queue to commit. 12991062SN/A } else { 13002292SN/A panic("Unexpected memory type!\n"); 13011062SN/A } 13021062SN/A 13031062SN/A } else { 13047847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13057847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13067847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13077847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13087847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13097847Sminkyu.jeong@arm.com inst->execute(); 131010231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 13117848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13127847Sminkyu.jeong@arm.com } 13131062SN/A 13142292SN/A inst->setExecuted(); 13152292SN/A 13162292SN/A instToCommit(inst); 13171062SN/A } 13181062SN/A 13192301SN/A updateExeInstStats(inst); 13201681SN/A 13212326SN/A // Check if branch prediction was correct, if not then we need 13222326SN/A // to tell commit to squash in flight instructions. Only 13232326SN/A // handle this if there hasn't already been something that 13242107SN/A // redirects fetch in this group of instructions. 13251681SN/A 13262292SN/A // This probably needs to prioritize the redirects if a different 13272292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13282292SN/A // instruction first, so the branch resolution order will be correct. 13296221Snate@binkert.org ThreadID tid = inst->threadNumber; 13301062SN/A 13313732Sktlim@umich.edu if (!fetchRedirect[tid] || 13327852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13333732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13341062SN/A 13357856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13367856SMatt.Horsnell@arm.com // that have not been executed. 13377856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13387856SMatt.Horsnell@arm.com 13397856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13402292SN/A fetchRedirect[tid] = true; 13411062SN/A 13422292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13438674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13448674Snilay@cs.wisc.edu inst->readPredTarg()); 13457720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13468674Snilay@cs.wisc.edu inst->pcState()); 13471062SN/A // If incorrect, then signal the ROB that it must be squashed. 13482292SN/A squashDueToBranch(inst, tid); 13491062SN/A 135010023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 135110023Smatt.horsnell@ARM.com 13523795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13531062SN/A predictedTakenIncorrect++; 13542292SN/A } else { 13552292SN/A predictedNotTakenIncorrect++; 13561062SN/A } 13572292SN/A } else if (ldstQueue.violation(tid)) { 13584033Sktlim@umich.edu assert(inst->isMemRef()); 13592326SN/A // If there was an ordering violation, then get the 13602326SN/A // DynInst that caused the violation. Note that this 13612292SN/A // clears the violation signal. 13622292SN/A DynInstPtr violator; 13632292SN/A violator = ldstQueue.getMemDepViolator(tid); 13641062SN/A 13657720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13667720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13677720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13687720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13697720Sgblack@eecs.umich.edu 13703732Sktlim@umich.edu fetchRedirect[tid] = true; 13713732Sktlim@umich.edu 13721062SN/A // Tell the instruction queue that a violation has occured. 13731062SN/A instQueue.violation(inst, violator); 13741062SN/A 13751062SN/A // Squash. 13768513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13771062SN/A 13781062SN/A ++memOrderViolationEvents; 13792292SN/A } else if (ldstQueue.loadBlocked(tid) && 13802292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13812292SN/A fetchRedirect[tid] = true; 13822292SN/A 13832292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13847720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13857720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13862292SN/A 13872292SN/A squashDueToMemBlocked(inst, tid); 13881062SN/A } 13894033Sktlim@umich.edu } else { 13904033Sktlim@umich.edu // Reset any state associated with redirects that will not 13914033Sktlim@umich.edu // be used. 13924033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13934033Sktlim@umich.edu assert(inst->isMemRef()); 13944033Sktlim@umich.edu 13954033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13964033Sktlim@umich.edu 13974033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13987720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 13997720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14007720Sgblack@eecs.umich.edu inst->physEffAddr); 14014033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14024033Sktlim@umich.edu "already squashing\n"); 14034033Sktlim@umich.edu 14044033Sktlim@umich.edu ++memOrderViolationEvents; 14054033Sktlim@umich.edu } 14064033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14074033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14084033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14097720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14107720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14114033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14124033Sktlim@umich.edu "already squashing\n"); 14134033Sktlim@umich.edu 14144033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14154033Sktlim@umich.edu } 14164033Sktlim@umich.edu 14171062SN/A } 14181062SN/A } 14192292SN/A 14202348SN/A // Update and record activity if we processed any instructions. 14212292SN/A if (inst_num) { 14222292SN/A if (exeStatus == Idle) { 14232292SN/A exeStatus = Running; 14242292SN/A } 14252292SN/A 14262292SN/A updatedQueues = true; 14272292SN/A 14282292SN/A cpu->activityThisCycle(); 14292292SN/A } 14302292SN/A 14312292SN/A // Need to reset this in case a writeback event needs to write into the 14322292SN/A // iew queue. That way the writeback event will write into the correct 14332292SN/A // spot in the queue. 14342292SN/A wbNumInst = 0; 14357852SMatt.Horsnell@arm.com 14362107SN/A} 14372107SN/A 14382292SN/Atemplate <class Impl> 14392107SN/Avoid 14402292SN/ADefaultIEW<Impl>::writebackInsts() 14412107SN/A{ 14422326SN/A // Loop through the head of the time buffer and wake any 14432326SN/A // dependents. These instructions are about to write back. Also 14442326SN/A // mark scoreboard that this instruction is finally complete. 14452326SN/A // Either have IEW have direct access to scoreboard, or have this 14462326SN/A // as part of backwards communication. 14473958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14482292SN/A toCommit->insts[inst_num]; inst_num++) { 14492107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14506221Snate@binkert.org ThreadID tid = inst->threadNumber; 14512107SN/A 14527720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14537720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14542107SN/A 14552301SN/A iewInstsToCommit[tid]++; 14562301SN/A 14572292SN/A // Some instructions will be sent to commit without having 14582292SN/A // executed because they need commit to handle them. 14592292SN/A // E.g. Uncached loads have not actually executed when they 14602292SN/A // are first sent to commit. Instead commit must tell the LSQ 14612292SN/A // when it's ready to execute the uncached load. 14622367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14632301SN/A int dependents = instQueue.wakeDependents(inst); 14642107SN/A 14652292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14662292SN/A //mark as Ready 14672292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14682292SN/A inst->renamedDestRegIdx(i)); 14692292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14702107SN/A } 14712301SN/A 14722348SN/A if (dependents) { 14732348SN/A producerInst[tid]++; 14742348SN/A consumerInst[tid]+= dependents; 14752348SN/A } 14762326SN/A writebackCount[tid]++; 14772107SN/A } 14782107SN/A } 14791060SN/A} 14801060SN/A 14811681SN/Atemplate<class Impl> 14821060SN/Avoid 14832292SN/ADefaultIEW<Impl>::tick() 14841060SN/A{ 14852292SN/A wbNumInst = 0; 14862292SN/A wbCycle = 0; 14871060SN/A 14882292SN/A wroteToTimeBuffer = false; 14892292SN/A updatedQueues = false; 14901060SN/A 14912292SN/A sortInsts(); 14921060SN/A 14932326SN/A // Free function units marked as being freed this cycle. 14942326SN/A fuPool->processFreeUnits(); 14951062SN/A 14966221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 14976221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 14981060SN/A 14992326SN/A // Check stall and squash signals, dispatch any instructions. 15003867Sbinkertn@umich.edu while (threads != end) { 15016221Snate@binkert.org ThreadID tid = *threads++; 15021060SN/A 15032292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15041060SN/A 15052292SN/A checkSignalsAndUpdate(tid); 15062292SN/A dispatch(tid); 15071060SN/A } 15081060SN/A 15092292SN/A if (exeStatus != Squashing) { 15102292SN/A executeInsts(); 15111060SN/A 15122292SN/A writebackInsts(); 15132292SN/A 15142292SN/A // Have the instruction queue try to schedule any ready instructions. 15152292SN/A // (In actuality, this scheduling is for instructions that will 15162292SN/A // be executed next cycle.) 15172292SN/A instQueue.scheduleReadyInsts(); 15182292SN/A 15192292SN/A // Also should advance its own time buffers if the stage ran. 15202292SN/A // Not the best place for it, but this works (hopefully). 15212292SN/A issueToExecQueue.advance(); 15222292SN/A } 15232292SN/A 15242292SN/A bool broadcast_free_entries = false; 15252292SN/A 15262292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15272292SN/A exeStatus = Idle; 15282292SN/A updateLSQNextCycle = false; 15292292SN/A 15302292SN/A broadcast_free_entries = true; 15312292SN/A } 15322292SN/A 15332292SN/A // Writeback any stores using any leftover bandwidth. 15341681SN/A ldstQueue.writebackStores(); 15351681SN/A 15361061SN/A // Check the committed load/store signals to see if there's a load 15371061SN/A // or store to commit. Also check if it's being told to execute a 15381061SN/A // nonspeculative instruction. 15391681SN/A // This is pretty inefficient... 15402292SN/A 15413867Sbinkertn@umich.edu threads = activeThreads->begin(); 15423867Sbinkertn@umich.edu while (threads != end) { 15436221Snate@binkert.org ThreadID tid = (*threads++); 15442292SN/A 15452292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15462292SN/A 15472348SN/A // Update structures based on instructions committed. 15482292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15492292SN/A !fromCommit->commitInfo[tid].squash && 15502292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15512292SN/A 15522292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15532292SN/A 15542292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15552292SN/A 15562292SN/A updateLSQNextCycle = true; 15572292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15582292SN/A } 15592292SN/A 15602292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15612292SN/A 15622292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15632292SN/A if (fromCommit->commitInfo[tid].uncached) { 15642292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15654033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15662292SN/A } else { 15672292SN/A instQueue.scheduleNonSpec( 15682292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15692292SN/A } 15702292SN/A } 15712292SN/A 15722292SN/A if (broadcast_free_entries) { 15732292SN/A toFetch->iewInfo[tid].iqCount = 15742292SN/A instQueue.getCount(tid); 15752292SN/A toFetch->iewInfo[tid].ldstqCount = 15762292SN/A ldstQueue.getCount(tid); 15772292SN/A 15782292SN/A toRename->iewInfo[tid].usedIQ = true; 15792292SN/A toRename->iewInfo[tid].freeIQEntries = 158010164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 15812292SN/A toRename->iewInfo[tid].usedLSQ = true; 158210239Sbinhpham@cs.rutgers.edu 158310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 158410239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 158510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 158610239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 15872292SN/A 15882292SN/A wroteToTimeBuffer = true; 15892292SN/A } 15902292SN/A 15912292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15922292SN/A tid, toRename->iewInfo[tid].dispatched); 15931061SN/A } 15941061SN/A 15952292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 159610239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 15972292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 159810239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 15992292SN/A 16002292SN/A updateStatus(); 16012292SN/A 16022292SN/A if (wroteToTimeBuffer) { 16032292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16042292SN/A cpu->activityThisCycle(); 16051061SN/A } 16061060SN/A} 16071060SN/A 16082301SN/Atemplate <class Impl> 16091060SN/Avoid 16102301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16111060SN/A{ 16126221Snate@binkert.org ThreadID tid = inst->threadNumber; 16131060SN/A 16142669Sktlim@umich.edu iewExecutedInsts++; 16151060SN/A 16168471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16179527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16189527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16199527SMatt.Horsnell@arm.com } 16208471SGiacomo.Gabrielli@arm.com#endif 16218471SGiacomo.Gabrielli@arm.com 16222301SN/A // 16232301SN/A // Control operations 16242301SN/A // 16252301SN/A if (inst->isControl()) 16266221Snate@binkert.org iewExecutedBranches[tid]++; 16271060SN/A 16282301SN/A // 16292301SN/A // Memory operations 16302301SN/A // 16312301SN/A if (inst->isMemRef()) { 16326221Snate@binkert.org iewExecutedRefs[tid]++; 16331060SN/A 16342301SN/A if (inst->isLoad()) { 16356221Snate@binkert.org iewExecLoadInsts[tid]++; 16361060SN/A } 16371060SN/A } 16381060SN/A} 16397598Sminkyu.jeong@arm.com 16407598Sminkyu.jeong@arm.comtemplate <class Impl> 16417598Sminkyu.jeong@arm.comvoid 16427598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16437598Sminkyu.jeong@arm.com{ 16447598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16457598Sminkyu.jeong@arm.com 16467598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16477852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16487598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16497598Sminkyu.jeong@arm.com 16507598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16517598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16527598Sminkyu.jeong@arm.com 16537598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16547598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16557720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16567598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16577720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16587720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16597598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16607598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16617598Sminkyu.jeong@arm.com 16627598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16637598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16647598Sminkyu.jeong@arm.com } else { 16657598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16667598Sminkyu.jeong@arm.com } 16677598Sminkyu.jeong@arm.com } 16687598Sminkyu.jeong@arm.com } 16697598Sminkyu.jeong@arm.com} 16709944Smatt.horsnell@ARM.com 16719944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1672