iew_impl.hh revision 10239
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147598Sminkyu.jeong@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_IEW_IMPL_IMPL_HH__ 469944Smatt.horsnell@ARM.com 471060SN/A// @todo: Fix the instantaneous communication among all the stages within 481060SN/A// iew. There's a clear delay between issue and execute, yet backwards 491689SN/A// communication happens simultaneously. 501060SN/A 511060SN/A#include <queue> 521060SN/A 538230Snate@binkert.org#include "arch/utility.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 562292SN/A#include "cpu/o3/fu_pool.hh" 571717SN/A#include "cpu/o3/iew.hh" 588229Snate@binkert.org#include "cpu/timebuf.hh" 598232Snate@binkert.org#include "debug/Activity.hh" 609444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 618232Snate@binkert.org#include "debug/IEW.hh" 629527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 635529Snate@binkert.org#include "params/DerivO3CPU.hh" 641060SN/A 656221Snate@binkert.orgusing namespace std; 666221Snate@binkert.org 671681SN/Atemplate<class Impl> 685529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 692873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 704329Sktlim@umich.edu cpu(_cpu), 714329Sktlim@umich.edu instQueue(_cpu, this, params), 724329Sktlim@umich.edu ldstQueue(_cpu, this, params), 732292SN/A fuPool(params->fuPool), 742292SN/A commitToIEWDelay(params->commitToIEWDelay), 752292SN/A renameToIEWDelay(params->renameToIEWDelay), 762292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 772820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 782292SN/A issueWidth(params->issueWidth), 792820Sktlim@umich.edu wbOutstanding(0), 802820Sktlim@umich.edu wbWidth(params->wbWidth), 819444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 821060SN/A{ 8310172Sdam.sunwoo@arm.com if (dispatchWidth > Impl::MaxWidth) 8410172Sdam.sunwoo@arm.com fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 8510172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 8610172Sdam.sunwoo@arm.com dispatchWidth, static_cast<int>(Impl::MaxWidth)); 8710172Sdam.sunwoo@arm.com if (issueWidth > Impl::MaxWidth) 8810172Sdam.sunwoo@arm.com fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 8910172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9010172Sdam.sunwoo@arm.com issueWidth, static_cast<int>(Impl::MaxWidth)); 9110172Sdam.sunwoo@arm.com if (wbWidth > Impl::MaxWidth) 9210172Sdam.sunwoo@arm.com fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 9310172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 9410172Sdam.sunwoo@arm.com wbWidth, static_cast<int>(Impl::MaxWidth)); 9510172Sdam.sunwoo@arm.com 962292SN/A _status = Active; 972292SN/A exeStatus = Running; 982292SN/A wbStatus = Idle; 991060SN/A 1001060SN/A // Setup wire to read instructions coming from issue. 1011060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1021060SN/A 1031060SN/A // Instruction queue needs the queue between issue and execute. 1041060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1051681SN/A 1066221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1076221Snate@binkert.org dispatchStatus[tid] = Running; 1086221Snate@binkert.org stalls[tid].commit = false; 1096221Snate@binkert.org fetchRedirect[tid] = false; 1102292SN/A } 1112292SN/A 1122820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 1132820Sktlim@umich.edu 1142292SN/A updateLSQNextCycle = false; 1152292SN/A 1162820Sktlim@umich.edu ableToIssue = true; 1172820Sktlim@umich.edu 1182292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1192292SN/A} 1202292SN/A 1212292SN/Atemplate <class Impl> 1222292SN/Astd::string 1232292SN/ADefaultIEW<Impl>::name() const 1242292SN/A{ 1252292SN/A return cpu->name() + ".iew"; 1261060SN/A} 1271060SN/A 1281681SN/Atemplate <class Impl> 1291062SN/Avoid 13010023Smatt.horsnell@ARM.comDefaultIEW<Impl>::regProbePoints() 13110023Smatt.horsnell@ARM.com{ 13210023Smatt.horsnell@ARM.com ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 13310023Smatt.horsnell@ARM.com ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 13410023Smatt.horsnell@ARM.com} 13510023Smatt.horsnell@ARM.com 13610023Smatt.horsnell@ARM.comtemplate <class Impl> 13710023Smatt.horsnell@ARM.comvoid 1382292SN/ADefaultIEW<Impl>::regStats() 1391062SN/A{ 1402301SN/A using namespace Stats; 1412301SN/A 1421062SN/A instQueue.regStats(); 1432727Sktlim@umich.edu ldstQueue.regStats(); 1441062SN/A 1451062SN/A iewIdleCycles 1461062SN/A .name(name() + ".iewIdleCycles") 1471062SN/A .desc("Number of cycles IEW is idle"); 1481062SN/A 1491062SN/A iewSquashCycles 1501062SN/A .name(name() + ".iewSquashCycles") 1511062SN/A .desc("Number of cycles IEW is squashing"); 1521062SN/A 1531062SN/A iewBlockCycles 1541062SN/A .name(name() + ".iewBlockCycles") 1551062SN/A .desc("Number of cycles IEW is blocking"); 1561062SN/A 1571062SN/A iewUnblockCycles 1581062SN/A .name(name() + ".iewUnblockCycles") 1591062SN/A .desc("Number of cycles IEW is unblocking"); 1601062SN/A 1611062SN/A iewDispatchedInsts 1621062SN/A .name(name() + ".iewDispatchedInsts") 1631062SN/A .desc("Number of instructions dispatched to IQ"); 1641062SN/A 1651062SN/A iewDispSquashedInsts 1661062SN/A .name(name() + ".iewDispSquashedInsts") 1671062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1681062SN/A 1691062SN/A iewDispLoadInsts 1701062SN/A .name(name() + ".iewDispLoadInsts") 1711062SN/A .desc("Number of dispatched load instructions"); 1721062SN/A 1731062SN/A iewDispStoreInsts 1741062SN/A .name(name() + ".iewDispStoreInsts") 1751062SN/A .desc("Number of dispatched store instructions"); 1761062SN/A 1771062SN/A iewDispNonSpecInsts 1781062SN/A .name(name() + ".iewDispNonSpecInsts") 1791062SN/A .desc("Number of dispatched non-speculative instructions"); 1801062SN/A 1811062SN/A iewIQFullEvents 1821062SN/A .name(name() + ".iewIQFullEvents") 1831062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1841062SN/A 1852292SN/A iewLSQFullEvents 1862292SN/A .name(name() + ".iewLSQFullEvents") 1872292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1882292SN/A 1891062SN/A memOrderViolationEvents 1901062SN/A .name(name() + ".memOrderViolationEvents") 1911062SN/A .desc("Number of memory order violations"); 1921062SN/A 1931062SN/A predictedTakenIncorrect 1941062SN/A .name(name() + ".predictedTakenIncorrect") 1951062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1962292SN/A 1972292SN/A predictedNotTakenIncorrect 1982292SN/A .name(name() + ".predictedNotTakenIncorrect") 1992292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2002292SN/A 2012292SN/A branchMispredicts 2022292SN/A .name(name() + ".branchMispredicts") 2032292SN/A .desc("Number of branch mispredicts detected at execute"); 2042292SN/A 2052292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2062301SN/A 2072727Sktlim@umich.edu iewExecutedInsts 2082353SN/A .name(name() + ".iewExecutedInsts") 2092727Sktlim@umich.edu .desc("Number of executed instructions"); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu iewExecLoadInsts 2126221Snate@binkert.org .init(cpu->numThreads) 2132353SN/A .name(name() + ".iewExecLoadInsts") 2142727Sktlim@umich.edu .desc("Number of load instructions executed") 2152727Sktlim@umich.edu .flags(total); 2162727Sktlim@umich.edu 2172727Sktlim@umich.edu iewExecSquashedInsts 2182353SN/A .name(name() + ".iewExecSquashedInsts") 2192727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2202727Sktlim@umich.edu 2212727Sktlim@umich.edu iewExecutedSwp 2226221Snate@binkert.org .init(cpu->numThreads) 2238240Snate@binkert.org .name(name() + ".exec_swp") 2242301SN/A .desc("number of swp insts executed") 2252727Sktlim@umich.edu .flags(total); 2262301SN/A 2272727Sktlim@umich.edu iewExecutedNop 2286221Snate@binkert.org .init(cpu->numThreads) 2298240Snate@binkert.org .name(name() + ".exec_nop") 2302301SN/A .desc("number of nop insts executed") 2312727Sktlim@umich.edu .flags(total); 2322301SN/A 2332727Sktlim@umich.edu iewExecutedRefs 2346221Snate@binkert.org .init(cpu->numThreads) 2358240Snate@binkert.org .name(name() + ".exec_refs") 2362301SN/A .desc("number of memory reference insts executed") 2372727Sktlim@umich.edu .flags(total); 2382301SN/A 2392727Sktlim@umich.edu iewExecutedBranches 2406221Snate@binkert.org .init(cpu->numThreads) 2418240Snate@binkert.org .name(name() + ".exec_branches") 2422301SN/A .desc("Number of branches executed") 2432727Sktlim@umich.edu .flags(total); 2442301SN/A 2452301SN/A iewExecStoreInsts 2468240Snate@binkert.org .name(name() + ".exec_stores") 2472301SN/A .desc("Number of stores executed") 2482727Sktlim@umich.edu .flags(total); 2492727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2502727Sktlim@umich.edu 2512727Sktlim@umich.edu iewExecRate 2528240Snate@binkert.org .name(name() + ".exec_rate") 2532727Sktlim@umich.edu .desc("Inst execution rate") 2542727Sktlim@umich.edu .flags(total); 2552727Sktlim@umich.edu 2562727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2572301SN/A 2582301SN/A iewInstsToCommit 2596221Snate@binkert.org .init(cpu->numThreads) 2608240Snate@binkert.org .name(name() + ".wb_sent") 2612301SN/A .desc("cumulative count of insts sent to commit") 2622727Sktlim@umich.edu .flags(total); 2632301SN/A 2642326SN/A writebackCount 2656221Snate@binkert.org .init(cpu->numThreads) 2668240Snate@binkert.org .name(name() + ".wb_count") 2672301SN/A .desc("cumulative count of insts written-back") 2682727Sktlim@umich.edu .flags(total); 2692301SN/A 2702326SN/A producerInst 2716221Snate@binkert.org .init(cpu->numThreads) 2728240Snate@binkert.org .name(name() + ".wb_producers") 2732301SN/A .desc("num instructions producing a value") 2742727Sktlim@umich.edu .flags(total); 2752301SN/A 2762326SN/A consumerInst 2776221Snate@binkert.org .init(cpu->numThreads) 2788240Snate@binkert.org .name(name() + ".wb_consumers") 2792301SN/A .desc("num instructions consuming a value") 2802727Sktlim@umich.edu .flags(total); 2812301SN/A 2822326SN/A wbPenalized 2836221Snate@binkert.org .init(cpu->numThreads) 2848240Snate@binkert.org .name(name() + ".wb_penalized") 2852301SN/A .desc("number of instrctions required to write to 'other' IQ") 2862727Sktlim@umich.edu .flags(total); 2872301SN/A 2882326SN/A wbPenalizedRate 2898240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2902301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2912727Sktlim@umich.edu .flags(total); 2922301SN/A 2932326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2942301SN/A 2952326SN/A wbFanout 2968240Snate@binkert.org .name(name() + ".wb_fanout") 2972301SN/A .desc("average fanout of values written-back") 2982727Sktlim@umich.edu .flags(total); 2992301SN/A 3002326SN/A wbFanout = producerInst / consumerInst; 3012301SN/A 3022326SN/A wbRate 3038240Snate@binkert.org .name(name() + ".wb_rate") 3042301SN/A .desc("insts written-back per cycle") 3052727Sktlim@umich.edu .flags(total); 3062326SN/A wbRate = writebackCount / cpu->numCycles; 3071062SN/A} 3081062SN/A 3091681SN/Atemplate<class Impl> 3101060SN/Avoid 3119427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 3121060SN/A{ 3136221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3142292SN/A toRename->iewInfo[tid].usedIQ = true; 3152292SN/A toRename->iewInfo[tid].freeIQEntries = 3162292SN/A instQueue.numFreeEntries(tid); 3172292SN/A 3182292SN/A toRename->iewInfo[tid].usedLSQ = true; 31910239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid); 32010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid); 3212292SN/A } 3222292SN/A 3238887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 3248733Sgeoffrey.blake@arm.com if (cpu->checker) { 3258850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3268887Sgeoffrey.blake@arm.com } 3278733Sgeoffrey.blake@arm.com 3282733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3291060SN/A} 3301060SN/A 3311681SN/Atemplate<class Impl> 3321060SN/Avoid 3332292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3341060SN/A{ 3351060SN/A timeBuffer = tb_ptr; 3361060SN/A 3371060SN/A // Setup wire to read information from time buffer, from commit. 3381060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3391060SN/A 3401060SN/A // Setup wire to write information back to previous stages. 3411060SN/A toRename = timeBuffer->getWire(0); 3421060SN/A 3432292SN/A toFetch = timeBuffer->getWire(0); 3442292SN/A 3451060SN/A // Instruction queue also needs main time buffer. 3461060SN/A instQueue.setTimeBuffer(tb_ptr); 3471060SN/A} 3481060SN/A 3491681SN/Atemplate<class Impl> 3501060SN/Avoid 3512292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3521060SN/A{ 3531060SN/A renameQueue = rq_ptr; 3541060SN/A 3551060SN/A // Setup wire to read information from rename queue. 3561060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3571060SN/A} 3581060SN/A 3591681SN/Atemplate<class Impl> 3601060SN/Avoid 3612292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3621060SN/A{ 3631060SN/A iewQueue = iq_ptr; 3641060SN/A 3651060SN/A // Setup wire to write instructions to commit. 3661060SN/A toCommit = iewQueue->getWire(0); 3671060SN/A} 3681060SN/A 3691681SN/Atemplate<class Impl> 3701060SN/Avoid 3716221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3721060SN/A{ 3732292SN/A activeThreads = at_ptr; 3742292SN/A 3752292SN/A ldstQueue.setActiveThreads(at_ptr); 3762292SN/A instQueue.setActiveThreads(at_ptr); 3771060SN/A} 3781060SN/A 3791681SN/Atemplate<class Impl> 3801060SN/Avoid 3812292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3821060SN/A{ 3832292SN/A scoreboard = sb_ptr; 3841060SN/A} 3851060SN/A 3862307SN/Atemplate <class Impl> 3872863Sktlim@umich.edubool 3889444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3892307SN/A{ 3909444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3919444SAndreas.Sandberg@ARM.com 3929444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3939444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3949444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3959444SAndreas.Sandberg@ARM.com drained = false; 3969444SAndreas.Sandberg@ARM.com } 3979444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3989444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3999444SAndreas.Sandberg@ARM.com drained = false; 4009444SAndreas.Sandberg@ARM.com } 4019444SAndreas.Sandberg@ARM.com } 4029444SAndreas.Sandberg@ARM.com 4039783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 4049783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 4059783Sandreas.hansson@arm.com // above 4069783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 4079783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 4089783Sandreas.hansson@arm.com drained = false; 4099783Sandreas.hansson@arm.com } 4109783Sandreas.hansson@arm.com 4119444SAndreas.Sandberg@ARM.com return drained; 4121681SN/A} 4131681SN/A 4142316SN/Atemplate <class Impl> 4151681SN/Avoid 4169444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 4172843Sktlim@umich.edu{ 4189444SAndreas.Sandberg@ARM.com assert(isDrained()); 4192843Sktlim@umich.edu 4209444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 4219444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 4221681SN/A} 4231681SN/A 4242307SN/Atemplate <class Impl> 4251681SN/Avoid 4262307SN/ADefaultIEW<Impl>::takeOverFrom() 4271060SN/A{ 4282348SN/A // Reset all state. 4292307SN/A _status = Active; 4302307SN/A exeStatus = Running; 4312307SN/A wbStatus = Idle; 4321060SN/A 4332307SN/A instQueue.takeOverFrom(); 4342307SN/A ldstQueue.takeOverFrom(); 4359444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4361060SN/A 4379427SAndreas.Sandberg@ARM.com startupStage(); 4382307SN/A cpu->activityThisCycle(); 4391060SN/A 4406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4416221Snate@binkert.org dispatchStatus[tid] = Running; 4426221Snate@binkert.org stalls[tid].commit = false; 4436221Snate@binkert.org fetchRedirect[tid] = false; 4442307SN/A } 4451060SN/A 4462307SN/A updateLSQNextCycle = false; 4472307SN/A 4482873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4492307SN/A issueToExecQueue.advance(); 4501060SN/A } 4511060SN/A} 4521060SN/A 4531681SN/Atemplate<class Impl> 4541060SN/Avoid 4556221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4562107SN/A{ 4576221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4582107SN/A 4592292SN/A // Tell the IQ to start squashing. 4602292SN/A instQueue.squash(tid); 4612107SN/A 4622292SN/A // Tell the LDSTQ to start squashing. 4632326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4642292SN/A updatedQueues = true; 4652107SN/A 4662292SN/A // Clear the skid buffer in case it has any data in it. 4672935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4684632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4692935Sksewell@umich.edu 4702292SN/A while (!skidBuffer[tid].empty()) { 47110239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isLoad()) { 47210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 47310239Sbinhpham@cs.rutgers.edu } 47410239Sbinhpham@cs.rutgers.edu if (skidBuffer[tid].front()->isStore()) { 47510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 4762292SN/A } 4772107SN/A 4782292SN/A toRename->iewInfo[tid].dispatched++; 4792107SN/A 4802292SN/A skidBuffer[tid].pop(); 4812292SN/A } 4822107SN/A 4832702Sktlim@umich.edu emptyRenameInsts(tid); 4842107SN/A} 4852107SN/A 4862107SN/Atemplate<class Impl> 4872107SN/Avoid 4886221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4892292SN/A{ 4907720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4917720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4922292SN/A 49310231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 4947852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4957852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4967852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4977852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4982935Sksewell@umich.edu 4997852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 5007852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 5012292SN/A 5027852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 5037852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 5047852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5052292SN/A 5067852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5077852SMatt.Horsnell@arm.com } 5087852SMatt.Horsnell@arm.com 5092292SN/A} 5102292SN/A 5112292SN/Atemplate<class Impl> 5122292SN/Avoid 5136221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5142292SN/A{ 5158513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5168513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5178513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 5188513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 5198513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 5208513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 5218513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 5228513SGiacomo.Gabrielli@arm.com // the squash. 52310231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5248513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5258513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 5262292SN/A 5277852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5288513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5298137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5302292SN/A 5318513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5328513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5332292SN/A 5347852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5357852SMatt.Horsnell@arm.com } 5362292SN/A} 5372292SN/A 5382292SN/Atemplate<class Impl> 5392292SN/Avoid 5406221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5412292SN/A{ 5422292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5437720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 54410231Ssteve.reinhardt@amd.com if (!toCommit->squash[tid] || 5457852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5467852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5472292SN/A 5487852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5497852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5508137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5512292SN/A 5527852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5537852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5542292SN/A 5557852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5562292SN/A 5577852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5587852SMatt.Horsnell@arm.com } 5592292SN/A} 5602292SN/A 5612292SN/Atemplate<class Impl> 5622292SN/Avoid 5636221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5642292SN/A{ 5652292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5662292SN/A 5672292SN/A if (dispatchStatus[tid] != Blocked && 5682292SN/A dispatchStatus[tid] != Unblocking) { 5692292SN/A toRename->iewBlock[tid] = true; 5702292SN/A wroteToTimeBuffer = true; 5712292SN/A } 5722292SN/A 5732292SN/A // Add the current inputs to the skid buffer so they can be 5742292SN/A // reprocessed when this stage unblocks. 5752292SN/A skidInsert(tid); 5762292SN/A 5772292SN/A dispatchStatus[tid] = Blocked; 5782292SN/A} 5792292SN/A 5802292SN/Atemplate<class Impl> 5812292SN/Avoid 5826221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5832292SN/A{ 5842292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5852292SN/A "buffer %u.\n",tid, tid); 5862292SN/A 5872292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5882292SN/A // Also switch status to running. 5892292SN/A if (skidBuffer[tid].empty()) { 5902292SN/A toRename->iewUnblock[tid] = true; 5912292SN/A wroteToTimeBuffer = true; 5922292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5932292SN/A dispatchStatus[tid] = Running; 5942292SN/A } 5952292SN/A} 5962292SN/A 5972292SN/Atemplate<class Impl> 5982292SN/Avoid 5992292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 6001060SN/A{ 6011681SN/A instQueue.wakeDependents(inst); 6021060SN/A} 6031060SN/A 6042292SN/Atemplate<class Impl> 6052292SN/Avoid 6062292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6072292SN/A{ 6082292SN/A instQueue.rescheduleMemInst(inst); 6092292SN/A} 6101681SN/A 6111681SN/Atemplate<class Impl> 6121060SN/Avoid 6132292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6141060SN/A{ 6152292SN/A instQueue.replayMemInst(inst); 6162292SN/A} 6171060SN/A 6182292SN/Atemplate<class Impl> 6192292SN/Avoid 6202292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6212292SN/A{ 6223221Sktlim@umich.edu // This function should not be called after writebackInsts in a 6233221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 6243221Sktlim@umich.edu // being added to the queue to commit without being processed by 6253221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 6263221Sktlim@umich.edu 6272292SN/A // First check the time slot that this instruction will write 6282292SN/A // to. If there are free write ports at the time, then go ahead 6292292SN/A // and write the instruction to that time. If there are not, 6302292SN/A // keep looking back to see where's the first time there's a 6312326SN/A // free slot. 6322292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6332292SN/A ++wbNumInst; 6342820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6352292SN/A ++wbCycle; 6362292SN/A wbNumInst = 0; 6372292SN/A } 6382292SN/A 6392353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6402292SN/A } 6412292SN/A 6422353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6432353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6442292SN/A // Add finished instruction to queue to commit. 6452292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6462292SN/A (*iewQueue)[wbCycle].size++; 6472292SN/A} 6482292SN/A 6492292SN/Atemplate <class Impl> 6502292SN/Aunsigned 6512292SN/ADefaultIEW<Impl>::validInstsFromRename() 6522292SN/A{ 6532292SN/A unsigned inst_count = 0; 6542292SN/A 6552292SN/A for (int i=0; i<fromRename->size; i++) { 6562731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6572292SN/A inst_count++; 6582292SN/A } 6592292SN/A 6602292SN/A return inst_count; 6612292SN/A} 6622292SN/A 6632292SN/Atemplate<class Impl> 6642292SN/Avoid 6656221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6662292SN/A{ 6672292SN/A DynInstPtr inst = NULL; 6682292SN/A 6692292SN/A while (!insts[tid].empty()) { 6702292SN/A inst = insts[tid].front(); 6712292SN/A 6722292SN/A insts[tid].pop(); 6732292SN/A 6749937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6752292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6767720Sgblack@eecs.umich.edu inst->pcState(),tid); 6772292SN/A 6782292SN/A skidBuffer[tid].push(inst); 6792292SN/A } 6802292SN/A 6812292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6822292SN/A "Skidbuffer Exceeded Max Size"); 6832292SN/A} 6842292SN/A 6852292SN/Atemplate<class Impl> 6862292SN/Aint 6872292SN/ADefaultIEW<Impl>::skidCount() 6882292SN/A{ 6892292SN/A int max=0; 6902292SN/A 6916221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6926221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6932292SN/A 6943867Sbinkertn@umich.edu while (threads != end) { 6956221Snate@binkert.org ThreadID tid = *threads++; 6963867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6972292SN/A if (max < thread_count) 6982292SN/A max = thread_count; 6992292SN/A } 7002292SN/A 7012292SN/A return max; 7022292SN/A} 7032292SN/A 7042292SN/Atemplate<class Impl> 7052292SN/Abool 7062292SN/ADefaultIEW<Impl>::skidsEmpty() 7072292SN/A{ 7086221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7096221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7102292SN/A 7113867Sbinkertn@umich.edu while (threads != end) { 7126221Snate@binkert.org ThreadID tid = *threads++; 7133867Sbinkertn@umich.edu 7143867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7152292SN/A return false; 7162292SN/A } 7172292SN/A 7182292SN/A return true; 7191062SN/A} 7201062SN/A 7211681SN/Atemplate <class Impl> 7221062SN/Avoid 7232292SN/ADefaultIEW<Impl>::updateStatus() 7241062SN/A{ 7252292SN/A bool any_unblocking = false; 7261062SN/A 7276221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7286221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7291062SN/A 7303867Sbinkertn@umich.edu while (threads != end) { 7316221Snate@binkert.org ThreadID tid = *threads++; 7321062SN/A 7332292SN/A if (dispatchStatus[tid] == Unblocking) { 7342292SN/A any_unblocking = true; 7352292SN/A break; 7362292SN/A } 7372292SN/A } 7381062SN/A 7392292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7402292SN/A // and there's no stores waiting to write back, and dispatch is not 7412292SN/A // unblocking, then there is no internal activity for the IEW stage. 7427897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7432292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7442292SN/A !ldstQueue.willWB() && !any_unblocking) { 7452292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7461062SN/A 7472292SN/A deactivateStage(); 7481062SN/A 7492292SN/A _status = Inactive; 7502292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7512292SN/A ldstQueue.willWB() || 7522292SN/A any_unblocking)) { 7532292SN/A // Otherwise there is internal activity. Set to active. 7542292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7551062SN/A 7562292SN/A activateStage(); 7571062SN/A 7582292SN/A _status = Active; 7591062SN/A } 7601062SN/A} 7611062SN/A 7621681SN/Atemplate <class Impl> 7631062SN/Avoid 7642292SN/ADefaultIEW<Impl>::resetEntries() 7651062SN/A{ 7662292SN/A instQueue.resetEntries(); 7672292SN/A ldstQueue.resetEntries(); 7682292SN/A} 7691062SN/A 7702292SN/Atemplate <class Impl> 7712292SN/Avoid 7726221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7732292SN/A{ 7742292SN/A if (fromCommit->commitBlock[tid]) { 7752292SN/A stalls[tid].commit = true; 7762292SN/A } 7771062SN/A 7782292SN/A if (fromCommit->commitUnblock[tid]) { 7792292SN/A assert(stalls[tid].commit); 7802292SN/A stalls[tid].commit = false; 7812292SN/A } 7822292SN/A} 7832292SN/A 7842292SN/Atemplate <class Impl> 7852292SN/Abool 7866221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7872292SN/A{ 7882292SN/A bool ret_val(false); 7892292SN/A 7902292SN/A if (stalls[tid].commit) { 7912292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7922292SN/A ret_val = true; 7932292SN/A } else if (instQueue.isFull(tid)) { 7942292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7952292SN/A ret_val = true; 7962292SN/A } else if (ldstQueue.isFull(tid)) { 7972292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7982292SN/A 7992292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 8002292SN/A 8012292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 8022292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8032292SN/A } 8042292SN/A 8052292SN/A if (ldstQueue.numStores(tid) > 0) { 8062292SN/A 8072292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8082292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8092292SN/A } 8102292SN/A 8112292SN/A ret_val = true; 8122292SN/A } else if (ldstQueue.isStalled(tid)) { 8132292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8142292SN/A ret_val = true; 8152292SN/A } 8162292SN/A 8172292SN/A return ret_val; 8182292SN/A} 8192292SN/A 8202292SN/Atemplate <class Impl> 8212292SN/Avoid 8226221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 8232292SN/A{ 8242292SN/A // Check if there's a squash signal, squash if there is 8252292SN/A // Check stall signals, block if there is. 8262292SN/A // If status was Blocked 8272292SN/A // if so then go to unblocking 8282292SN/A // If status was Squashing 8292292SN/A // check if squashing is not high. Switch to running this cycle. 8302292SN/A 8312292SN/A readStallSignals(tid); 8322292SN/A 8332292SN/A if (fromCommit->commitInfo[tid].squash) { 8342292SN/A squash(tid); 8352292SN/A 8362292SN/A if (dispatchStatus[tid] == Blocked || 8372292SN/A dispatchStatus[tid] == Unblocking) { 8382292SN/A toRename->iewUnblock[tid] = true; 8392292SN/A wroteToTimeBuffer = true; 8402292SN/A } 8412292SN/A 8422292SN/A dispatchStatus[tid] = Squashing; 8432292SN/A fetchRedirect[tid] = false; 8442292SN/A return; 8452292SN/A } 8462292SN/A 8472292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8482702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8492292SN/A 8502292SN/A dispatchStatus[tid] = Squashing; 8512702Sktlim@umich.edu emptyRenameInsts(tid); 8522702Sktlim@umich.edu wroteToTimeBuffer = true; 8532292SN/A return; 8542292SN/A } 8552292SN/A 8562292SN/A if (checkStall(tid)) { 8572292SN/A block(tid); 8582292SN/A dispatchStatus[tid] = Blocked; 8592292SN/A return; 8602292SN/A } 8612292SN/A 8622292SN/A if (dispatchStatus[tid] == Blocked) { 8632292SN/A // Status from previous cycle was blocked, but there are no more stall 8642292SN/A // conditions. Switch over to unblocking. 8652292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8662292SN/A tid); 8672292SN/A 8682292SN/A dispatchStatus[tid] = Unblocking; 8692292SN/A 8702292SN/A unblock(tid); 8712292SN/A 8722292SN/A return; 8732292SN/A } 8742292SN/A 8752292SN/A if (dispatchStatus[tid] == Squashing) { 8762292SN/A // Switch status to running if rename isn't being told to block or 8772292SN/A // squash this cycle. 8782292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8792292SN/A tid); 8802292SN/A 8812292SN/A dispatchStatus[tid] = Running; 8822292SN/A 8832292SN/A return; 8842292SN/A } 8852292SN/A} 8862292SN/A 8872292SN/Atemplate <class Impl> 8882292SN/Avoid 8892292SN/ADefaultIEW<Impl>::sortInsts() 8902292SN/A{ 8912292SN/A int insts_from_rename = fromRename->size; 8922326SN/A#ifdef DEBUG 8936221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8946221Snate@binkert.org assert(insts[tid].empty()); 8952326SN/A#endif 8962292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8972292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8982292SN/A } 8992292SN/A} 9002292SN/A 9012292SN/Atemplate <class Impl> 9022292SN/Avoid 9036221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 9042702Sktlim@umich.edu{ 9054632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 9062935Sksewell@umich.edu 9072702Sktlim@umich.edu while (!insts[tid].empty()) { 9082935Sksewell@umich.edu 90910239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isLoad()) { 91010239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 91110239Sbinhpham@cs.rutgers.edu } 91210239Sbinhpham@cs.rutgers.edu if (insts[tid].front()->isStore()) { 91310239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 9142702Sktlim@umich.edu } 9152702Sktlim@umich.edu 9162702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 9172702Sktlim@umich.edu 9182702Sktlim@umich.edu insts[tid].pop(); 9192702Sktlim@umich.edu } 9202702Sktlim@umich.edu} 9212702Sktlim@umich.edu 9222702Sktlim@umich.edutemplate <class Impl> 9232702Sktlim@umich.eduvoid 9242292SN/ADefaultIEW<Impl>::wakeCPU() 9252292SN/A{ 9262292SN/A cpu->wakeCPU(); 9272292SN/A} 9282292SN/A 9292292SN/Atemplate <class Impl> 9302292SN/Avoid 9312292SN/ADefaultIEW<Impl>::activityThisCycle() 9322292SN/A{ 9332292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9342292SN/A cpu->activityThisCycle(); 9352292SN/A} 9362292SN/A 9372292SN/Atemplate <class Impl> 9382292SN/Ainline void 9392292SN/ADefaultIEW<Impl>::activateStage() 9402292SN/A{ 9412292SN/A DPRINTF(Activity, "Activating stage.\n"); 9422733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9432292SN/A} 9442292SN/A 9452292SN/Atemplate <class Impl> 9462292SN/Ainline void 9472292SN/ADefaultIEW<Impl>::deactivateStage() 9482292SN/A{ 9492292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9502733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9512292SN/A} 9522292SN/A 9532292SN/Atemplate<class Impl> 9542292SN/Avoid 9556221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9562292SN/A{ 9572292SN/A // If status is Running or idle, 9582292SN/A // call dispatchInsts() 9592292SN/A // If status is Unblocking, 9602292SN/A // buffer any instructions coming from rename 9612292SN/A // continue trying to empty skid buffer 9622292SN/A // check if stall conditions have passed 9632292SN/A 9642292SN/A if (dispatchStatus[tid] == Blocked) { 9652292SN/A ++iewBlockCycles; 9662292SN/A 9672292SN/A } else if (dispatchStatus[tid] == Squashing) { 9682292SN/A ++iewSquashCycles; 9692292SN/A } 9702292SN/A 9712292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9722292SN/A // will allow, as long as it is not currently blocked. 9732292SN/A if (dispatchStatus[tid] == Running || 9742292SN/A dispatchStatus[tid] == Idle) { 9752292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9762292SN/A "dispatch.\n", tid); 9772292SN/A 9782292SN/A dispatchInsts(tid); 9792292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9802292SN/A // Make sure that the skid buffer has something in it if the 9812292SN/A // status is unblocking. 9822292SN/A assert(!skidsEmpty()); 9832292SN/A 9842292SN/A // If the status was unblocking, then instructions from the skid 9852292SN/A // buffer were used. Remove those instructions and handle 9862292SN/A // the rest of unblocking. 9872292SN/A dispatchInsts(tid); 9882292SN/A 9892292SN/A ++iewUnblockCycles; 9902292SN/A 9915215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9922292SN/A // Add the current inputs to the skid buffer so they can be 9932292SN/A // reprocessed when this stage unblocks. 9942292SN/A skidInsert(tid); 9952292SN/A } 9962292SN/A 9972292SN/A unblock(tid); 9982292SN/A } 9992292SN/A} 10002292SN/A 10012292SN/Atemplate <class Impl> 10022292SN/Avoid 10036221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 10042292SN/A{ 10052292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10062292SN/A // otherwise. 10072292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10082292SN/A dispatchStatus[tid] == Unblocking ? 10092292SN/A skidBuffer[tid] : insts[tid]; 10102292SN/A 10112292SN/A int insts_to_add = insts_to_dispatch.size(); 10122292SN/A 10132292SN/A DynInstPtr inst; 10142292SN/A bool add_to_iq = false; 10152292SN/A int dis_num_inst = 0; 10162292SN/A 10172292SN/A // Loop through the instructions, putting them in the instruction 10182292SN/A // queue. 10192292SN/A for ( ; dis_num_inst < insts_to_add && 10202820Sktlim@umich.edu dis_num_inst < dispatchWidth; 10212292SN/A ++dis_num_inst) 10222292SN/A { 10232292SN/A inst = insts_to_dispatch.front(); 10242292SN/A 10252292SN/A if (dispatchStatus[tid] == Unblocking) { 10262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10272292SN/A "buffer\n", tid); 10282292SN/A } 10292292SN/A 10302292SN/A // Make sure there's a valid instruction there. 10312292SN/A assert(inst); 10322292SN/A 10337720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10342292SN/A "IQ.\n", 10357720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10362292SN/A 10372292SN/A // Be sure to mark these instructions as ready so that the 10382292SN/A // commit stage can go ahead and execute them, and mark 10392292SN/A // them as issued so the IQ doesn't reprocess them. 10402292SN/A 10412292SN/A // Check for squashed instructions. 10422292SN/A if (inst->isSquashed()) { 10432292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10442292SN/A "not adding to IQ.\n", tid); 10452292SN/A 10462292SN/A ++iewDispSquashedInsts; 10472292SN/A 10482292SN/A insts_to_dispatch.pop(); 10492292SN/A 10502292SN/A //Tell Rename That An Instruction has been processed 105110239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 105210239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 10532292SN/A } 105410239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 105510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 105610239Sbinhpham@cs.rutgers.edu } 105710239Sbinhpham@cs.rutgers.edu 10582292SN/A toRename->iewInfo[tid].dispatched++; 10592292SN/A 10602292SN/A continue; 10612292SN/A } 10622292SN/A 10632292SN/A // Check for full conditions. 10642292SN/A if (instQueue.isFull(tid)) { 10652292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10662292SN/A 10672292SN/A // Call function to start blocking. 10682292SN/A block(tid); 10692292SN/A 10702292SN/A // Set unblock to false. Special case where we are using 10712292SN/A // skidbuffer (unblocking) instructions but then we still 10722292SN/A // get full in the IQ. 10732292SN/A toRename->iewUnblock[tid] = false; 10742292SN/A 10752292SN/A ++iewIQFullEvents; 10762292SN/A break; 10772292SN/A } else if (ldstQueue.isFull(tid)) { 10782292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10792292SN/A 10802292SN/A // Call function to start blocking. 10812292SN/A block(tid); 10822292SN/A 10832292SN/A // Set unblock to false. Special case where we are using 10842292SN/A // skidbuffer (unblocking) instructions but then we still 10852292SN/A // get full in the IQ. 10862292SN/A toRename->iewUnblock[tid] = false; 10872292SN/A 10882292SN/A ++iewLSQFullEvents; 10892292SN/A break; 10902292SN/A } 10912292SN/A 10922292SN/A // Otherwise issue the instruction just fine. 10932292SN/A if (inst->isLoad()) { 10942292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10952292SN/A "encountered, adding to LSQ.\n", tid); 10962292SN/A 10972292SN/A // Reserve a spot in the load store queue for this 10982292SN/A // memory access. 10992292SN/A ldstQueue.insertLoad(inst); 11002292SN/A 11012292SN/A ++iewDispLoadInsts; 11022292SN/A 11032292SN/A add_to_iq = true; 11042292SN/A 110510239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToLQ++; 11062292SN/A } else if (inst->isStore()) { 11072292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 11082292SN/A "encountered, adding to LSQ.\n", tid); 11092292SN/A 11102292SN/A ldstQueue.insertStore(inst); 11112292SN/A 11122292SN/A ++iewDispStoreInsts; 11132292SN/A 11142336SN/A if (inst->isStoreConditional()) { 11152336SN/A // Store conditionals need to be set as "canCommit()" 11162336SN/A // so that commit can process them when they reach the 11172336SN/A // head of commit. 11182348SN/A // @todo: This is somewhat specific to Alpha. 11192292SN/A inst->setCanCommit(); 11202292SN/A instQueue.insertNonSpec(inst); 11212292SN/A add_to_iq = false; 11222292SN/A 11232292SN/A ++iewDispNonSpecInsts; 11242292SN/A } else { 11252292SN/A add_to_iq = true; 11262292SN/A } 11272292SN/A 112810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].dispatchedToSQ++; 11292292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11302326SN/A // Same as non-speculative stores. 11312292SN/A inst->setCanCommit(); 11322292SN/A instQueue.insertBarrier(inst); 11332292SN/A add_to_iq = false; 11342292SN/A } else if (inst->isNop()) { 11352292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11362292SN/A "skipping.\n", tid); 11372292SN/A 11382292SN/A inst->setIssued(); 11392292SN/A inst->setExecuted(); 11402292SN/A inst->setCanCommit(); 11412292SN/A 11422326SN/A instQueue.recordProducer(inst); 11432292SN/A 11442727Sktlim@umich.edu iewExecutedNop[tid]++; 11452301SN/A 11462292SN/A add_to_iq = false; 11472292SN/A } else if (inst->isExecuted()) { 11482292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11492292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11502292SN/A "skipping.\n"); 11512292SN/A 11522292SN/A inst->setIssued(); 11532292SN/A inst->setCanCommit(); 11542292SN/A 11552326SN/A instQueue.recordProducer(inst); 11562292SN/A 11572292SN/A add_to_iq = false; 11582292SN/A } else { 11592292SN/A add_to_iq = true; 11602292SN/A } 11614033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11624033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11634033Sktlim@umich.edu "encountered, skipping.\n", tid); 11644033Sktlim@umich.edu 11654033Sktlim@umich.edu // Same as non-speculative stores. 11664033Sktlim@umich.edu inst->setCanCommit(); 11674033Sktlim@umich.edu 11684033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11694033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11704033Sktlim@umich.edu 11714033Sktlim@umich.edu ++iewDispNonSpecInsts; 11724033Sktlim@umich.edu 11734033Sktlim@umich.edu add_to_iq = false; 11744033Sktlim@umich.edu } 11752292SN/A 11762292SN/A // If the instruction queue is not full, then add the 11772292SN/A // instruction. 11782292SN/A if (add_to_iq) { 11792292SN/A instQueue.insert(inst); 11802292SN/A } 11812292SN/A 11822292SN/A insts_to_dispatch.pop(); 11832292SN/A 11842292SN/A toRename->iewInfo[tid].dispatched++; 11852292SN/A 11862292SN/A ++iewDispatchedInsts; 11878471SGiacomo.Gabrielli@arm.com 11888471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11899046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11908471SGiacomo.Gabrielli@arm.com#endif 119110023Smatt.horsnell@ARM.com ppDispatch->notify(inst); 11922292SN/A } 11932292SN/A 11942292SN/A if (!insts_to_dispatch.empty()) { 11952935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11962292SN/A block(tid); 11972292SN/A toRename->iewUnblock[tid] = false; 11982292SN/A } 11992292SN/A 12002292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 12012292SN/A dispatchStatus[tid] = Running; 12022292SN/A 12032292SN/A updatedQueues = true; 12042292SN/A } 12052292SN/A 12062292SN/A dis_num_inst = 0; 12072292SN/A} 12082292SN/A 12092292SN/Atemplate <class Impl> 12102292SN/Avoid 12112292SN/ADefaultIEW<Impl>::printAvailableInsts() 12122292SN/A{ 12132292SN/A int inst = 0; 12142292SN/A 12152980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 12162292SN/A 12172292SN/A while (fromIssue->insts[inst]) { 12182292SN/A 12192980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 12202292SN/A 12217720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 12222292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12232292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12242292SN/A 12252292SN/A inst++; 12262292SN/A 12272292SN/A } 12282292SN/A 12292980Sgblack@eecs.umich.edu std::cout << "\n"; 12302292SN/A} 12312292SN/A 12322292SN/Atemplate <class Impl> 12332292SN/Avoid 12342292SN/ADefaultIEW<Impl>::executeInsts() 12352292SN/A{ 12362292SN/A wbNumInst = 0; 12372292SN/A wbCycle = 0; 12382292SN/A 12396221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12406221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12412292SN/A 12423867Sbinkertn@umich.edu while (threads != end) { 12436221Snate@binkert.org ThreadID tid = *threads++; 12442292SN/A fetchRedirect[tid] = false; 12452292SN/A } 12462292SN/A 12472698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12487599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12492698Sktlim@umich.edu// printAvailableInsts(); 12501062SN/A 12511062SN/A // Execute/writeback any instructions that are available. 12522333SN/A int insts_to_execute = fromIssue->size; 12532292SN/A int inst_num = 0; 12542333SN/A for (; inst_num < insts_to_execute; 12552326SN/A ++inst_num) { 12561062SN/A 12572292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12581062SN/A 12592333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12601062SN/A 12617720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12627720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12631062SN/A 12641062SN/A // Check if the instruction is squashed; if so then skip it 12651062SN/A if (inst->isSquashed()) { 12668315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12678315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12688315Sgeoffrey.blake@arm.com inst->seqNum); 12691062SN/A 12701062SN/A // Consider this instruction executed so that commit can go 12711062SN/A // ahead and retire the instruction. 12721062SN/A inst->setExecuted(); 12731062SN/A 12742292SN/A // Not sure if I should set this here or just let commit try to 12752292SN/A // commit any squashed instructions. I like the latter a bit more. 12762292SN/A inst->setCanCommit(); 12771062SN/A 12781062SN/A ++iewExecSquashedInsts; 12791062SN/A 12802820Sktlim@umich.edu decrWb(inst->seqNum); 12811062SN/A continue; 12821062SN/A } 12831062SN/A 12842292SN/A Fault fault = NoFault; 12851062SN/A 12861062SN/A // Execute instruction. 12871062SN/A // Note that if the instruction faults, it will be handled 12881062SN/A // at the commit stage. 12897850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12902292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12911062SN/A "reference.\n"); 12921062SN/A 12931062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12941062SN/A if (inst->isLoad()) { 12952292SN/A // Loads will mark themselves as executed, and their writeback 12962292SN/A // event adds the instruction to the queue to commit 12972292SN/A fault = ldstQueue.executeLoad(inst); 12987944SGiacomo.Gabrielli@arm.com 12997944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 13007944SGiacomo.Gabrielli@arm.com fault == NoFault) { 13017944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 13027944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 13037944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 13047944SGiacomo.Gabrielli@arm.com "load.\n"); 13057944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13067944SGiacomo.Gabrielli@arm.com continue; 13077944SGiacomo.Gabrielli@arm.com } 13087944SGiacomo.Gabrielli@arm.com 13097850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 13108073SAli.Saidi@ARM.com inst->fault = NoFault; 13117850SMatt.Horsnell@arm.com } 13121062SN/A } else if (inst->isStore()) { 13132367SN/A fault = ldstQueue.executeStore(inst); 13141062SN/A 13157944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 13167944SGiacomo.Gabrielli@arm.com fault == NoFault) { 13177944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 13187944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 13197944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 13207944SGiacomo.Gabrielli@arm.com "store.\n"); 13217944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 13227944SGiacomo.Gabrielli@arm.com continue; 13237944SGiacomo.Gabrielli@arm.com } 13247944SGiacomo.Gabrielli@arm.com 13252292SN/A // If the store had a fault then it may not have a mem req 132610231Ssteve.reinhardt@amd.com if (fault != NoFault || !inst->readPredicate() || 13277782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 13287782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 13297782Sminkyu.jeong@arm.com // to commit without the instruction completing. 13302367SN/A // Send this instruction to commit, also make sure iew stage 13312367SN/A // realizes there is activity. 13322367SN/A inst->setExecuted(); 13332367SN/A instToCommit(inst); 13342367SN/A activityThisCycle(); 13352292SN/A } 13362326SN/A 13372326SN/A // Store conditionals will mark themselves as 13382326SN/A // executed, and their writeback event will add the 13392326SN/A // instruction to the queue to commit. 13401062SN/A } else { 13412292SN/A panic("Unexpected memory type!\n"); 13421062SN/A } 13431062SN/A 13441062SN/A } else { 13457847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13467847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13477847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13487847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13497847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13507847Sminkyu.jeong@arm.com inst->execute(); 135110231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 13527848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13537847Sminkyu.jeong@arm.com } 13541062SN/A 13552292SN/A inst->setExecuted(); 13562292SN/A 13572292SN/A instToCommit(inst); 13581062SN/A } 13591062SN/A 13602301SN/A updateExeInstStats(inst); 13611681SN/A 13622326SN/A // Check if branch prediction was correct, if not then we need 13632326SN/A // to tell commit to squash in flight instructions. Only 13642326SN/A // handle this if there hasn't already been something that 13652107SN/A // redirects fetch in this group of instructions. 13661681SN/A 13672292SN/A // This probably needs to prioritize the redirects if a different 13682292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13692292SN/A // instruction first, so the branch resolution order will be correct. 13706221Snate@binkert.org ThreadID tid = inst->threadNumber; 13711062SN/A 13723732Sktlim@umich.edu if (!fetchRedirect[tid] || 13737852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13743732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13751062SN/A 13767856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13777856SMatt.Horsnell@arm.com // that have not been executed. 13787856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13797856SMatt.Horsnell@arm.com 13807856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13812292SN/A fetchRedirect[tid] = true; 13821062SN/A 13832292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13848674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13858674Snilay@cs.wisc.edu inst->readPredTarg()); 13867720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13878674Snilay@cs.wisc.edu inst->pcState()); 13881062SN/A // If incorrect, then signal the ROB that it must be squashed. 13892292SN/A squashDueToBranch(inst, tid); 13901062SN/A 139110023Smatt.horsnell@ARM.com ppMispredict->notify(inst); 139210023Smatt.horsnell@ARM.com 13933795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13941062SN/A predictedTakenIncorrect++; 13952292SN/A } else { 13962292SN/A predictedNotTakenIncorrect++; 13971062SN/A } 13982292SN/A } else if (ldstQueue.violation(tid)) { 13994033Sktlim@umich.edu assert(inst->isMemRef()); 14002326SN/A // If there was an ordering violation, then get the 14012326SN/A // DynInst that caused the violation. Note that this 14022292SN/A // clears the violation signal. 14032292SN/A DynInstPtr violator; 14042292SN/A violator = ldstQueue.getMemDepViolator(tid); 14051062SN/A 14067720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 14077720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 14087720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 14097720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 14107720Sgblack@eecs.umich.edu 14113732Sktlim@umich.edu fetchRedirect[tid] = true; 14123732Sktlim@umich.edu 14131062SN/A // Tell the instruction queue that a violation has occured. 14141062SN/A instQueue.violation(inst, violator); 14151062SN/A 14161062SN/A // Squash. 14178513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 14181062SN/A 14191062SN/A ++memOrderViolationEvents; 14202292SN/A } else if (ldstQueue.loadBlocked(tid) && 14212292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 14222292SN/A fetchRedirect[tid] = true; 14232292SN/A 14242292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 14257720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14267720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14272292SN/A 14282292SN/A squashDueToMemBlocked(inst, tid); 14291062SN/A } 14304033Sktlim@umich.edu } else { 14314033Sktlim@umich.edu // Reset any state associated with redirects that will not 14324033Sktlim@umich.edu // be used. 14334033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 14344033Sktlim@umich.edu assert(inst->isMemRef()); 14354033Sktlim@umich.edu 14364033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14374033Sktlim@umich.edu 14384033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14397720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14407720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14417720Sgblack@eecs.umich.edu inst->physEffAddr); 14424033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14434033Sktlim@umich.edu "already squashing\n"); 14444033Sktlim@umich.edu 14454033Sktlim@umich.edu ++memOrderViolationEvents; 14464033Sktlim@umich.edu } 14474033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14484033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14494033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14507720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14517720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14524033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14534033Sktlim@umich.edu "already squashing\n"); 14544033Sktlim@umich.edu 14554033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14564033Sktlim@umich.edu } 14574033Sktlim@umich.edu 14581062SN/A } 14591062SN/A } 14602292SN/A 14612348SN/A // Update and record activity if we processed any instructions. 14622292SN/A if (inst_num) { 14632292SN/A if (exeStatus == Idle) { 14642292SN/A exeStatus = Running; 14652292SN/A } 14662292SN/A 14672292SN/A updatedQueues = true; 14682292SN/A 14692292SN/A cpu->activityThisCycle(); 14702292SN/A } 14712292SN/A 14722292SN/A // Need to reset this in case a writeback event needs to write into the 14732292SN/A // iew queue. That way the writeback event will write into the correct 14742292SN/A // spot in the queue. 14752292SN/A wbNumInst = 0; 14767852SMatt.Horsnell@arm.com 14772107SN/A} 14782107SN/A 14792292SN/Atemplate <class Impl> 14802107SN/Avoid 14812292SN/ADefaultIEW<Impl>::writebackInsts() 14822107SN/A{ 14832326SN/A // Loop through the head of the time buffer and wake any 14842326SN/A // dependents. These instructions are about to write back. Also 14852326SN/A // mark scoreboard that this instruction is finally complete. 14862326SN/A // Either have IEW have direct access to scoreboard, or have this 14872326SN/A // as part of backwards communication. 14883958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14892292SN/A toCommit->insts[inst_num]; inst_num++) { 14902107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14916221Snate@binkert.org ThreadID tid = inst->threadNumber; 14922107SN/A 14937720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14947720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14952107SN/A 14962301SN/A iewInstsToCommit[tid]++; 14972301SN/A 14982292SN/A // Some instructions will be sent to commit without having 14992292SN/A // executed because they need commit to handle them. 15002292SN/A // E.g. Uncached loads have not actually executed when they 15012292SN/A // are first sent to commit. Instead commit must tell the LSQ 15022292SN/A // when it's ready to execute the uncached load. 15032367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 15042301SN/A int dependents = instQueue.wakeDependents(inst); 15052107SN/A 15062292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 15072292SN/A //mark as Ready 15082292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 15092292SN/A inst->renamedDestRegIdx(i)); 15102292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 15112107SN/A } 15122301SN/A 15132348SN/A if (dependents) { 15142348SN/A producerInst[tid]++; 15152348SN/A consumerInst[tid]+= dependents; 15162348SN/A } 15172326SN/A writebackCount[tid]++; 15182107SN/A } 15192820Sktlim@umich.edu 15202820Sktlim@umich.edu decrWb(inst->seqNum); 15212107SN/A } 15221060SN/A} 15231060SN/A 15241681SN/Atemplate<class Impl> 15251060SN/Avoid 15262292SN/ADefaultIEW<Impl>::tick() 15271060SN/A{ 15282292SN/A wbNumInst = 0; 15292292SN/A wbCycle = 0; 15301060SN/A 15312292SN/A wroteToTimeBuffer = false; 15322292SN/A updatedQueues = false; 15331060SN/A 15342292SN/A sortInsts(); 15351060SN/A 15362326SN/A // Free function units marked as being freed this cycle. 15372326SN/A fuPool->processFreeUnits(); 15381062SN/A 15396221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15406221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15411060SN/A 15422326SN/A // Check stall and squash signals, dispatch any instructions. 15433867Sbinkertn@umich.edu while (threads != end) { 15446221Snate@binkert.org ThreadID tid = *threads++; 15451060SN/A 15462292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15471060SN/A 15482292SN/A checkSignalsAndUpdate(tid); 15492292SN/A dispatch(tid); 15501060SN/A } 15511060SN/A 15522292SN/A if (exeStatus != Squashing) { 15532292SN/A executeInsts(); 15541060SN/A 15552292SN/A writebackInsts(); 15562292SN/A 15572292SN/A // Have the instruction queue try to schedule any ready instructions. 15582292SN/A // (In actuality, this scheduling is for instructions that will 15592292SN/A // be executed next cycle.) 15602292SN/A instQueue.scheduleReadyInsts(); 15612292SN/A 15622292SN/A // Also should advance its own time buffers if the stage ran. 15632292SN/A // Not the best place for it, but this works (hopefully). 15642292SN/A issueToExecQueue.advance(); 15652292SN/A } 15662292SN/A 15672292SN/A bool broadcast_free_entries = false; 15682292SN/A 15692292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15702292SN/A exeStatus = Idle; 15712292SN/A updateLSQNextCycle = false; 15722292SN/A 15732292SN/A broadcast_free_entries = true; 15742292SN/A } 15752292SN/A 15762292SN/A // Writeback any stores using any leftover bandwidth. 15771681SN/A ldstQueue.writebackStores(); 15781681SN/A 15791061SN/A // Check the committed load/store signals to see if there's a load 15801061SN/A // or store to commit. Also check if it's being told to execute a 15811061SN/A // nonspeculative instruction. 15821681SN/A // This is pretty inefficient... 15832292SN/A 15843867Sbinkertn@umich.edu threads = activeThreads->begin(); 15853867Sbinkertn@umich.edu while (threads != end) { 15866221Snate@binkert.org ThreadID tid = (*threads++); 15872292SN/A 15882292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15892292SN/A 15902348SN/A // Update structures based on instructions committed. 15912292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15922292SN/A !fromCommit->commitInfo[tid].squash && 15932292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15942292SN/A 15952292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15962292SN/A 15972292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15982292SN/A 15992292SN/A updateLSQNextCycle = true; 16002292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 16012292SN/A } 16022292SN/A 16032292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 16042292SN/A 16052292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 16062292SN/A if (fromCommit->commitInfo[tid].uncached) { 16072292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 16084033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 16092292SN/A } else { 16102292SN/A instQueue.scheduleNonSpec( 16112292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 16122292SN/A } 16132292SN/A } 16142292SN/A 16152292SN/A if (broadcast_free_entries) { 16162292SN/A toFetch->iewInfo[tid].iqCount = 16172292SN/A instQueue.getCount(tid); 16182292SN/A toFetch->iewInfo[tid].ldstqCount = 16192292SN/A ldstQueue.getCount(tid); 16202292SN/A 16212292SN/A toRename->iewInfo[tid].usedIQ = true; 16222292SN/A toRename->iewInfo[tid].freeIQEntries = 162310164Ssleimanf@umich.edu instQueue.numFreeEntries(tid); 16242292SN/A toRename->iewInfo[tid].usedLSQ = true; 162510239Sbinhpham@cs.rutgers.edu 162610239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeLQEntries = 162710239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(tid); 162810239Sbinhpham@cs.rutgers.edu toRename->iewInfo[tid].freeSQEntries = 162910239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeStoreEntries(tid); 16302292SN/A 16312292SN/A wroteToTimeBuffer = true; 16322292SN/A } 16332292SN/A 16342292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 16352292SN/A tid, toRename->iewInfo[tid].dispatched); 16361061SN/A } 16371061SN/A 16382292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 163910239Sbinhpham@cs.rutgers.edu "LQ has %i free entries. SQ has %i free entries.\n", 16402292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 164110239Sbinhpham@cs.rutgers.edu ldstQueue.numFreeLoadEntries(), ldstQueue.numFreeStoreEntries()); 16422292SN/A 16432292SN/A updateStatus(); 16442292SN/A 16452292SN/A if (wroteToTimeBuffer) { 16462292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16472292SN/A cpu->activityThisCycle(); 16481061SN/A } 16491060SN/A} 16501060SN/A 16512301SN/Atemplate <class Impl> 16521060SN/Avoid 16532301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16541060SN/A{ 16556221Snate@binkert.org ThreadID tid = inst->threadNumber; 16561060SN/A 16572669Sktlim@umich.edu iewExecutedInsts++; 16581060SN/A 16598471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16609527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16619527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16629527SMatt.Horsnell@arm.com } 16638471SGiacomo.Gabrielli@arm.com#endif 16648471SGiacomo.Gabrielli@arm.com 16652301SN/A // 16662301SN/A // Control operations 16672301SN/A // 16682301SN/A if (inst->isControl()) 16696221Snate@binkert.org iewExecutedBranches[tid]++; 16701060SN/A 16712301SN/A // 16722301SN/A // Memory operations 16732301SN/A // 16742301SN/A if (inst->isMemRef()) { 16756221Snate@binkert.org iewExecutedRefs[tid]++; 16761060SN/A 16772301SN/A if (inst->isLoad()) { 16786221Snate@binkert.org iewExecLoadInsts[tid]++; 16791060SN/A } 16801060SN/A } 16811060SN/A} 16827598Sminkyu.jeong@arm.com 16837598Sminkyu.jeong@arm.comtemplate <class Impl> 16847598Sminkyu.jeong@arm.comvoid 16857598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16867598Sminkyu.jeong@arm.com{ 16877598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16887598Sminkyu.jeong@arm.com 16897598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16907852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16917598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16927598Sminkyu.jeong@arm.com 16937598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16947598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16957598Sminkyu.jeong@arm.com 16967598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16977598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16987720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16997598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 17007720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 17017720Sgblack@eecs.umich.edu inst->nextInstAddr()); 17027598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 17037598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 17047598Sminkyu.jeong@arm.com 17057598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 17067598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 17077598Sminkyu.jeong@arm.com } else { 17087598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 17097598Sminkyu.jeong@arm.com } 17107598Sminkyu.jeong@arm.com } 17117598Sminkyu.jeong@arm.com } 17127598Sminkyu.jeong@arm.com} 17139944Smatt.horsnell@ARM.com 17149944Smatt.horsnell@ARM.com#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1715