iew_impl.hh revision 10231
11689SN/A/* 22329SN/A * Copyright (c) 2010-2013 ARM Limited 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * The license below extends only to copyright in the software and shall 61689SN/A * not be construed as granting a license to any other intellectual 71689SN/A * property including but not limited to intellectual property relating 81689SN/A * to a hardware implementation of the functionality of the software 91689SN/A * licensed hereunder. You may use the software subject to the license 101689SN/A * terms below provided that you ensure that this notice is replicated 111689SN/A * unmodified and in its entirety in all distributions of the software, 121689SN/A * modified or unmodified, in source code or in binary form. 131689SN/A * 141689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331858SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341717SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381061SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392292SN/A * 402292SN/A * Authors: Kevin Lim 412292SN/A */ 422292SN/A 432292SN/A#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__ 442292SN/A#define __CPU_O3_IEW_IMPL_IMPL_HH__ 452292SN/A 461060SN/A// @todo: Fix the instantaneous communication among all the stages within 472292SN/A// iew. There's a clear delay between issue and execute, yet backwards 482292SN/A// communication happens simultaneously. 492292SN/A 502292SN/A#include <queue> 512292SN/A 522292SN/A#include "arch/utility.hh" 532292SN/A#include "config/the_isa.hh" 542292SN/A#include "cpu/checker/cpu.hh" 552292SN/A#include "cpu/o3/fu_pool.hh" 562292SN/A#include "cpu/o3/iew.hh" 572292SN/A#include "cpu/timebuf.hh" 582301SN/A#include "debug/Activity.hh" 592292SN/A#include "debug/Drain.hh" 602292SN/A#include "debug/IEW.hh" 612292SN/A#include "debug/O3PipeView.hh" 622292SN/A#include "params/DerivO3CPU.hh" 632292SN/A 642292SN/Ausing namespace std; 652292SN/A 662292SN/Atemplate<class Impl> 672292SN/ADefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 682292SN/A : issueToExecQueue(params->backComSize, params->forwardComSize), 692292SN/A cpu(_cpu), 702292SN/A instQueue(_cpu, this, params), 712292SN/A ldstQueue(_cpu, this, params), 722292SN/A fuPool(params->fuPool), 732292SN/A commitToIEWDelay(params->commitToIEWDelay), 742292SN/A renameToIEWDelay(params->renameToIEWDelay), 752292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 761060SN/A dispatchWidth(params->dispatchWidth), 771060SN/A issueWidth(params->issueWidth), 781061SN/A wbOutstanding(0), 791060SN/A wbWidth(params->wbWidth), 802292SN/A numThreads(params->numThreads) 811062SN/A{ 821062SN/A if (dispatchWidth > Impl::MaxWidth) 832301SN/A fatal("dispatchWidth (%d) is larger than compiled limit (%d),\n" 841062SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 851062SN/A dispatchWidth, static_cast<int>(Impl::MaxWidth)); 861062SN/A if (issueWidth > Impl::MaxWidth) 872301SN/A fatal("issueWidth (%d) is larger than compiled limit (%d),\n" 881062SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 891062SN/A issueWidth, static_cast<int>(Impl::MaxWidth)); 901062SN/A if (wbWidth > Impl::MaxWidth) 912301SN/A fatal("wbWidth (%d) is larger than compiled limit (%d),\n" 921062SN/A "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 931062SN/A wbWidth, static_cast<int>(Impl::MaxWidth)); 942301SN/A 952301SN/A _status = Active; 962301SN/A exeStatus = Running; 972301SN/A wbStatus = Idle; 982292SN/A 992301SN/A // Setup wire to read instructions coming from issue. 1002292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1012292SN/A 1021062SN/A // Instruction queue needs the queue between issue and execute. 1032301SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1041062SN/A 1051062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1061062SN/A dispatchStatus[tid] = Running; 1072301SN/A stalls[tid].commit = false; 1081062SN/A fetchRedirect[tid] = false; 1091062SN/A } 1101062SN/A 1112301SN/A wbMax = wbWidth * params->wbDepth; 1121062SN/A 1131062SN/A updateLSQNextCycle = false; 1141062SN/A 1152301SN/A ableToIssue = true; 1162292SN/A 1171062SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1181062SN/A} 1192301SN/A 1202292SN/Atemplate <class Impl> 1211062SN/Astd::string 1222292SN/ADefaultIEW<Impl>::name() const 1232301SN/A{ 1242292SN/A return cpu->name() + ".iew"; 1252292SN/A} 1261062SN/A 1272301SN/Atemplate <class Impl> 1281062SN/Avoid 1291062SN/ADefaultIEW<Impl>::regProbePoints() 1301062SN/A{ 1312301SN/A ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); 1321062SN/A ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); 1331062SN/A} 1341062SN/A 1352301SN/Atemplate <class Impl> 1361062SN/Avoid 1371062SN/ADefaultIEW<Impl>::regStats() 1381062SN/A{ 1392301SN/A using namespace Stats; 1401062SN/A 1411062SN/A instQueue.regStats(); 1421062SN/A ldstQueue.regStats(); 1432301SN/A 1441062SN/A iewIdleCycles 1451062SN/A .name(name() + ".iewIdleCycles") 1462301SN/A .desc("Number of cycles IEW is idle"); 1472301SN/A 1482301SN/A iewSquashCycles 1492301SN/A .name(name() + ".iewSquashCycles") 1502301SN/A .desc("Number of cycles IEW is squashing"); 1512301SN/A 1522301SN/A iewBlockCycles 1532301SN/A .name(name() + ".iewBlockCycles") 1542301SN/A .desc("Number of cycles IEW is blocking"); 1552301SN/A 1562307SN/A iewUnblockCycles 1572307SN/A .name(name() + ".iewUnblockCycles") 1582307SN/A .desc("Number of cycles IEW is unblocking"); 1592307SN/A 1602307SN/A iewDispatchedInsts 1611062SN/A .name(name() + ".iewDispatchedInsts") 1621062SN/A .desc("Number of instructions dispatched to IQ"); 1631062SN/A 1641062SN/A iewDispSquashedInsts 1652292SN/A .name(name() + ".iewDispSquashedInsts") 1661060SN/A .desc("Number of squashed instructions skipped by dispatch"); 1672292SN/A 1681060SN/A iewDispLoadInsts 1691060SN/A .name(name() + ".iewDispLoadInsts") 1701060SN/A .desc("Number of dispatched load instructions"); 1711061SN/A 1721060SN/A iewDispStoreInsts 1732292SN/A .name(name() + ".iewDispStoreInsts") 1741060SN/A .desc("Number of dispatched store instructions"); 1752292SN/A 1761060SN/A iewDispNonSpecInsts 1771060SN/A .name(name() + ".iewDispNonSpecInsts") 1781060SN/A .desc("Number of dispatched non-speculative instructions"); 1791060SN/A 1801060SN/A iewIQFullEvents 1811060SN/A .name(name() + ".iewIQFullEvents") 1821060SN/A .desc("Number of times the IQ has become full, causing a stall"); 1831060SN/A 1841060SN/A iewLSQFullEvents 1851060SN/A .name(name() + ".iewLSQFullEvents") 1861060SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1871060SN/A 1881061SN/A memOrderViolationEvents 1891060SN/A .name(name() + ".memOrderViolationEvents") 1902292SN/A .desc("Number of memory order violations"); 1911060SN/A 1922292SN/A predictedTakenIncorrect 1931060SN/A .name(name() + ".predictedTakenIncorrect") 1941060SN/A .desc("Number of branches that were predicted taken incorrectly"); 1951060SN/A 1961060SN/A predictedNotTakenIncorrect 1971060SN/A .name(name() + ".predictedNotTakenIncorrect") 1981060SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1991061SN/A 2001060SN/A branchMispredicts 2012292SN/A .name(name() + ".branchMispredicts") 2021060SN/A .desc("Number of branch mispredicts detected at execute"); 2032292SN/A 2041060SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2051060SN/A 2061060SN/A iewExecutedInsts 2071060SN/A .name(name() + ".iewExecutedInsts") 2081060SN/A .desc("Number of executed instructions"); 2091060SN/A 2101061SN/A iewExecLoadInsts 2111060SN/A .init(cpu->numThreads) 2122292SN/A .name(name() + ".iewExecLoadInsts") 2131060SN/A .desc("Number of load instructions executed") 2142329SN/A .flags(total); 2152292SN/A 2162292SN/A iewExecSquashedInsts 2172292SN/A .name(name() + ".iewExecSquashedInsts") 2182292SN/A .desc("Number of squashed instructions skipped in execute"); 2192292SN/A 2202292SN/A iewExecutedSwp 2211060SN/A .init(cpu->numThreads) 2221060SN/A .name(name() + ".exec_swp") 2232292SN/A .desc("number of swp insts executed") 2242292SN/A .flags(total); 2252292SN/A 2262292SN/A iewExecutedNop 2272292SN/A .init(cpu->numThreads) 2282292SN/A .name(name() + ".exec_nop") 2292292SN/A .desc("number of nop insts executed") 2302292SN/A .flags(total); 2312292SN/A 2321061SN/A iewExecutedRefs 2331060SN/A .init(cpu->numThreads) 2342292SN/A .name(name() + ".exec_refs") 2351060SN/A .desc("number of memory reference insts executed") 2362292SN/A .flags(total); 2371060SN/A 2382292SN/A iewExecutedBranches 2392292SN/A .init(cpu->numThreads) 2401060SN/A .name(name() + ".exec_branches") 2411060SN/A .desc("Number of branches executed") 2421060SN/A .flags(total); 2431061SN/A 2441060SN/A iewExecStoreInsts 2452292SN/A .name(name() + ".exec_stores") 2461060SN/A .desc("Number of stores executed") 2472292SN/A .flags(total); 2482292SN/A iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2492292SN/A 2501060SN/A iewExecRate 2512292SN/A .name(name() + ".exec_rate") 2522292SN/A .desc("Inst execution rate") 2532292SN/A .flags(total); 2542292SN/A 2552292SN/A iewExecRate = iewExecutedInsts / cpu->numCycles; 2562292SN/A 2571060SN/A iewInstsToCommit 2581060SN/A .init(cpu->numThreads) 2591061SN/A .name(name() + ".wb_sent") 2602292SN/A .desc("cumulative count of insts sent to commit") 2612307SN/A .flags(total); 2621060SN/A 2632348SN/A writebackCount 2642316SN/A .init(cpu->numThreads) 2652316SN/A .name(name() + ".wb_count") 2661060SN/A .desc("cumulative count of insts written-back") 2672316SN/A .flags(total); 2682316SN/A 2692316SN/A producerInst 2702316SN/A .init(cpu->numThreads) 2712348SN/A .name(name() + ".wb_producers") 2722307SN/A .desc("num instructions producing a value") 2732307SN/A .flags(total); 2742307SN/A 2752307SN/A consumerInst 2762307SN/A .init(cpu->numThreads) 2772307SN/A .name(name() + ".wb_consumers") 2782307SN/A .desc("num instructions consuming a value") 2792307SN/A .flags(total); 2802307SN/A 2812307SN/A wbPenalized 2822307SN/A .init(cpu->numThreads) 2832307SN/A .name(name() + ".wb_penalized") 2842307SN/A .desc("number of instrctions required to write to 'other' IQ") 2852307SN/A .flags(total); 2862307SN/A 2872307SN/A wbPenalizedRate 2882307SN/A .name(name() + ".wb_penalized_rate") 2892307SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2902307SN/A .flags(total); 2912307SN/A 2921060SN/A wbPenalizedRate = wbPenalized / writebackCount; 2931060SN/A 2941060SN/A wbFanout 2951061SN/A .name(name() + ".wb_fanout") 2961060SN/A .desc("average fanout of values written-back") 2972307SN/A .flags(total); 2981060SN/A 2992307SN/A wbFanout = producerInst / consumerInst; 3002307SN/A 3011060SN/A wbRate 3022329SN/A .name(name() + ".wb_rate") 3032307SN/A .desc("insts written-back per cycle") 3042307SN/A .flags(total); 3051060SN/A wbRate = writebackCount / cpu->numCycles; 3062307SN/A} 3072307SN/A 3082307SN/Atemplate<class Impl> 3092307SN/Avoid 3102307SN/ADefaultIEW<Impl>::startupStage() 3112307SN/A{ 3122307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3132307SN/A toRename->iewInfo[tid].usedIQ = true; 3142307SN/A toRename->iewInfo[tid].freeIQEntries = 3152307SN/A instQueue.numFreeEntries(tid); 3162307SN/A 3172307SN/A toRename->iewInfo[tid].usedLSQ = true; 3182307SN/A toRename->iewInfo[tid].freeLSQEntries = 3192307SN/A ldstQueue.numFreeEntries(tid); 3202292SN/A } 3211858SN/A 3222292SN/A // Initialize the checker's dcache port here 3231858SN/A if (cpu->checker) { 3242292SN/A cpu->checker->setDcachePort(&cpu->getDataPort()); 3252292SN/A } 3262292SN/A 3272292SN/A cpu->activateStage(O3CPU::IEWIdx); 3282292SN/A} 3292301SN/A 3302698Sktlim@umich.edutemplate<class Impl> 3312292SN/Avoid 3322698Sktlim@umich.eduDefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3332301SN/A{ 3342292SN/A timeBuffer = tb_ptr; 3352292SN/A 3362292SN/A // Setup wire to read information from time buffer, from commit. 3372292SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3382292SN/A 3392329SN/A // Setup wire to write information back to previous stages. 3402292SN/A toRename = timeBuffer->getWire(0); 3412292SN/A 3422292SN/A toFetch = timeBuffer->getWire(0); 3432292SN/A 3442731Sktlim@umich.edu // Instruction queue also needs main time buffer. 3452292SN/A instQueue.setTimeBuffer(tb_ptr); 3462292SN/A} 3472292SN/A 3482292SN/Atemplate<class Impl> 3492292SN/Avoid 3502292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3512292SN/A{ 3522292SN/A renameQueue = rq_ptr; 3532292SN/A 3542292SN/A // Setup wire to read information from rename queue. 3552292SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3562292SN/A} 3572292SN/A 3582292SN/Atemplate<class Impl> 3592292SN/Avoid 3602292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3612292SN/A{ 3622292SN/A iewQueue = iq_ptr; 3632292SN/A 3642292SN/A // Setup wire to write instructions to commit. 3652292SN/A toCommit = iewQueue->getWire(0); 3662292SN/A} 3672292SN/A 3682292SN/Atemplate<class Impl> 3692292SN/Avoid 3702292SN/ADefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3712292SN/A{ 3722292SN/A activeThreads = at_ptr; 3732292SN/A 3742292SN/A ldstQueue.setActiveThreads(at_ptr); 3752292SN/A instQueue.setActiveThreads(at_ptr); 3762292SN/A} 3772292SN/A 3782292SN/Atemplate<class Impl> 3792292SN/Avoid 3802292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3812292SN/A{ 3822292SN/A scoreboard = sb_ptr; 3832292SN/A} 3842292SN/A 3852292SN/Atemplate <class Impl> 3862292SN/Abool 3872292SN/ADefaultIEW<Impl>::isDrained() const 3882292SN/A{ 3892292SN/A bool drained(ldstQueue.isDrained()); 3902292SN/A 3912292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3922292SN/A if (!insts[tid].empty()) { 3932292SN/A DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3942292SN/A drained = false; 3952292SN/A } 3962292SN/A if (!skidBuffer[tid].empty()) { 3972292SN/A DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3982292SN/A drained = false; 3992292SN/A } 4002292SN/A } 4012292SN/A 4022292SN/A // Also check the FU pool as instructions are "stored" in FU 4032292SN/A // completion events until they are done and not accounted for 4042292SN/A // above 4052292SN/A if (drained && !fuPool->isDrained()) { 4062292SN/A DPRINTF(Drain, "FU pool still busy.\n"); 4072292SN/A drained = false; 4082292SN/A } 4092292SN/A 4102292SN/A return drained; 4112292SN/A} 4122292SN/A 4132292SN/Atemplate <class Impl> 4142292SN/Avoid 4152292SN/ADefaultIEW<Impl>::drainSanityCheck() const 4162292SN/A{ 4172292SN/A assert(isDrained()); 4182292SN/A 4192292SN/A instQueue.drainSanityCheck(); 4202292SN/A ldstQueue.drainSanityCheck(); 4212292SN/A} 4222292SN/A 4232292SN/Atemplate <class Impl> 4242292SN/Avoid 4252292SN/ADefaultIEW<Impl>::takeOverFrom() 4262292SN/A{ 4272292SN/A // Reset all state. 4282292SN/A _status = Active; 4292292SN/A exeStatus = Running; 4302292SN/A wbStatus = Idle; 4312292SN/A 4322292SN/A instQueue.takeOverFrom(); 4332301SN/A ldstQueue.takeOverFrom(); 4342301SN/A fuPool->takeOverFrom(); 4352292SN/A 4362292SN/A startupStage(); 4372292SN/A cpu->activityThisCycle(); 4382292SN/A 4392292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 4402292SN/A dispatchStatus[tid] = Running; 4412292SN/A stalls[tid].commit = false; 4422292SN/A fetchRedirect[tid] = false; 4432292SN/A } 4442292SN/A 4452292SN/A updateLSQNextCycle = false; 4462292SN/A 4472292SN/A for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4482292SN/A issueToExecQueue.advance(); 4492292SN/A } 4502292SN/A} 4512292SN/A 4522292SN/Atemplate<class Impl> 4532292SN/Avoid 4542292SN/ADefaultIEW<Impl>::squash(ThreadID tid) 4551858SN/A{ 4561858SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4571858SN/A 4581858SN/A // Tell the IQ to start squashing. 4591858SN/A instQueue.squash(tid); 4602292SN/A 4611858SN/A // Tell the LDSTQ to start squashing. 4622292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4632292SN/A updatedQueues = true; 4642292SN/A 4652292SN/A // Clear the skid buffer in case it has any data in it. 4661858SN/A DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4672292SN/A tid, fromCommit->commitInfo[tid].doneSeqNum); 4682292SN/A 4692292SN/A while (!skidBuffer[tid].empty()) { 4702292SN/A if (skidBuffer[tid].front()->isLoad() || 4712292SN/A skidBuffer[tid].front()->isStore() ) { 4722292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4732292SN/A } 4742292SN/A 4752292SN/A toRename->iewInfo[tid].dispatched++; 4762292SN/A 4772292SN/A skidBuffer[tid].pop(); 4782292SN/A } 4792292SN/A 4801858SN/A emptyRenameInsts(tid); 4812292SN/A} 4822292SN/A 4832292SN/Atemplate<class Impl> 4842292SN/Avoid 4852292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4862292SN/A{ 4872292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4882292SN/A "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4892292SN/A 4902292SN/A if (!toCommit->squash[tid] || 4912292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 4922292SN/A toCommit->squash[tid] = true; 4932292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4942292SN/A toCommit->branchTaken[tid] = inst->pcState().branching(); 4952292SN/A 4962292SN/A TheISA::PCState pc = inst->pcState(); 4972292SN/A TheISA::advancePC(pc, inst->staticInst); 4982292SN/A 4992292SN/A toCommit->pc[tid] = pc; 5002292SN/A toCommit->mispredictInst[tid] = inst; 5012292SN/A toCommit->includeSquashInst[tid] = false; 5022292SN/A 5032292SN/A wroteToTimeBuffer = true; 5042292SN/A } 5052292SN/A 5062292SN/A} 5072292SN/A 5082292SN/Atemplate<class Impl> 5092292SN/Avoid 5102292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 5112292SN/A{ 5122292SN/A DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 5132292SN/A "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5142292SN/A // Need to include inst->seqNum in the following comparison to cover the 5152292SN/A // corner case when a branch misprediction and a memory violation for the 5162292SN/A // same instruction (e.g. load PC) are detected in the same cycle. In this 5172292SN/A // case the memory violator should take precedence over the branch 5182292SN/A // misprediction because it requires the violator itself to be included in 5192292SN/A // the squash. 5202292SN/A if (!toCommit->squash[tid] || 5212292SN/A inst->seqNum <= toCommit->squashedSeqNum[tid]) { 5222292SN/A toCommit->squash[tid] = true; 5232292SN/A 5242292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5252292SN/A toCommit->pc[tid] = inst->pcState(); 5262292SN/A toCommit->mispredictInst[tid] = NULL; 5272292SN/A 5282292SN/A // Must include the memory violator in the squash. 5292292SN/A toCommit->includeSquashInst[tid] = true; 5302292SN/A 5312292SN/A wroteToTimeBuffer = true; 5322292SN/A } 5332292SN/A} 5342292SN/A 5352292SN/Atemplate<class Impl> 5362292SN/Avoid 5372292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5382292SN/A{ 5392292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5402292SN/A "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5412292SN/A if (!toCommit->squash[tid] || 5422292SN/A inst->seqNum < toCommit->squashedSeqNum[tid]) { 5432292SN/A toCommit->squash[tid] = true; 5442292SN/A 5452292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5462292SN/A toCommit->pc[tid] = inst->pcState(); 5472292SN/A toCommit->mispredictInst[tid] = NULL; 5482292SN/A 5492292SN/A // Must include the broadcasted SN in the squash. 5502292SN/A toCommit->includeSquashInst[tid] = true; 5512292SN/A 5522292SN/A ldstQueue.setLoadBlockedHandled(tid); 5532292SN/A 5542292SN/A wroteToTimeBuffer = true; 5552292SN/A } 5562292SN/A} 5572292SN/A 5582292SN/Atemplate<class Impl> 5592292SN/Avoid 5602292SN/ADefaultIEW<Impl>::block(ThreadID tid) 5612292SN/A{ 5622292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5632292SN/A 5642292SN/A if (dispatchStatus[tid] != Blocked && 5652292SN/A dispatchStatus[tid] != Unblocking) { 5662292SN/A toRename->iewBlock[tid] = true; 5672292SN/A wroteToTimeBuffer = true; 5682292SN/A } 5692292SN/A 5702292SN/A // Add the current inputs to the skid buffer so they can be 5712292SN/A // reprocessed when this stage unblocks. 5722292SN/A skidInsert(tid); 5732292SN/A 5742292SN/A dispatchStatus[tid] = Blocked; 5752292SN/A} 5762292SN/A 5772292SN/Atemplate<class Impl> 5782292SN/Avoid 5792292SN/ADefaultIEW<Impl>::unblock(ThreadID tid) 5802292SN/A{ 5812292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5822292SN/A "buffer %u.\n",tid, tid); 5832292SN/A 5842292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5852292SN/A // Also switch status to running. 5862292SN/A if (skidBuffer[tid].empty()) { 5872292SN/A toRename->iewUnblock[tid] = true; 5882292SN/A wroteToTimeBuffer = true; 5892292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5902292SN/A dispatchStatus[tid] = Running; 5912292SN/A } 5922336SN/A} 5932336SN/A 5942336SN/Atemplate<class Impl> 5952336SN/Avoid 5962336SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5972336SN/A{ 5982336SN/A instQueue.wakeDependents(inst); 5992336SN/A} 6002292SN/A 6012292SN/Atemplate<class Impl> 6022301SN/Avoid 6032301SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6042292SN/A{ 6052301SN/A instQueue.rescheduleMemInst(inst); 6062301SN/A} 6072301SN/A 6082292SN/Atemplate<class Impl> 6092301SN/Avoid 6102292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6112301SN/A{ 6122292SN/A instQueue.replayMemInst(inst); 6132301SN/A} 6142292SN/A 6152292SN/Atemplate<class Impl> 6162292SN/Avoid 6172292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6182336SN/A{ 6192336SN/A // This function should not be called after writebackInsts in a 6202292SN/A // single cycle. That will cause problems with an instruction 6212292SN/A // being added to the queue to commit without being processed by 6222307SN/A // writebackInsts prior to being sent to commit. 6232307SN/A 6242292SN/A // First check the time slot that this instruction will write 6252292SN/A // to. If there are free write ports at the time, then go ahead 6262292SN/A // and write the instruction to that time. If there are not, 6272292SN/A // keep looking back to see where's the first time there's a 6282292SN/A // free slot. 6292292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6302292SN/A ++wbNumInst; 6312292SN/A if (wbNumInst == wbWidth) { 6322292SN/A ++wbCycle; 6332292SN/A wbNumInst = 0; 6342292SN/A } 6352292SN/A 6362292SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6372292SN/A } 6382292SN/A 6392292SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6402292SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6412292SN/A // Add finished instruction to queue to commit. 6422292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6432292SN/A (*iewQueue)[wbCycle].size++; 6442292SN/A} 6452292SN/A 6462292SN/Atemplate <class Impl> 6472292SN/Aunsigned 6482292SN/ADefaultIEW<Impl>::validInstsFromRename() 6492292SN/A{ 6502292SN/A unsigned inst_count = 0; 6512292SN/A 6522292SN/A for (int i=0; i<fromRename->size; i++) { 6532292SN/A if (!fromRename->insts[i]->isSquashed()) 6542292SN/A inst_count++; 6552292SN/A } 6562292SN/A 6572292SN/A return inst_count; 6582292SN/A} 6592307SN/A 6602292SN/Atemplate<class Impl> 6612292SN/Avoid 6622292SN/ADefaultIEW<Impl>::skidInsert(ThreadID tid) 6632292SN/A{ 6642292SN/A DynInstPtr inst = NULL; 6652292SN/A 6662292SN/A while (!insts[tid].empty()) { 6672292SN/A inst = insts[tid].front(); 6682292SN/A 6692292SN/A insts[tid].pop(); 6702292SN/A 6712292SN/A DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6722292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6732292SN/A inst->pcState(),tid); 6742292SN/A 6752292SN/A skidBuffer[tid].push(inst); 6762292SN/A } 6772292SN/A 6782292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6792292SN/A "Skidbuffer Exceeded Max Size"); 6802292SN/A} 6812292SN/A 6822292SN/Atemplate<class Impl> 6832292SN/Aint 6842292SN/ADefaultIEW<Impl>::skidCount() 6852292SN/A{ 6862292SN/A int max=0; 6872292SN/A 6882292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 6892292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6902292SN/A 6912292SN/A while (threads != end) { 6922292SN/A ThreadID tid = *threads++; 6932292SN/A unsigned thread_count = skidBuffer[tid].size(); 6942307SN/A if (max < thread_count) 6952307SN/A max = thread_count; 6962292SN/A } 6972292SN/A 6982292SN/A return max; 6992292SN/A} 7002292SN/A 7012292SN/Atemplate<class Impl> 7022292SN/Abool 7032292SN/ADefaultIEW<Impl>::skidsEmpty() 7042292SN/A{ 7052292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7062292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7072292SN/A 7082329SN/A while (threads != end) { 7092292SN/A ThreadID tid = *threads++; 7102292SN/A 7112329SN/A if (!skidBuffer[tid].empty()) 7122292SN/A return false; 7132292SN/A } 7142292SN/A 7152292SN/A return true; 7162292SN/A} 7172292SN/A 7182292SN/Atemplate <class Impl> 7192292SN/Avoid 7202292SN/ADefaultIEW<Impl>::updateStatus() 7212292SN/A{ 7222292SN/A bool any_unblocking = false; 7232292SN/A 7242292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7252292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7262292SN/A 7272292SN/A while (threads != end) { 7282292SN/A ThreadID tid = *threads++; 7292292SN/A 7302292SN/A if (dispatchStatus[tid] == Unblocking) { 7312292SN/A any_unblocking = true; 7322292SN/A break; 7332292SN/A } 7342292SN/A } 7352292SN/A 7362292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7372292SN/A // and there's no stores waiting to write back, and dispatch is not 7382292SN/A // unblocking, then there is no internal activity for the IEW stage. 7392292SN/A instQueue.intInstQueueReads++; 7402292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7412292SN/A !ldstQueue.willWB() && !any_unblocking) { 7422292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7432292SN/A 7442292SN/A deactivateStage(); 7452292SN/A 7462292SN/A _status = Inactive; 7472292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7482292SN/A ldstQueue.willWB() || 7492292SN/A any_unblocking)) { 7502292SN/A // Otherwise there is internal activity. Set to active. 7512292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7522292SN/A 7532292SN/A activateStage(); 7542292SN/A 7552292SN/A _status = Active; 7562292SN/A } 7572292SN/A} 7582292SN/A 7592292SN/Atemplate <class Impl> 7602292SN/Avoid 7612292SN/ADefaultIEW<Impl>::resetEntries() 7622292SN/A{ 7632292SN/A instQueue.resetEntries(); 7642292SN/A ldstQueue.resetEntries(); 7652292SN/A} 7662292SN/A 7672292SN/Atemplate <class Impl> 7682292SN/Avoid 7692292SN/ADefaultIEW<Impl>::readStallSignals(ThreadID tid) 7702292SN/A{ 7712292SN/A if (fromCommit->commitBlock[tid]) { 7722292SN/A stalls[tid].commit = true; 7732292SN/A } 7742292SN/A 7752292SN/A if (fromCommit->commitUnblock[tid]) { 7762292SN/A assert(stalls[tid].commit); 7772292SN/A stalls[tid].commit = false; 7782292SN/A } 7792292SN/A} 7802292SN/A 7812292SN/Atemplate <class Impl> 7822292SN/Abool 7832292SN/ADefaultIEW<Impl>::checkStall(ThreadID tid) 7842292SN/A{ 7852292SN/A bool ret_val(false); 7862292SN/A 7872292SN/A if (stalls[tid].commit) { 7882292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7892292SN/A ret_val = true; 7902292SN/A } else if (instQueue.isFull(tid)) { 7912329SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7922329SN/A ret_val = true; 7932301SN/A } else if (ldstQueue.isFull(tid)) { 7942292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7952292SN/A 7962292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7972292SN/A 7982292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7992292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8002292SN/A } 8012292SN/A 8022292SN/A if (ldstQueue.numStores(tid) > 0) { 8032292SN/A 8042292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8052292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8062292SN/A } 8072292SN/A 8082292SN/A ret_val = true; 8092292SN/A } else if (ldstQueue.isStalled(tid)) { 8102301SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8112292SN/A ret_val = true; 8122292SN/A } 8132292SN/A 8142292SN/A return ret_val; 8152292SN/A} 8162292SN/A 8172292SN/Atemplate <class Impl> 8182292SN/Avoid 8192292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 8202292SN/A{ 8212292SN/A // Check if there's a squash signal, squash if there is 8222292SN/A // Check stall signals, block if there is. 8232292SN/A // If status was Blocked 8242292SN/A // if so then go to unblocking 8252292SN/A // If status was Squashing 8262292SN/A // check if squashing is not high. Switch to running this cycle. 8272292SN/A 8282292SN/A readStallSignals(tid); 8292292SN/A 8302292SN/A if (fromCommit->commitInfo[tid].squash) { 8312292SN/A squash(tid); 8321060SN/A 8331060SN/A if (dispatchStatus[tid] == Blocked || 8342292SN/A dispatchStatus[tid] == Unblocking) { 8351060SN/A toRename->iewUnblock[tid] = true; 8361060SN/A wroteToTimeBuffer = true; 8371060SN/A } 8381060SN/A 8391060SN/A dispatchStatus[tid] = Squashing; 8402292SN/A fetchRedirect[tid] = false; 8412292SN/A return; 8422292SN/A } 8431062SN/A 8442292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8452292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8461060SN/A 8472292SN/A dispatchStatus[tid] = Squashing; 8482292SN/A emptyRenameInsts(tid); 8492292SN/A wroteToTimeBuffer = true; 8501060SN/A return; 8512292SN/A } 8522292SN/A 8531062SN/A if (checkStall(tid)) { 8542292SN/A block(tid); 8551061SN/A dispatchStatus[tid] = Blocked; 8561062SN/A return; 8571060SN/A } 8581060SN/A 8591060SN/A if (dispatchStatus[tid] == Blocked) { 8601060SN/A // Status from previous cycle was blocked, but there are no more stall 8611060SN/A // conditions. Switch over to unblocking. 8622292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8631060SN/A tid); 8642292SN/A 8652292SN/A dispatchStatus[tid] = Unblocking; 8662292SN/A 8672292SN/A unblock(tid); 8682292SN/A 8691060SN/A return; 8701061SN/A } 8711060SN/A 8722292SN/A if (dispatchStatus[tid] == Squashing) { 8732292SN/A // Switch status to running if rename isn't being told to block or 8742292SN/A // squash this cycle. 8752292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8762292SN/A tid); 8772292SN/A 8781060SN/A dispatchStatus[tid] = Running; 8791060SN/A 8801060SN/A return; 8812292SN/A } 8822292SN/A} 8832292SN/A 8842292SN/Atemplate <class Impl> 8852292SN/Avoid 8862292SN/ADefaultIEW<Impl>::sortInsts() 8872292SN/A{ 8881060SN/A int insts_from_rename = fromRename->size; 8892329SN/A#ifdef DEBUG 8902329SN/A for (ThreadID tid = 0; tid < numThreads; tid++) 8912292SN/A assert(insts[tid].empty()); 8921061SN/A#endif 8932292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8942292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8951061SN/A } 8962292SN/A} 8971060SN/A 8981060SN/Atemplate <class Impl> 8991060SN/Avoid 9001061SN/ADefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 9011061SN/A{ 9022292SN/A DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 9031061SN/A 9042292SN/A while (!insts[tid].empty()) { 9052292SN/A 9061061SN/A if (insts[tid].front()->isLoad() || 9071061SN/A insts[tid].front()->isStore() ) { 9081061SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9091061SN/A } 9101061SN/A 9112292SN/A toRename->iewInfo[tid].dispatched++; 9121061SN/A 9131061SN/A insts[tid].pop(); 9141061SN/A } 9151061SN/A} 9162292SN/A 9171061SN/Atemplate <class Impl> 9182292SN/Avoid 9192292SN/ADefaultIEW<Impl>::wakeCPU() 9202292SN/A{ 9211061SN/A cpu->wakeCPU(); 9221061SN/A} 9231061SN/A 9242292SN/Atemplate <class Impl> 9252292SN/Avoid 9262292SN/ADefaultIEW<Impl>::activityThisCycle() 9271061SN/A{ 9281061SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9291061SN/A cpu->activityThisCycle(); 9301062SN/A} 9311062SN/A 9321061SN/Atemplate <class Impl> 9331061SN/Ainline void 9341061SN/ADefaultIEW<Impl>::activateStage() 9351061SN/A{ 9361061SN/A DPRINTF(Activity, "Activating stage.\n"); 9372292SN/A cpu->activateStage(O3CPU::IEWIdx); 9381061SN/A} 9392292SN/A 9401061SN/Atemplate <class Impl> 9411061SN/Ainline void 9421061SN/ADefaultIEW<Impl>::deactivateStage() 9432292SN/A{ 9442292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9452292SN/A cpu->deactivateStage(O3CPU::IEWIdx); 9461061SN/A} 9472292SN/A 9482292SN/Atemplate<class Impl> 9492292SN/Avoid 9501061SN/ADefaultIEW<Impl>::dispatch(ThreadID tid) 9512292SN/A{ 9522292SN/A // If status is Running or idle, 9531062SN/A // call dispatchInsts() 9542292SN/A // If status is Unblocking, 9552292SN/A // buffer any instructions coming from rename 9562292SN/A // continue trying to empty skid buffer 9571062SN/A // check if stall conditions have passed 9582292SN/A 9592292SN/A if (dispatchStatus[tid] == Blocked) { 9602292SN/A ++iewBlockCycles; 9612292SN/A 9621062SN/A } else if (dispatchStatus[tid] == Squashing) { 9632292SN/A ++iewSquashCycles; 9641062SN/A } 9652292SN/A 9662292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9672292SN/A // will allow, as long as it is not currently blocked. 9681062SN/A if (dispatchStatus[tid] == Running || 9692292SN/A dispatchStatus[tid] == Idle) { 9702292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9712292SN/A "dispatch.\n", tid); 9722292SN/A 9732292SN/A dispatchInsts(tid); 9742292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9752292SN/A // Make sure that the skid buffer has something in it if the 9762292SN/A // status is unblocking. 9771062SN/A assert(!skidsEmpty()); 9782292SN/A 9791061SN/A // If the status was unblocking, then instructions from the skid 9801061SN/A // buffer were used. Remove those instructions and handle 9811061SN/A // the rest of unblocking. 9821061SN/A dispatchInsts(tid); 9831061SN/A 9842292SN/A ++iewUnblockCycles; 9851061SN/A 9862292SN/A if (validInstsFromRename()) { 9872292SN/A // Add the current inputs to the skid buffer so they can be 9882292SN/A // reprocessed when this stage unblocks. 9892292SN/A skidInsert(tid); 9902292SN/A } 9912292SN/A 9921061SN/A unblock(tid); 9931061SN/A } 9941061SN/A} 9951061SN/A 9962292SN/Atemplate <class Impl> 9971061SN/Avoid 9982292SN/ADefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9992292SN/A{ 10002292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 10012292SN/A // otherwise. 10022292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 10032292SN/A dispatchStatus[tid] == Unblocking ? 10042292SN/A skidBuffer[tid] : insts[tid]; 10052292SN/A 10062292SN/A int insts_to_add = insts_to_dispatch.size(); 10072292SN/A 10082292SN/A DynInstPtr inst; 10092292SN/A bool add_to_iq = false; 10102292SN/A int dis_num_inst = 0; 10112292SN/A 10122292SN/A // Loop through the instructions, putting them in the instruction 10132292SN/A // queue. 10142292SN/A for ( ; dis_num_inst < insts_to_add && 10152292SN/A dis_num_inst < dispatchWidth; 10162292SN/A ++dis_num_inst) 10172292SN/A { 10182292SN/A inst = insts_to_dispatch.front(); 10192292SN/A 10202292SN/A if (dispatchStatus[tid] == Unblocking) { 10212292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10222292SN/A "buffer\n", tid); 10232292SN/A } 10242292SN/A 10252731Sktlim@umich.edu // Make sure there's a valid instruction there. 10262292SN/A assert(inst); 10272292SN/A 10282292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10292292SN/A "IQ.\n", 10302292SN/A tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10312292SN/A 10322292SN/A // Be sure to mark these instructions as ready so that the 10332292SN/A // commit stage can go ahead and execute them, and mark 10342292SN/A // them as issued so the IQ doesn't reprocess them. 10352292SN/A 10362292SN/A // Check for squashed instructions. 10372292SN/A if (inst->isSquashed()) { 10382292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10392292SN/A "not adding to IQ.\n", tid); 10402292SN/A 10412292SN/A ++iewDispSquashedInsts; 10422292SN/A 10432292SN/A insts_to_dispatch.pop(); 10442292SN/A 10452292SN/A //Tell Rename That An Instruction has been processed 10462292SN/A if (inst->isLoad() || inst->isStore()) { 10472292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10482292SN/A } 10492292SN/A toRename->iewInfo[tid].dispatched++; 10502292SN/A 10512292SN/A continue; 10522292SN/A } 10532292SN/A 10542292SN/A // Check for full conditions. 10552292SN/A if (instQueue.isFull(tid)) { 10562292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10572292SN/A 10582292SN/A // Call function to start blocking. 10592292SN/A block(tid); 10602292SN/A 10612292SN/A // Set unblock to false. Special case where we are using 10622292SN/A // skidbuffer (unblocking) instructions but then we still 10632292SN/A // get full in the IQ. 10642292SN/A toRename->iewUnblock[tid] = false; 10652292SN/A 10662292SN/A ++iewIQFullEvents; 10672292SN/A break; 10682292SN/A } else if (ldstQueue.isFull(tid)) { 10692292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10702292SN/A 10712292SN/A // Call function to start blocking. 10722292SN/A block(tid); 10732292SN/A 10742292SN/A // Set unblock to false. Special case where we are using 10752292SN/A // skidbuffer (unblocking) instructions but then we still 10762292SN/A // get full in the IQ. 10772292SN/A toRename->iewUnblock[tid] = false; 10782292SN/A 10792301SN/A ++iewLSQFullEvents; 10802292SN/A break; 10812301SN/A } 10822292SN/A 10832292SN/A // Otherwise issue the instruction just fine. 10842292SN/A if (inst->isLoad()) { 10852292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10862292SN/A "encountered, adding to LSQ.\n", tid); 10872292SN/A 10882292SN/A // Reserve a spot in the load store queue for this 10892292SN/A // memory access. 10902292SN/A ldstQueue.insertLoad(inst); 10912292SN/A 10922292SN/A ++iewDispLoadInsts; 10932292SN/A 10942292SN/A add_to_iq = true; 10952292SN/A 10962292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10972292SN/A } else if (inst->isStore()) { 10982292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10992292SN/A "encountered, adding to LSQ.\n", tid); 11002292SN/A 11012292SN/A ldstQueue.insertStore(inst); 11022292SN/A 11032292SN/A ++iewDispStoreInsts; 11042292SN/A 11052292SN/A if (inst->isStoreConditional()) { 11062292SN/A // Store conditionals need to be set as "canCommit()" 11072292SN/A // so that commit can process them when they reach the 11082292SN/A // head of commit. 11092292SN/A // @todo: This is somewhat specific to Alpha. 11102292SN/A inst->setCanCommit(); 11112292SN/A instQueue.insertNonSpec(inst); 11122292SN/A add_to_iq = false; 11132292SN/A 11142292SN/A ++iewDispNonSpecInsts; 11152292SN/A } else { 11162292SN/A add_to_iq = true; 11172292SN/A } 11182292SN/A 11192292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11202292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11212292SN/A // Same as non-speculative stores. 11222292SN/A inst->setCanCommit(); 11232292SN/A instQueue.insertBarrier(inst); 11242292SN/A add_to_iq = false; 11252292SN/A } else if (inst->isNop()) { 11262292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11272292SN/A "skipping.\n", tid); 11282292SN/A 11292292SN/A inst->setIssued(); 11302292SN/A inst->setExecuted(); 11312292SN/A inst->setCanCommit(); 11322292SN/A 11332292SN/A instQueue.recordProducer(inst); 11342292SN/A 11352301SN/A iewExecutedNop[tid]++; 11362292SN/A 11372292SN/A add_to_iq = false; 11382292SN/A } else if (inst->isExecuted()) { 11392292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11402292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11412292SN/A "skipping.\n"); 11422292SN/A 11432292SN/A inst->setIssued(); 11442292SN/A inst->setCanCommit(); 11452292SN/A 11462292SN/A instQueue.recordProducer(inst); 11472292SN/A 11482292SN/A add_to_iq = false; 11492292SN/A } else { 11502292SN/A add_to_iq = true; 11512292SN/A } 11522292SN/A if (inst->isNonSpeculative()) { 11532292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11542292SN/A "encountered, skipping.\n", tid); 11552292SN/A 11562292SN/A // Same as non-speculative stores. 11572292SN/A inst->setCanCommit(); 11582292SN/A 11592292SN/A // Specifically insert it as nonspeculative. 11602292SN/A instQueue.insertNonSpec(inst); 11612292SN/A 11622292SN/A ++iewDispNonSpecInsts; 11632292SN/A 11642292SN/A add_to_iq = false; 11652292SN/A } 11662292SN/A 11672292SN/A // If the instruction queue is not full, then add the 11682292SN/A // instruction. 11692292SN/A if (add_to_iq) { 11702292SN/A instQueue.insert(inst); 11712292SN/A } 11722292SN/A 11732292SN/A insts_to_dispatch.pop(); 11742292SN/A 11752292SN/A toRename->iewInfo[tid].dispatched++; 11762292SN/A 11772292SN/A ++iewDispatchedInsts; 11782292SN/A 11792292SN/A#if TRACING_ON 11802292SN/A inst->dispatchTick = curTick() - inst->fetchTick; 11812292SN/A#endif 11822292SN/A ppDispatch->notify(inst); 11832292SN/A } 11842301SN/A 11852292SN/A if (!insts_to_dispatch.empty()) { 11862301SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11872292SN/A block(tid); 11882292SN/A toRename->iewUnblock[tid] = false; 11892301SN/A } 11902292SN/A 11912292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11922292SN/A dispatchStatus[tid] = Running; 11932292SN/A 11942292SN/A updatedQueues = true; 11952292SN/A } 11962292SN/A 11972301SN/A dis_num_inst = 0; 11982292SN/A} 11992292SN/A 12002301SN/Atemplate <class Impl> 12012292SN/Avoid 12022292SN/ADefaultIEW<Impl>::printAvailableInsts() 12032301SN/A{ 12042292SN/A int inst = 0; 12052301SN/A 12062292SN/A std::cout << "Available Instructions: "; 12072292SN/A 12082292SN/A while (fromIssue->insts[inst]) { 12092703Sktlim@umich.edu 12102292SN/A if (inst%3==0) std::cout << "\n\t"; 12112301SN/A 12122292SN/A std::cout << "PC: " << fromIssue->insts[inst]->pcState() 12132292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12142292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12152292SN/A 12162292SN/A inst++; 12172292SN/A 12182292SN/A } 12191061SN/A 12201061SN/A std::cout << "\n"; 12211060SN/A} 12221060SN/A 12232292SN/Atemplate <class Impl> 12242292SN/Avoid 12251060SN/ADefaultIEW<Impl>::executeInsts() 12262292SN/A{ 12272292SN/A wbNumInst = 0; 12282292SN/A wbCycle = 0; 12291060SN/A 12301060SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 12311060SN/A list<ThreadID>::iterator end = activeThreads->end(); 12322292SN/A 12332292SN/A while (threads != end) { 12342292SN/A ThreadID tid = *threads++; 12352292SN/A fetchRedirect[tid] = false; 12362292SN/A } 12372292SN/A 12382292SN/A // Uncomment this if you want to see all available instructions. 12392292SN/A // @todo This doesn't actually work anymore, we should fix it. 12402292SN/A// printAvailableInsts(); 12412292SN/A 12422292SN/A // Execute/writeback any instructions that are available. 12432292SN/A int insts_to_execute = fromIssue->size; 12442292SN/A int inst_num = 0; 12452292SN/A for (; inst_num < insts_to_execute; 12462292SN/A ++inst_num) { 12472292SN/A 12482292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12492292SN/A 12502292SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12512292SN/A 12522292SN/A DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12531060SN/A inst->pcState(), inst->threadNumber,inst->seqNum); 12542292SN/A 12551060SN/A // Check if the instruction is squashed; if so then skip it 12562292SN/A if (inst->isSquashed()) { 12572292SN/A DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12582292SN/A " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12592292SN/A inst->seqNum); 12602292SN/A 12611060SN/A // Consider this instruction executed so that commit can go 12622292SN/A // ahead and retire the instruction. 12631060SN/A inst->setExecuted(); 12642292SN/A 12651060SN/A // Not sure if I should set this here or just let commit try to 12662292SN/A // commit any squashed instructions. I like the latter a bit more. 12672292SN/A inst->setCanCommit(); 12682292SN/A 12692292SN/A ++iewExecSquashedInsts; 12701060SN/A 12712292SN/A decrWb(inst->seqNum); 12721062SN/A continue; 12731060SN/A } 12741060SN/A 1275 Fault fault = NoFault; 1276 1277 // Execute instruction. 1278 // Note that if the instruction faults, it will be handled 1279 // at the commit stage. 1280 if (inst->isMemRef()) { 1281 DPRINTF(IEW, "Execute: Calculating address for memory " 1282 "reference.\n"); 1283 1284 // Tell the LDSTQ to execute this instruction (if it is a load). 1285 if (inst->isLoad()) { 1286 // Loads will mark themselves as executed, and their writeback 1287 // event adds the instruction to the queue to commit 1288 fault = ldstQueue.executeLoad(inst); 1289 1290 if (inst->isTranslationDelayed() && 1291 fault == NoFault) { 1292 // A hw page table walk is currently going on; the 1293 // instruction must be deferred. 1294 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1295 "load.\n"); 1296 instQueue.deferMemInst(inst); 1297 continue; 1298 } 1299 1300 if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 1301 inst->fault = NoFault; 1302 } 1303 } else if (inst->isStore()) { 1304 fault = ldstQueue.executeStore(inst); 1305 1306 if (inst->isTranslationDelayed() && 1307 fault == NoFault) { 1308 // A hw page table walk is currently going on; the 1309 // instruction must be deferred. 1310 DPRINTF(IEW, "Execute: Delayed translation, deferring " 1311 "store.\n"); 1312 instQueue.deferMemInst(inst); 1313 continue; 1314 } 1315 1316 // If the store had a fault then it may not have a mem req 1317 if (fault != NoFault || !inst->readPredicate() || 1318 !inst->isStoreConditional()) { 1319 // If the instruction faulted, then we need to send it along 1320 // to commit without the instruction completing. 1321 // Send this instruction to commit, also make sure iew stage 1322 // realizes there is activity. 1323 inst->setExecuted(); 1324 instToCommit(inst); 1325 activityThisCycle(); 1326 } 1327 1328 // Store conditionals will mark themselves as 1329 // executed, and their writeback event will add the 1330 // instruction to the queue to commit. 1331 } else { 1332 panic("Unexpected memory type!\n"); 1333 } 1334 1335 } else { 1336 // If the instruction has already faulted, then skip executing it. 1337 // Such case can happen when it faulted during ITLB translation. 1338 // If we execute the instruction (even if it's a nop) the fault 1339 // will be replaced and we will lose it. 1340 if (inst->getFault() == NoFault) { 1341 inst->execute(); 1342 if (!inst->readPredicate()) 1343 inst->forwardOldRegs(); 1344 } 1345 1346 inst->setExecuted(); 1347 1348 instToCommit(inst); 1349 } 1350 1351 updateExeInstStats(inst); 1352 1353 // Check if branch prediction was correct, if not then we need 1354 // to tell commit to squash in flight instructions. Only 1355 // handle this if there hasn't already been something that 1356 // redirects fetch in this group of instructions. 1357 1358 // This probably needs to prioritize the redirects if a different 1359 // scheduler is used. Currently the scheduler schedules the oldest 1360 // instruction first, so the branch resolution order will be correct. 1361 ThreadID tid = inst->threadNumber; 1362 1363 if (!fetchRedirect[tid] || 1364 !toCommit->squash[tid] || 1365 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1366 1367 // Prevent testing for misprediction on load instructions, 1368 // that have not been executed. 1369 bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 1370 1371 if (inst->mispredicted() && !loadNotExecuted) { 1372 fetchRedirect[tid] = true; 1373 1374 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1375 DPRINTF(IEW, "Predicted target was PC: %s.\n", 1376 inst->readPredTarg()); 1377 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 1378 inst->pcState()); 1379 // If incorrect, then signal the ROB that it must be squashed. 1380 squashDueToBranch(inst, tid); 1381 1382 ppMispredict->notify(inst); 1383 1384 if (inst->readPredTaken()) { 1385 predictedTakenIncorrect++; 1386 } else { 1387 predictedNotTakenIncorrect++; 1388 } 1389 } else if (ldstQueue.violation(tid)) { 1390 assert(inst->isMemRef()); 1391 // If there was an ordering violation, then get the 1392 // DynInst that caused the violation. Note that this 1393 // clears the violation signal. 1394 DynInstPtr violator; 1395 violator = ldstQueue.getMemDepViolator(tid); 1396 1397 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 1398 "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 1399 violator->pcState(), violator->seqNum, 1400 inst->pcState(), inst->seqNum, inst->physEffAddr); 1401 1402 fetchRedirect[tid] = true; 1403 1404 // Tell the instruction queue that a violation has occured. 1405 instQueue.violation(inst, violator); 1406 1407 // Squash. 1408 squashDueToMemOrder(violator, tid); 1409 1410 ++memOrderViolationEvents; 1411 } else if (ldstQueue.loadBlocked(tid) && 1412 !ldstQueue.isLoadBlockedHandled(tid)) { 1413 fetchRedirect[tid] = true; 1414 1415 DPRINTF(IEW, "Load operation couldn't execute because the " 1416 "memory system is blocked. PC: %s [sn:%lli]\n", 1417 inst->pcState(), inst->seqNum); 1418 1419 squashDueToMemBlocked(inst, tid); 1420 } 1421 } else { 1422 // Reset any state associated with redirects that will not 1423 // be used. 1424 if (ldstQueue.violation(tid)) { 1425 assert(inst->isMemRef()); 1426 1427 DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 1428 1429 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1430 "%s, inst PC: %s. Addr is: %#x.\n", 1431 violator->pcState(), inst->pcState(), 1432 inst->physEffAddr); 1433 DPRINTF(IEW, "Violation will not be handled because " 1434 "already squashing\n"); 1435 1436 ++memOrderViolationEvents; 1437 } 1438 if (ldstQueue.loadBlocked(tid) && 1439 !ldstQueue.isLoadBlockedHandled(tid)) { 1440 DPRINTF(IEW, "Load operation couldn't execute because the " 1441 "memory system is blocked. PC: %s [sn:%lli]\n", 1442 inst->pcState(), inst->seqNum); 1443 DPRINTF(IEW, "Blocked load will not be handled because " 1444 "already squashing\n"); 1445 1446 ldstQueue.setLoadBlockedHandled(tid); 1447 } 1448 1449 } 1450 } 1451 1452 // Update and record activity if we processed any instructions. 1453 if (inst_num) { 1454 if (exeStatus == Idle) { 1455 exeStatus = Running; 1456 } 1457 1458 updatedQueues = true; 1459 1460 cpu->activityThisCycle(); 1461 } 1462 1463 // Need to reset this in case a writeback event needs to write into the 1464 // iew queue. That way the writeback event will write into the correct 1465 // spot in the queue. 1466 wbNumInst = 0; 1467 1468} 1469 1470template <class Impl> 1471void 1472DefaultIEW<Impl>::writebackInsts() 1473{ 1474 // Loop through the head of the time buffer and wake any 1475 // dependents. These instructions are about to write back. Also 1476 // mark scoreboard that this instruction is finally complete. 1477 // Either have IEW have direct access to scoreboard, or have this 1478 // as part of backwards communication. 1479 for (int inst_num = 0; inst_num < wbWidth && 1480 toCommit->insts[inst_num]; inst_num++) { 1481 DynInstPtr inst = toCommit->insts[inst_num]; 1482 ThreadID tid = inst->threadNumber; 1483 1484 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 1485 inst->seqNum, inst->pcState()); 1486 1487 iewInstsToCommit[tid]++; 1488 1489 // Some instructions will be sent to commit without having 1490 // executed because they need commit to handle them. 1491 // E.g. Uncached loads have not actually executed when they 1492 // are first sent to commit. Instead commit must tell the LSQ 1493 // when it's ready to execute the uncached load. 1494 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1495 int dependents = instQueue.wakeDependents(inst); 1496 1497 for (int i = 0; i < inst->numDestRegs(); i++) { 1498 //mark as Ready 1499 DPRINTF(IEW,"Setting Destination Register %i\n", 1500 inst->renamedDestRegIdx(i)); 1501 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1502 } 1503 1504 if (dependents) { 1505 producerInst[tid]++; 1506 consumerInst[tid]+= dependents; 1507 } 1508 writebackCount[tid]++; 1509 } 1510 1511 decrWb(inst->seqNum); 1512 } 1513} 1514 1515template<class Impl> 1516void 1517DefaultIEW<Impl>::tick() 1518{ 1519 wbNumInst = 0; 1520 wbCycle = 0; 1521 1522 wroteToTimeBuffer = false; 1523 updatedQueues = false; 1524 1525 sortInsts(); 1526 1527 // Free function units marked as being freed this cycle. 1528 fuPool->processFreeUnits(); 1529 1530 list<ThreadID>::iterator threads = activeThreads->begin(); 1531 list<ThreadID>::iterator end = activeThreads->end(); 1532 1533 // Check stall and squash signals, dispatch any instructions. 1534 while (threads != end) { 1535 ThreadID tid = *threads++; 1536 1537 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1538 1539 checkSignalsAndUpdate(tid); 1540 dispatch(tid); 1541 } 1542 1543 if (exeStatus != Squashing) { 1544 executeInsts(); 1545 1546 writebackInsts(); 1547 1548 // Have the instruction queue try to schedule any ready instructions. 1549 // (In actuality, this scheduling is for instructions that will 1550 // be executed next cycle.) 1551 instQueue.scheduleReadyInsts(); 1552 1553 // Also should advance its own time buffers if the stage ran. 1554 // Not the best place for it, but this works (hopefully). 1555 issueToExecQueue.advance(); 1556 } 1557 1558 bool broadcast_free_entries = false; 1559 1560 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1561 exeStatus = Idle; 1562 updateLSQNextCycle = false; 1563 1564 broadcast_free_entries = true; 1565 } 1566 1567 // Writeback any stores using any leftover bandwidth. 1568 ldstQueue.writebackStores(); 1569 1570 // Check the committed load/store signals to see if there's a load 1571 // or store to commit. Also check if it's being told to execute a 1572 // nonspeculative instruction. 1573 // This is pretty inefficient... 1574 1575 threads = activeThreads->begin(); 1576 while (threads != end) { 1577 ThreadID tid = (*threads++); 1578 1579 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1580 1581 // Update structures based on instructions committed. 1582 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1583 !fromCommit->commitInfo[tid].squash && 1584 !fromCommit->commitInfo[tid].robSquashing) { 1585 1586 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1587 1588 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1589 1590 updateLSQNextCycle = true; 1591 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1592 } 1593 1594 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1595 1596 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1597 if (fromCommit->commitInfo[tid].uncached) { 1598 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1599 fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 1600 } else { 1601 instQueue.scheduleNonSpec( 1602 fromCommit->commitInfo[tid].nonSpecSeqNum); 1603 } 1604 } 1605 1606 if (broadcast_free_entries) { 1607 toFetch->iewInfo[tid].iqCount = 1608 instQueue.getCount(tid); 1609 toFetch->iewInfo[tid].ldstqCount = 1610 ldstQueue.getCount(tid); 1611 1612 toRename->iewInfo[tid].usedIQ = true; 1613 toRename->iewInfo[tid].freeIQEntries = 1614 instQueue.numFreeEntries(tid); 1615 toRename->iewInfo[tid].usedLSQ = true; 1616 toRename->iewInfo[tid].freeLSQEntries = 1617 ldstQueue.numFreeEntries(tid); 1618 1619 wroteToTimeBuffer = true; 1620 } 1621 1622 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1623 tid, toRename->iewInfo[tid].dispatched); 1624 } 1625 1626 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1627 "LSQ has %i free entries.\n", 1628 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1629 ldstQueue.numFreeEntries()); 1630 1631 updateStatus(); 1632 1633 if (wroteToTimeBuffer) { 1634 DPRINTF(Activity, "Activity this cycle.\n"); 1635 cpu->activityThisCycle(); 1636 } 1637} 1638 1639template <class Impl> 1640void 1641DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1642{ 1643 ThreadID tid = inst->threadNumber; 1644 1645 iewExecutedInsts++; 1646 1647#if TRACING_ON 1648 if (DTRACE(O3PipeView)) { 1649 inst->completeTick = curTick() - inst->fetchTick; 1650 } 1651#endif 1652 1653 // 1654 // Control operations 1655 // 1656 if (inst->isControl()) 1657 iewExecutedBranches[tid]++; 1658 1659 // 1660 // Memory operations 1661 // 1662 if (inst->isMemRef()) { 1663 iewExecutedRefs[tid]++; 1664 1665 if (inst->isLoad()) { 1666 iewExecLoadInsts[tid]++; 1667 } 1668 } 1669} 1670 1671template <class Impl> 1672void 1673DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 1674{ 1675 ThreadID tid = inst->threadNumber; 1676 1677 if (!fetchRedirect[tid] || 1678 !toCommit->squash[tid] || 1679 toCommit->squashedSeqNum[tid] > inst->seqNum) { 1680 1681 if (inst->mispredicted()) { 1682 fetchRedirect[tid] = true; 1683 1684 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1685 DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 1686 inst->predInstAddr(), inst->predNextInstAddr()); 1687 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 1688 " NPC: %#x.\n", inst->nextInstAddr(), 1689 inst->nextInstAddr()); 1690 // If incorrect, then signal the ROB that it must be squashed. 1691 squashDueToBranch(inst, tid); 1692 1693 if (inst->readPredTaken()) { 1694 predictedTakenIncorrect++; 1695 } else { 1696 predictedNotTakenIncorrect++; 1697 } 1698 } 1699 } 1700} 1701 1702#endif//__CPU_O3_IEW_IMPL_IMPL_HH__ 1703