fetch_impl.hh revision 9814:7ad2b0186a32 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46#include <list>
47#include <map>
48#include <queue>
49
50#include "arch/isa_traits.hh"
51#include "arch/tlb.hh"
52#include "arch/utility.hh"
53#include "arch/vtophys.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/base.hh"
57//#include "cpu/checker/cpu.hh"
58#include "cpu/o3/fetch.hh"
59#include "cpu/exetrace.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/Fetch.hh"
63#include "debug/O3PipeView.hh"
64#include "mem/packet.hh"
65#include "params/DerivO3CPU.hh"
66#include "sim/byteswap.hh"
67#include "sim/core.hh"
68#include "sim/eventq.hh"
69#include "sim/full_system.hh"
70#include "sim/system.hh"
71
72using namespace std;
73
74template<class Impl>
75DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
76    : cpu(_cpu),
77      decodeToFetchDelay(params->decodeToFetchDelay),
78      renameToFetchDelay(params->renameToFetchDelay),
79      iewToFetchDelay(params->iewToFetchDelay),
80      commitToFetchDelay(params->commitToFetchDelay),
81      fetchWidth(params->fetchWidth),
82      retryPkt(NULL),
83      retryTid(InvalidThreadID),
84      cacheBlkSize(cpu->cacheLineSize()),
85      cacheBlkMask(cacheBlkSize - 1),
86      numThreads(params->numThreads),
87      numFetchingThreads(params->smtNumFetchingThreads),
88      finishTranslationEvent(this)
89{
90    if (numThreads > Impl::MaxThreads)
91        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
92              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
93              numThreads, static_cast<int>(Impl::MaxThreads));
94    if (fetchWidth > Impl::MaxWidth)
95        fatal("fetchWidth (%d) is larger than compiled limit (%d),\n"
96             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
97             fetchWidth, static_cast<int>(Impl::MaxWidth));
98
99    std::string policy = params->smtFetchPolicy;
100
101    // Convert string to lowercase
102    std::transform(policy.begin(), policy.end(), policy.begin(),
103                   (int(*)(int)) tolower);
104
105    // Figure out fetch policy
106    if (policy == "singlethread") {
107        fetchPolicy = SingleThread;
108        if (numThreads > 1)
109            panic("Invalid Fetch Policy for a SMT workload.");
110    } else if (policy == "roundrobin") {
111        fetchPolicy = RoundRobin;
112        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
113    } else if (policy == "branch") {
114        fetchPolicy = Branch;
115        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
116    } else if (policy == "iqcount") {
117        fetchPolicy = IQ;
118        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
119    } else if (policy == "lsqcount") {
120        fetchPolicy = LSQ;
121        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
122    } else {
123        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
124              " RoundRobin,LSQcount,IQcount}\n");
125    }
126
127    // Get the size of an instruction.
128    instSize = sizeof(TheISA::MachInst);
129
130    for (int i = 0; i < Impl::MaxThreads; i++) {
131        decoder[i] = new TheISA::Decoder;
132    }
133
134    branchPred = params->branchPred;
135
136    for (ThreadID tid = 0; tid < numThreads; tid++) {
137        // Create space to store a cache line.
138        cacheData[tid] = new uint8_t[cacheBlkSize];
139        cacheDataPC[tid] = 0;
140        cacheDataValid[tid] = false;
141    }
142}
143
144template <class Impl>
145std::string
146DefaultFetch<Impl>::name() const
147{
148    return cpu->name() + ".fetch";
149}
150
151template <class Impl>
152void
153DefaultFetch<Impl>::regStats()
154{
155    icacheStallCycles
156        .name(name() + ".icacheStallCycles")
157        .desc("Number of cycles fetch is stalled on an Icache miss")
158        .prereq(icacheStallCycles);
159
160    fetchedInsts
161        .name(name() + ".Insts")
162        .desc("Number of instructions fetch has processed")
163        .prereq(fetchedInsts);
164
165    fetchedBranches
166        .name(name() + ".Branches")
167        .desc("Number of branches that fetch encountered")
168        .prereq(fetchedBranches);
169
170    predictedBranches
171        .name(name() + ".predictedBranches")
172        .desc("Number of branches that fetch has predicted taken")
173        .prereq(predictedBranches);
174
175    fetchCycles
176        .name(name() + ".Cycles")
177        .desc("Number of cycles fetch has run and was not squashing or"
178              " blocked")
179        .prereq(fetchCycles);
180
181    fetchSquashCycles
182        .name(name() + ".SquashCycles")
183        .desc("Number of cycles fetch has spent squashing")
184        .prereq(fetchSquashCycles);
185
186    fetchTlbCycles
187        .name(name() + ".TlbCycles")
188        .desc("Number of cycles fetch has spent waiting for tlb")
189        .prereq(fetchTlbCycles);
190
191    fetchIdleCycles
192        .name(name() + ".IdleCycles")
193        .desc("Number of cycles fetch was idle")
194        .prereq(fetchIdleCycles);
195
196    fetchBlockedCycles
197        .name(name() + ".BlockedCycles")
198        .desc("Number of cycles fetch has spent blocked")
199        .prereq(fetchBlockedCycles);
200
201    fetchedCacheLines
202        .name(name() + ".CacheLines")
203        .desc("Number of cache lines fetched")
204        .prereq(fetchedCacheLines);
205
206    fetchMiscStallCycles
207        .name(name() + ".MiscStallCycles")
208        .desc("Number of cycles fetch has spent waiting on interrupts, or "
209              "bad addresses, or out of MSHRs")
210        .prereq(fetchMiscStallCycles);
211
212    fetchPendingDrainCycles
213        .name(name() + ".PendingDrainCycles")
214        .desc("Number of cycles fetch has spent waiting on pipes to drain")
215        .prereq(fetchPendingDrainCycles);
216
217    fetchNoActiveThreadStallCycles
218        .name(name() + ".NoActiveThreadStallCycles")
219        .desc("Number of stall cycles due to no active thread to fetch from")
220        .prereq(fetchNoActiveThreadStallCycles);
221
222    fetchPendingTrapStallCycles
223        .name(name() + ".PendingTrapStallCycles")
224        .desc("Number of stall cycles due to pending traps")
225        .prereq(fetchPendingTrapStallCycles);
226
227    fetchPendingQuiesceStallCycles
228        .name(name() + ".PendingQuiesceStallCycles")
229        .desc("Number of stall cycles due to pending quiesce instructions")
230        .prereq(fetchPendingQuiesceStallCycles);
231
232    fetchIcacheWaitRetryStallCycles
233        .name(name() + ".IcacheWaitRetryStallCycles")
234        .desc("Number of stall cycles due to full MSHR")
235        .prereq(fetchIcacheWaitRetryStallCycles);
236
237    fetchIcacheSquashes
238        .name(name() + ".IcacheSquashes")
239        .desc("Number of outstanding Icache misses that were squashed")
240        .prereq(fetchIcacheSquashes);
241
242    fetchTlbSquashes
243        .name(name() + ".ItlbSquashes")
244        .desc("Number of outstanding ITLB misses that were squashed")
245        .prereq(fetchTlbSquashes);
246
247    fetchNisnDist
248        .init(/* base value */ 0,
249              /* last value */ fetchWidth,
250              /* bucket size */ 1)
251        .name(name() + ".rateDist")
252        .desc("Number of instructions fetched each cycle (Total)")
253        .flags(Stats::pdf);
254
255    idleRate
256        .name(name() + ".idleRate")
257        .desc("Percent of cycles fetch was idle")
258        .prereq(idleRate);
259    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
260
261    branchRate
262        .name(name() + ".branchRate")
263        .desc("Number of branch fetches per cycle")
264        .flags(Stats::total);
265    branchRate = fetchedBranches / cpu->numCycles;
266
267    fetchRate
268        .name(name() + ".rate")
269        .desc("Number of inst fetches per cycle")
270        .flags(Stats::total);
271    fetchRate = fetchedInsts / cpu->numCycles;
272}
273
274template<class Impl>
275void
276DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
277{
278    timeBuffer = time_buffer;
279
280    // Create wires to get information from proper places in time buffer.
281    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
282    fromRename = timeBuffer->getWire(-renameToFetchDelay);
283    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
284    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
285}
286
287template<class Impl>
288void
289DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
290{
291    activeThreads = at_ptr;
292}
293
294template<class Impl>
295void
296DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
297{
298    fetchQueue = fq_ptr;
299
300    // Create wire to write information to proper place in fetch queue.
301    toDecode = fetchQueue->getWire(0);
302}
303
304template<class Impl>
305void
306DefaultFetch<Impl>::startupStage()
307{
308    assert(priorityList.empty());
309    resetStage();
310
311    // Fetch needs to start fetching instructions at the very beginning,
312    // so it must start up in active state.
313    switchToActive();
314}
315
316template<class Impl>
317void
318DefaultFetch<Impl>::resetStage()
319{
320    numInst = 0;
321    interruptPending = false;
322    cacheBlocked = false;
323
324    priorityList.clear();
325
326    // Setup PC and nextPC with initial state.
327    for (ThreadID tid = 0; tid < numThreads; tid++) {
328        fetchStatus[tid] = Running;
329        pc[tid] = cpu->pcState(tid);
330        fetchOffset[tid] = 0;
331        macroop[tid] = NULL;
332
333        delayedCommit[tid] = false;
334        memReq[tid] = NULL;
335
336        stalls[tid].decode = false;
337        stalls[tid].rename = false;
338        stalls[tid].iew = false;
339        stalls[tid].commit = false;
340        stalls[tid].drain = false;
341
342        priorityList.push_back(tid);
343    }
344
345    wroteToTimeBuffer = false;
346    _status = Inactive;
347}
348
349template<class Impl>
350void
351DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
352{
353    ThreadID tid = pkt->req->threadId();
354
355    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
356    assert(!cpu->switchedOut());
357
358    // Only change the status if it's still waiting on the icache access
359    // to return.
360    if (fetchStatus[tid] != IcacheWaitResponse ||
361        pkt->req != memReq[tid]) {
362        ++fetchIcacheSquashes;
363        delete pkt->req;
364        delete pkt;
365        return;
366    }
367
368    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
369    cacheDataValid[tid] = true;
370
371    // Wake up the CPU (if it went to sleep and was waiting on
372    // this completion event).
373    cpu->wakeCPU();
374
375    DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
376            tid);
377
378    switchToActive();
379
380    // Only switch to IcacheAccessComplete if we're not stalled as well.
381    if (checkStall(tid)) {
382        fetchStatus[tid] = Blocked;
383    } else {
384        fetchStatus[tid] = IcacheAccessComplete;
385    }
386
387    // Reset the mem req to NULL.
388    delete pkt->req;
389    delete pkt;
390    memReq[tid] = NULL;
391}
392
393template <class Impl>
394void
395DefaultFetch<Impl>::drainResume()
396{
397    for (ThreadID i = 0; i < Impl::MaxThreads; ++i)
398        stalls[i].drain = false;
399}
400
401template <class Impl>
402void
403DefaultFetch<Impl>::drainSanityCheck() const
404{
405    assert(isDrained());
406    assert(retryPkt == NULL);
407    assert(retryTid == InvalidThreadID);
408    assert(cacheBlocked == false);
409    assert(interruptPending == false);
410
411    for (ThreadID i = 0; i < numThreads; ++i) {
412        assert(!memReq[i]);
413        assert(!stalls[i].decode);
414        assert(!stalls[i].rename);
415        assert(!stalls[i].iew);
416        assert(!stalls[i].commit);
417        assert(fetchStatus[i] == Idle || stalls[i].drain);
418    }
419
420    branchPred->drainSanityCheck();
421}
422
423template <class Impl>
424bool
425DefaultFetch<Impl>::isDrained() const
426{
427    /* Make sure that threads are either idle of that the commit stage
428     * has signaled that draining has completed by setting the drain
429     * stall flag. This effectively forces the pipeline to be disabled
430     * until the whole system is drained (simulation may continue to
431     * drain other components).
432     */
433    for (ThreadID i = 0; i < numThreads; ++i) {
434        if (!(fetchStatus[i] == Idle ||
435              (fetchStatus[i] == Blocked && stalls[i].drain)))
436            return false;
437    }
438
439    /* The pipeline might start up again in the middle of the drain
440     * cycle if the finish translation event is scheduled, so make
441     * sure that's not the case.
442     */
443    return !finishTranslationEvent.scheduled();
444}
445
446template <class Impl>
447void
448DefaultFetch<Impl>::takeOverFrom()
449{
450    assert(cpu->getInstPort().isConnected());
451    resetStage();
452
453}
454
455template <class Impl>
456void
457DefaultFetch<Impl>::drainStall(ThreadID tid)
458{
459    assert(cpu->isDraining());
460    assert(!stalls[tid].drain);
461    DPRINTF(Drain, "%i: Thread drained.\n", tid);
462    stalls[tid].drain = true;
463}
464
465template <class Impl>
466void
467DefaultFetch<Impl>::wakeFromQuiesce()
468{
469    DPRINTF(Fetch, "Waking up from quiesce\n");
470    // Hopefully this is safe
471    // @todo: Allow other threads to wake from quiesce.
472    fetchStatus[0] = Running;
473}
474
475template <class Impl>
476inline void
477DefaultFetch<Impl>::switchToActive()
478{
479    if (_status == Inactive) {
480        DPRINTF(Activity, "Activating stage.\n");
481
482        cpu->activateStage(O3CPU::FetchIdx);
483
484        _status = Active;
485    }
486}
487
488template <class Impl>
489inline void
490DefaultFetch<Impl>::switchToInactive()
491{
492    if (_status == Active) {
493        DPRINTF(Activity, "Deactivating stage.\n");
494
495        cpu->deactivateStage(O3CPU::FetchIdx);
496
497        _status = Inactive;
498    }
499}
500
501template <class Impl>
502bool
503DefaultFetch<Impl>::lookupAndUpdateNextPC(
504        DynInstPtr &inst, TheISA::PCState &nextPC)
505{
506    // Do branch prediction check here.
507    // A bit of a misnomer...next_PC is actually the current PC until
508    // this function updates it.
509    bool predict_taken;
510
511    if (!inst->isControl()) {
512        TheISA::advancePC(nextPC, inst->staticInst);
513        inst->setPredTarg(nextPC);
514        inst->setPredTaken(false);
515        return false;
516    }
517
518    ThreadID tid = inst->threadNumber;
519    predict_taken = branchPred->predict(inst->staticInst, inst->seqNum,
520                                        nextPC, tid);
521
522    if (predict_taken) {
523        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
524                tid, inst->seqNum, nextPC);
525    } else {
526        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
527                tid, inst->seqNum);
528    }
529
530    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
531            tid, inst->seqNum, nextPC);
532    inst->setPredTarg(nextPC);
533    inst->setPredTaken(predict_taken);
534
535    ++fetchedBranches;
536
537    if (predict_taken) {
538        ++predictedBranches;
539    }
540
541    return predict_taken;
542}
543
544template <class Impl>
545bool
546DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
547{
548    Fault fault = NoFault;
549
550    assert(!cpu->switchedOut());
551
552    // @todo: not sure if these should block translation.
553    //AlphaDep
554    if (cacheBlocked) {
555        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
556                tid);
557        return false;
558    } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
559        // Hold off fetch from getting new instructions when:
560        // Cache is blocked, or
561        // while an interrupt is pending and we're not in PAL mode, or
562        // fetch is switched out.
563        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
564                tid);
565        return false;
566    }
567
568    // Align the fetch address so it's at the start of a cache block.
569    Addr block_PC = icacheBlockAlignPC(vaddr);
570
571    DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
572            tid, block_PC, vaddr);
573
574    // Setup the memReq to do a read of the first instruction's address.
575    // Set the appropriate read size and flags as well.
576    // Build request here.
577    RequestPtr mem_req =
578        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
579                    cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid);
580
581    memReq[tid] = mem_req;
582
583    // Initiate translation of the icache block
584    fetchStatus[tid] = ItlbWait;
585    FetchTranslation *trans = new FetchTranslation(this);
586    cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
587                              trans, BaseTLB::Execute);
588    return true;
589}
590
591template <class Impl>
592void
593DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
594{
595    ThreadID tid = mem_req->threadId();
596    Addr block_PC = mem_req->getVaddr();
597
598    assert(!cpu->switchedOut());
599
600    // Wake up CPU if it was idle
601    cpu->wakeCPU();
602
603    if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
604        mem_req->getVaddr() != memReq[tid]->getVaddr()) {
605        DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
606                tid);
607        ++fetchTlbSquashes;
608        delete mem_req;
609        return;
610    }
611
612
613    // If translation was successful, attempt to read the icache block.
614    if (fault == NoFault) {
615        // Check that we're not going off into random memory
616        // If we have, just wait around for commit to squash something and put
617        // us on the right track
618        if (!cpu->system->isMemAddr(mem_req->getPaddr())) {
619            warn("Address %#x is outside of physical memory, stopping fetch\n",
620                    mem_req->getPaddr());
621            fetchStatus[tid] = NoGoodAddr;
622            delete mem_req;
623            memReq[tid] = NULL;
624            return;
625        }
626
627        // Build packet here.
628        PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
629        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
630
631        cacheDataPC[tid] = block_PC;
632        cacheDataValid[tid] = false;
633        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
634
635        fetchedCacheLines++;
636
637        // Access the cache.
638        if (!cpu->getInstPort().sendTimingReq(data_pkt)) {
639            assert(retryPkt == NULL);
640            assert(retryTid == InvalidThreadID);
641            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
642
643            fetchStatus[tid] = IcacheWaitRetry;
644            retryPkt = data_pkt;
645            retryTid = tid;
646            cacheBlocked = true;
647        } else {
648            DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
649            DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
650                    "response.\n", tid);
651
652            lastIcacheStall[tid] = curTick();
653            fetchStatus[tid] = IcacheWaitResponse;
654        }
655    } else {
656        if (!(numInst < fetchWidth)) {
657            assert(!finishTranslationEvent.scheduled());
658            finishTranslationEvent.setFault(fault);
659            finishTranslationEvent.setReq(mem_req);
660            cpu->schedule(finishTranslationEvent,
661                          cpu->clockEdge(Cycles(1)));
662            return;
663        }
664        DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
665                tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
666        // Translation faulted, icache request won't be sent.
667        delete mem_req;
668        memReq[tid] = NULL;
669
670        // Send the fault to commit.  This thread will not do anything
671        // until commit handles the fault.  The only other way it can
672        // wake up is if a squash comes along and changes the PC.
673        TheISA::PCState fetchPC = pc[tid];
674
675        DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
676        // We will use a nop in ordier to carry the fault.
677        DynInstPtr instruction = buildInst(tid,
678                decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()),
679                NULL, fetchPC, fetchPC, false);
680
681        instruction->setPredTarg(fetchPC);
682        instruction->fault = fault;
683        wroteToTimeBuffer = true;
684
685        DPRINTF(Activity, "Activity this cycle.\n");
686        cpu->activityThisCycle();
687
688        fetchStatus[tid] = TrapPending;
689
690        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
691        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
692                tid, fault->name(), pc[tid]);
693    }
694    _status = updateFetchStatus();
695}
696
697template <class Impl>
698inline void
699DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
700                             const DynInstPtr squashInst, ThreadID tid)
701{
702    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
703            tid, newPC);
704
705    pc[tid] = newPC;
706    fetchOffset[tid] = 0;
707    if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
708        macroop[tid] = squashInst->macroop;
709    else
710        macroop[tid] = NULL;
711    decoder[tid]->reset();
712
713    // Clear the icache miss if it's outstanding.
714    if (fetchStatus[tid] == IcacheWaitResponse) {
715        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
716                tid);
717        memReq[tid] = NULL;
718    } else if (fetchStatus[tid] == ItlbWait) {
719        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
720                tid);
721        memReq[tid] = NULL;
722    }
723
724    // Get rid of the retrying packet if it was from this thread.
725    if (retryTid == tid) {
726        assert(cacheBlocked);
727        if (retryPkt) {
728            delete retryPkt->req;
729            delete retryPkt;
730        }
731        retryPkt = NULL;
732        retryTid = InvalidThreadID;
733    }
734
735    fetchStatus[tid] = Squashing;
736
737    // microops are being squashed, it is not known wheather the
738    // youngest non-squashed microop was  marked delayed commit
739    // or not. Setting the flag to true ensures that the
740    // interrupts are not handled when they cannot be, though
741    // some opportunities to handle interrupts may be missed.
742    delayedCommit[tid] = true;
743
744    ++fetchSquashCycles;
745}
746
747template<class Impl>
748void
749DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
750                                     const DynInstPtr squashInst,
751                                     const InstSeqNum seq_num, ThreadID tid)
752{
753    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
754
755    doSquash(newPC, squashInst, tid);
756
757    // Tell the CPU to remove any instructions that are in flight between
758    // fetch and decode.
759    cpu->removeInstsUntil(seq_num, tid);
760}
761
762template<class Impl>
763bool
764DefaultFetch<Impl>::checkStall(ThreadID tid) const
765{
766    bool ret_val = false;
767
768    if (cpu->contextSwitch) {
769        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
770        ret_val = true;
771    } else if (stalls[tid].drain) {
772        assert(cpu->isDraining());
773        DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid);
774        ret_val = true;
775    } else if (stalls[tid].decode) {
776        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
777        ret_val = true;
778    } else if (stalls[tid].rename) {
779        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
780        ret_val = true;
781    } else if (stalls[tid].iew) {
782        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
783        ret_val = true;
784    } else if (stalls[tid].commit) {
785        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
786        ret_val = true;
787    }
788
789    return ret_val;
790}
791
792template<class Impl>
793typename DefaultFetch<Impl>::FetchStatus
794DefaultFetch<Impl>::updateFetchStatus()
795{
796    //Check Running
797    list<ThreadID>::iterator threads = activeThreads->begin();
798    list<ThreadID>::iterator end = activeThreads->end();
799
800    while (threads != end) {
801        ThreadID tid = *threads++;
802
803        if (fetchStatus[tid] == Running ||
804            fetchStatus[tid] == Squashing ||
805            fetchStatus[tid] == IcacheAccessComplete) {
806
807            if (_status == Inactive) {
808                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
809
810                if (fetchStatus[tid] == IcacheAccessComplete) {
811                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
812                            "completion\n",tid);
813                }
814
815                cpu->activateStage(O3CPU::FetchIdx);
816            }
817
818            return Active;
819        }
820    }
821
822    // Stage is switching from active to inactive, notify CPU of it.
823    if (_status == Active) {
824        DPRINTF(Activity, "Deactivating stage.\n");
825
826        cpu->deactivateStage(O3CPU::FetchIdx);
827    }
828
829    return Inactive;
830}
831
832template <class Impl>
833void
834DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
835                           const InstSeqNum seq_num, DynInstPtr squashInst,
836                           ThreadID tid)
837{
838    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
839
840    doSquash(newPC, squashInst, tid);
841
842    // Tell the CPU to remove any instructions that are not in the ROB.
843    cpu->removeInstsNotInROB(tid);
844}
845
846template <class Impl>
847void
848DefaultFetch<Impl>::tick()
849{
850    list<ThreadID>::iterator threads = activeThreads->begin();
851    list<ThreadID>::iterator end = activeThreads->end();
852    bool status_change = false;
853
854    wroteToTimeBuffer = false;
855
856    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
857        issuePipelinedIfetch[i] = false;
858    }
859
860    while (threads != end) {
861        ThreadID tid = *threads++;
862
863        // Check the signals for each thread to determine the proper status
864        // for each thread.
865        bool updated_status = checkSignalsAndUpdate(tid);
866        status_change =  status_change || updated_status;
867    }
868
869    DPRINTF(Fetch, "Running stage.\n");
870
871    if (FullSystem) {
872        if (fromCommit->commitInfo[0].interruptPending) {
873            interruptPending = true;
874        }
875
876        if (fromCommit->commitInfo[0].clearInterrupt) {
877            interruptPending = false;
878        }
879    }
880
881    for (threadFetched = 0; threadFetched < numFetchingThreads;
882         threadFetched++) {
883        // Fetch each of the actively fetching threads.
884        fetch(status_change);
885    }
886
887    // Record number of instructions fetched this cycle for distribution.
888    fetchNisnDist.sample(numInst);
889
890    if (status_change) {
891        // Change the fetch stage status if there was a status change.
892        _status = updateFetchStatus();
893    }
894
895    // If there was activity this cycle, inform the CPU of it.
896    if (wroteToTimeBuffer || cpu->contextSwitch) {
897        DPRINTF(Activity, "Activity this cycle.\n");
898
899        cpu->activityThisCycle();
900    }
901
902    // Issue the next I-cache request if possible.
903    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
904        if (issuePipelinedIfetch[i]) {
905            pipelineIcacheAccesses(i);
906        }
907    }
908
909    // Reset the number of the instruction we've fetched.
910    numInst = 0;
911}
912
913template <class Impl>
914bool
915DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
916{
917    // Update the per thread stall statuses.
918    if (fromDecode->decodeBlock[tid]) {
919        stalls[tid].decode = true;
920    }
921
922    if (fromDecode->decodeUnblock[tid]) {
923        assert(stalls[tid].decode);
924        assert(!fromDecode->decodeBlock[tid]);
925        stalls[tid].decode = false;
926    }
927
928    if (fromRename->renameBlock[tid]) {
929        stalls[tid].rename = true;
930    }
931
932    if (fromRename->renameUnblock[tid]) {
933        assert(stalls[tid].rename);
934        assert(!fromRename->renameBlock[tid]);
935        stalls[tid].rename = false;
936    }
937
938    if (fromIEW->iewBlock[tid]) {
939        stalls[tid].iew = true;
940    }
941
942    if (fromIEW->iewUnblock[tid]) {
943        assert(stalls[tid].iew);
944        assert(!fromIEW->iewBlock[tid]);
945        stalls[tid].iew = false;
946    }
947
948    if (fromCommit->commitBlock[tid]) {
949        stalls[tid].commit = true;
950    }
951
952    if (fromCommit->commitUnblock[tid]) {
953        assert(stalls[tid].commit);
954        assert(!fromCommit->commitBlock[tid]);
955        stalls[tid].commit = false;
956    }
957
958    // Check squash signals from commit.
959    if (fromCommit->commitInfo[tid].squash) {
960
961        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
962                "from commit.\n",tid);
963        // In any case, squash.
964        squash(fromCommit->commitInfo[tid].pc,
965               fromCommit->commitInfo[tid].doneSeqNum,
966               fromCommit->commitInfo[tid].squashInst, tid);
967
968        // If it was a branch mispredict on a control instruction, update the
969        // branch predictor with that instruction, otherwise just kill the
970        // invalid state we generated in after sequence number
971        if (fromCommit->commitInfo[tid].mispredictInst &&
972            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
973            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
974                              fromCommit->commitInfo[tid].pc,
975                              fromCommit->commitInfo[tid].branchTaken,
976                              tid);
977        } else {
978            branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
979                              tid);
980        }
981
982        return true;
983    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
984        // Update the branch predictor if it wasn't a squashed instruction
985        // that was broadcasted.
986        branchPred->update(fromCommit->commitInfo[tid].doneSeqNum, tid);
987    }
988
989    // Check ROB squash signals from commit.
990    if (fromCommit->commitInfo[tid].robSquashing) {
991        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
992
993        // Continue to squash.
994        fetchStatus[tid] = Squashing;
995
996        return true;
997    }
998
999    // Check squash signals from decode.
1000    if (fromDecode->decodeInfo[tid].squash) {
1001        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
1002                "from decode.\n",tid);
1003
1004        // Update the branch predictor.
1005        if (fromDecode->decodeInfo[tid].branchMispredict) {
1006            branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1007                              fromDecode->decodeInfo[tid].nextPC,
1008                              fromDecode->decodeInfo[tid].branchTaken,
1009                              tid);
1010        } else {
1011            branchPred->squash(fromDecode->decodeInfo[tid].doneSeqNum,
1012                              tid);
1013        }
1014
1015        if (fetchStatus[tid] != Squashing) {
1016
1017            DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
1018                fromDecode->decodeInfo[tid].nextPC);
1019            // Squash unless we're already squashing
1020            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
1021                             fromDecode->decodeInfo[tid].squashInst,
1022                             fromDecode->decodeInfo[tid].doneSeqNum,
1023                             tid);
1024
1025            return true;
1026        }
1027    }
1028
1029    if (checkStall(tid) &&
1030        fetchStatus[tid] != IcacheWaitResponse &&
1031        fetchStatus[tid] != IcacheWaitRetry &&
1032        fetchStatus[tid] != ItlbWait &&
1033        fetchStatus[tid] != QuiescePending) {
1034        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1035
1036        fetchStatus[tid] = Blocked;
1037
1038        return true;
1039    }
1040
1041    if (fetchStatus[tid] == Blocked ||
1042        fetchStatus[tid] == Squashing) {
1043        // Switch status to running if fetch isn't being told to block or
1044        // squash this cycle.
1045        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1046                tid);
1047
1048        fetchStatus[tid] = Running;
1049
1050        return true;
1051    }
1052
1053    // If we've reached this point, we have not gotten any signals that
1054    // cause fetch to change its status.  Fetch remains the same as before.
1055    return false;
1056}
1057
1058template<class Impl>
1059typename Impl::DynInstPtr
1060DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1061                              StaticInstPtr curMacroop, TheISA::PCState thisPC,
1062                              TheISA::PCState nextPC, bool trace)
1063{
1064    // Get a sequence number.
1065    InstSeqNum seq = cpu->getAndIncrementInstSeq();
1066
1067    // Create a new DynInst from the instruction fetched.
1068    DynInstPtr instruction =
1069        new DynInst(staticInst, curMacroop, thisPC, nextPC, seq, cpu);
1070    instruction->setTid(tid);
1071
1072    instruction->setASID(tid);
1073
1074    instruction->setThreadState(cpu->thread[tid]);
1075
1076    DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1077            "[sn:%lli].\n", tid, thisPC.instAddr(),
1078            thisPC.microPC(), seq);
1079
1080    DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1081            instruction->staticInst->
1082            disassemble(thisPC.instAddr()));
1083
1084#if TRACING_ON
1085    if (trace) {
1086        instruction->traceData =
1087            cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1088                    instruction->staticInst, thisPC, curMacroop);
1089    }
1090#else
1091    instruction->traceData = NULL;
1092#endif
1093
1094    // Add instruction to the CPU's list of instructions.
1095    instruction->setInstListIt(cpu->addInst(instruction));
1096
1097    // Write the instruction to the first slot in the queue
1098    // that heads to decode.
1099    assert(numInst < fetchWidth);
1100    toDecode->insts[toDecode->size++] = instruction;
1101
1102    // Keep track of if we can take an interrupt at this boundary
1103    delayedCommit[tid] = instruction->isDelayedCommit();
1104
1105    return instruction;
1106}
1107
1108template<class Impl>
1109void
1110DefaultFetch<Impl>::fetch(bool &status_change)
1111{
1112    //////////////////////////////////////////
1113    // Start actual fetch
1114    //////////////////////////////////////////
1115    ThreadID tid = getFetchingThread(fetchPolicy);
1116
1117    assert(!cpu->switchedOut());
1118
1119    if (tid == InvalidThreadID) {
1120        // Breaks looping condition in tick()
1121        threadFetched = numFetchingThreads;
1122
1123        if (numThreads == 1) {  // @todo Per-thread stats
1124            profileStall(0);
1125        }
1126
1127        return;
1128    }
1129
1130    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1131
1132    // The current PC.
1133    TheISA::PCState thisPC = pc[tid];
1134
1135    Addr pcOffset = fetchOffset[tid];
1136    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1137
1138    bool inRom = isRomMicroPC(thisPC.microPC());
1139
1140    // If returning from the delay of a cache miss, then update the status
1141    // to running, otherwise do the cache access.  Possibly move this up
1142    // to tick() function.
1143    if (fetchStatus[tid] == IcacheAccessComplete) {
1144        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1145
1146        fetchStatus[tid] = Running;
1147        status_change = true;
1148    } else if (fetchStatus[tid] == Running) {
1149        // Align the fetch PC so its at the start of a cache block.
1150        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1151
1152        // If buffer is no longer valid or fetchAddr has moved to point
1153        // to the next cache block, AND we have no remaining ucode
1154        // from a macro-op, then start fetch from icache.
1155        if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1156            && !inRom && !macroop[tid]) {
1157            DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1158                    "instruction, starting at PC %s.\n", tid, thisPC);
1159
1160            fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1161
1162            if (fetchStatus[tid] == IcacheWaitResponse)
1163                ++icacheStallCycles;
1164            else if (fetchStatus[tid] == ItlbWait)
1165                ++fetchTlbCycles;
1166            else
1167                ++fetchMiscStallCycles;
1168            return;
1169        } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])) {
1170            // Stall CPU if an interrupt is posted and we're not issuing
1171            // an delayed commit micro-op currently (delayed commit instructions
1172            // are not interruptable by interrupts, only faults)
1173            ++fetchMiscStallCycles;
1174            DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid);
1175            return;
1176        }
1177    } else {
1178        if (fetchStatus[tid] == Idle) {
1179            ++fetchIdleCycles;
1180            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1181        }
1182
1183        // Status is Idle, so fetch should do nothing.
1184        return;
1185    }
1186
1187    ++fetchCycles;
1188
1189    TheISA::PCState nextPC = thisPC;
1190
1191    StaticInstPtr staticInst = NULL;
1192    StaticInstPtr curMacroop = macroop[tid];
1193
1194    // If the read of the first instruction was successful, then grab the
1195    // instructions from the rest of the cache line and put them into the
1196    // queue heading to decode.
1197
1198    DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1199            "decode.\n", tid);
1200
1201    // Need to keep track of whether or not a predicted branch
1202    // ended this fetch block.
1203    bool predictedBranch = false;
1204
1205    TheISA::MachInst *cacheInsts =
1206        reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1207
1208    const unsigned numInsts = cacheBlkSize / instSize;
1209    unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1210
1211    // Loop through instruction memory from the cache.
1212    // Keep issuing while fetchWidth is available and branch is not
1213    // predicted taken
1214    while (numInst < fetchWidth && !predictedBranch) {
1215
1216        // We need to process more memory if we aren't going to get a
1217        // StaticInst from the rom, the current macroop, or what's already
1218        // in the decoder.
1219        bool needMem = !inRom && !curMacroop &&
1220            !decoder[tid]->instReady();
1221        fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1222        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1223
1224        if (needMem) {
1225            // If buffer is no longer valid or fetchAddr has moved to point
1226            // to the next cache block then start fetch from icache.
1227            if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
1228                break;
1229
1230            if (blkOffset >= numInsts) {
1231                // We need to process more memory, but we've run out of the
1232                // current block.
1233                break;
1234            }
1235
1236            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1237                // Walk past any annulled delay slot instructions.
1238                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1239                while (fetchAddr != pcAddr && blkOffset < numInsts) {
1240                    blkOffset++;
1241                    fetchAddr += instSize;
1242                }
1243                if (blkOffset >= numInsts)
1244                    break;
1245            }
1246
1247            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1248            decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
1249
1250            if (decoder[tid]->needMoreBytes()) {
1251                blkOffset++;
1252                fetchAddr += instSize;
1253                pcOffset += instSize;
1254            }
1255        }
1256
1257        // Extract as many instructions and/or microops as we can from
1258        // the memory we've processed so far.
1259        do {
1260            if (!(curMacroop || inRom)) {
1261                if (decoder[tid]->instReady()) {
1262                    staticInst = decoder[tid]->decode(thisPC);
1263
1264                    // Increment stat of fetched instructions.
1265                    ++fetchedInsts;
1266
1267                    if (staticInst->isMacroop()) {
1268                        curMacroop = staticInst;
1269                    } else {
1270                        pcOffset = 0;
1271                    }
1272                } else {
1273                    // We need more bytes for this instruction so blkOffset and
1274                    // pcOffset will be updated
1275                    break;
1276                }
1277            }
1278            // Whether we're moving to a new macroop because we're at the
1279            // end of the current one, or the branch predictor incorrectly
1280            // thinks we are...
1281            bool newMacro = false;
1282            if (curMacroop || inRom) {
1283                if (inRom) {
1284                    staticInst = cpu->microcodeRom.fetchMicroop(
1285                            thisPC.microPC(), curMacroop);
1286                } else {
1287                    staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1288                }
1289                newMacro |= staticInst->isLastMicroop();
1290            }
1291
1292            DynInstPtr instruction =
1293                buildInst(tid, staticInst, curMacroop,
1294                          thisPC, nextPC, true);
1295
1296            numInst++;
1297
1298#if TRACING_ON
1299            if (DTRACE(O3PipeView)) {
1300                instruction->fetchTick = curTick();
1301            }
1302#endif
1303
1304            nextPC = thisPC;
1305
1306            // If we're branching after this instruction, quite fetching
1307            // from the same block then.
1308            predictedBranch |= thisPC.branching();
1309            predictedBranch |=
1310                lookupAndUpdateNextPC(instruction, nextPC);
1311            if (predictedBranch) {
1312                DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1313            }
1314
1315            newMacro |= thisPC.instAddr() != nextPC.instAddr();
1316
1317            // Move to the next instruction, unless we have a branch.
1318            thisPC = nextPC;
1319            inRom = isRomMicroPC(thisPC.microPC());
1320
1321            if (newMacro) {
1322                fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1323                blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1324                pcOffset = 0;
1325                curMacroop = NULL;
1326            }
1327
1328            if (instruction->isQuiesce()) {
1329                DPRINTF(Fetch,
1330                        "Quiesce instruction encountered, halting fetch!");
1331                fetchStatus[tid] = QuiescePending;
1332                status_change = true;
1333                break;
1334            }
1335        } while ((curMacroop || decoder[tid]->instReady()) &&
1336                 numInst < fetchWidth);
1337    }
1338
1339    if (predictedBranch) {
1340        DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1341                "instruction encountered.\n", tid);
1342    } else if (numInst >= fetchWidth) {
1343        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1344                "for this cycle.\n", tid);
1345    } else if (blkOffset >= cacheBlkSize) {
1346        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1347                "block.\n", tid);
1348    }
1349
1350    macroop[tid] = curMacroop;
1351    fetchOffset[tid] = pcOffset;
1352
1353    if (numInst > 0) {
1354        wroteToTimeBuffer = true;
1355    }
1356
1357    pc[tid] = thisPC;
1358
1359    // pipeline a fetch if we're crossing a cache boundary and not in
1360    // a state that would preclude fetching
1361    fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1362    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1363    issuePipelinedIfetch[tid] = block_PC != cacheDataPC[tid] &&
1364        fetchStatus[tid] != IcacheWaitResponse &&
1365        fetchStatus[tid] != ItlbWait &&
1366        fetchStatus[tid] != IcacheWaitRetry &&
1367        fetchStatus[tid] != QuiescePending &&
1368        !curMacroop;
1369}
1370
1371template<class Impl>
1372void
1373DefaultFetch<Impl>::recvRetry()
1374{
1375    if (retryPkt != NULL) {
1376        assert(cacheBlocked);
1377        assert(retryTid != InvalidThreadID);
1378        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1379
1380        if (cpu->getInstPort().sendTimingReq(retryPkt)) {
1381            fetchStatus[retryTid] = IcacheWaitResponse;
1382            retryPkt = NULL;
1383            retryTid = InvalidThreadID;
1384            cacheBlocked = false;
1385        }
1386    } else {
1387        assert(retryTid == InvalidThreadID);
1388        // Access has been squashed since it was sent out.  Just clear
1389        // the cache being blocked.
1390        cacheBlocked = false;
1391    }
1392}
1393
1394///////////////////////////////////////
1395//                                   //
1396//  SMT FETCH POLICY MAINTAINED HERE //
1397//                                   //
1398///////////////////////////////////////
1399template<class Impl>
1400ThreadID
1401DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1402{
1403    if (numThreads > 1) {
1404        switch (fetch_priority) {
1405
1406          case SingleThread:
1407            return 0;
1408
1409          case RoundRobin:
1410            return roundRobin();
1411
1412          case IQ:
1413            return iqCount();
1414
1415          case LSQ:
1416            return lsqCount();
1417
1418          case Branch:
1419            return branchCount();
1420
1421          default:
1422            return InvalidThreadID;
1423        }
1424    } else {
1425        list<ThreadID>::iterator thread = activeThreads->begin();
1426        if (thread == activeThreads->end()) {
1427            return InvalidThreadID;
1428        }
1429
1430        ThreadID tid = *thread;
1431
1432        if (fetchStatus[tid] == Running ||
1433            fetchStatus[tid] == IcacheAccessComplete ||
1434            fetchStatus[tid] == Idle) {
1435            return tid;
1436        } else {
1437            return InvalidThreadID;
1438        }
1439    }
1440}
1441
1442
1443template<class Impl>
1444ThreadID
1445DefaultFetch<Impl>::roundRobin()
1446{
1447    list<ThreadID>::iterator pri_iter = priorityList.begin();
1448    list<ThreadID>::iterator end      = priorityList.end();
1449
1450    ThreadID high_pri;
1451
1452    while (pri_iter != end) {
1453        high_pri = *pri_iter;
1454
1455        assert(high_pri <= numThreads);
1456
1457        if (fetchStatus[high_pri] == Running ||
1458            fetchStatus[high_pri] == IcacheAccessComplete ||
1459            fetchStatus[high_pri] == Idle) {
1460
1461            priorityList.erase(pri_iter);
1462            priorityList.push_back(high_pri);
1463
1464            return high_pri;
1465        }
1466
1467        pri_iter++;
1468    }
1469
1470    return InvalidThreadID;
1471}
1472
1473template<class Impl>
1474ThreadID
1475DefaultFetch<Impl>::iqCount()
1476{
1477    std::priority_queue<unsigned> PQ;
1478    std::map<unsigned, ThreadID> threadMap;
1479
1480    list<ThreadID>::iterator threads = activeThreads->begin();
1481    list<ThreadID>::iterator end = activeThreads->end();
1482
1483    while (threads != end) {
1484        ThreadID tid = *threads++;
1485        unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1486
1487        PQ.push(iqCount);
1488        threadMap[iqCount] = tid;
1489    }
1490
1491    while (!PQ.empty()) {
1492        ThreadID high_pri = threadMap[PQ.top()];
1493
1494        if (fetchStatus[high_pri] == Running ||
1495            fetchStatus[high_pri] == IcacheAccessComplete ||
1496            fetchStatus[high_pri] == Idle)
1497            return high_pri;
1498        else
1499            PQ.pop();
1500
1501    }
1502
1503    return InvalidThreadID;
1504}
1505
1506template<class Impl>
1507ThreadID
1508DefaultFetch<Impl>::lsqCount()
1509{
1510    std::priority_queue<unsigned> PQ;
1511    std::map<unsigned, ThreadID> threadMap;
1512
1513    list<ThreadID>::iterator threads = activeThreads->begin();
1514    list<ThreadID>::iterator end = activeThreads->end();
1515
1516    while (threads != end) {
1517        ThreadID tid = *threads++;
1518        unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1519
1520        PQ.push(ldstqCount);
1521        threadMap[ldstqCount] = tid;
1522    }
1523
1524    while (!PQ.empty()) {
1525        ThreadID high_pri = threadMap[PQ.top()];
1526
1527        if (fetchStatus[high_pri] == Running ||
1528            fetchStatus[high_pri] == IcacheAccessComplete ||
1529            fetchStatus[high_pri] == Idle)
1530            return high_pri;
1531        else
1532            PQ.pop();
1533    }
1534
1535    return InvalidThreadID;
1536}
1537
1538template<class Impl>
1539ThreadID
1540DefaultFetch<Impl>::branchCount()
1541{
1542#if 0
1543    list<ThreadID>::iterator thread = activeThreads->begin();
1544    assert(thread != activeThreads->end());
1545    ThreadID tid = *thread;
1546#endif
1547
1548    panic("Branch Count Fetch policy unimplemented\n");
1549    return InvalidThreadID;
1550}
1551
1552template<class Impl>
1553void
1554DefaultFetch<Impl>::pipelineIcacheAccesses(ThreadID tid)
1555{
1556    if (!issuePipelinedIfetch[tid]) {
1557        return;
1558    }
1559
1560    // The next PC to access.
1561    TheISA::PCState thisPC = pc[tid];
1562
1563    if (isRomMicroPC(thisPC.microPC())) {
1564        return;
1565    }
1566
1567    Addr pcOffset = fetchOffset[tid];
1568    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1569
1570    // Align the fetch PC so its at the start of a cache block.
1571    Addr block_PC = icacheBlockAlignPC(fetchAddr);
1572
1573    // Unless buffer already got the block, fetch it from icache.
1574    if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])) {
1575        DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
1576                "starting at PC %s.\n", tid, thisPC);
1577
1578        fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1579    }
1580}
1581
1582template<class Impl>
1583void
1584DefaultFetch<Impl>::profileStall(ThreadID tid) {
1585    DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1586
1587    // @todo Per-thread stats
1588
1589    if (stalls[tid].drain) {
1590        ++fetchPendingDrainCycles;
1591        DPRINTF(Fetch, "Fetch is waiting for a drain!\n");
1592    } else if (activeThreads->empty()) {
1593        ++fetchNoActiveThreadStallCycles;
1594        DPRINTF(Fetch, "Fetch has no active thread!\n");
1595    } else if (fetchStatus[tid] == Blocked) {
1596        ++fetchBlockedCycles;
1597        DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1598    } else if (fetchStatus[tid] == Squashing) {
1599        ++fetchSquashCycles;
1600        DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1601    } else if (fetchStatus[tid] == IcacheWaitResponse) {
1602        ++icacheStallCycles;
1603        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1604                tid);
1605    } else if (fetchStatus[tid] == ItlbWait) {
1606        ++fetchTlbCycles;
1607        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1608                "finish!\n", tid);
1609    } else if (fetchStatus[tid] == TrapPending) {
1610        ++fetchPendingTrapStallCycles;
1611        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n",
1612                tid);
1613    } else if (fetchStatus[tid] == QuiescePending) {
1614        ++fetchPendingQuiesceStallCycles;
1615        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce "
1616                "instruction!\n", tid);
1617    } else if (fetchStatus[tid] == IcacheWaitRetry) {
1618        ++fetchIcacheWaitRetryStallCycles;
1619        DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache retry!\n",
1620                tid);
1621    } else if (fetchStatus[tid] == NoGoodAddr) {
1622            DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1623                    tid);
1624    } else {
1625        DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason (Status: %i).\n",
1626             tid, fetchStatus[tid]);
1627    }
1628}
1629