fetch_impl.hh revision 8460:3893d9d2c6c2 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <algorithm>
45#include <cstring>
46
47#include "arch/isa_traits.hh"
48#include "arch/utility.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/fetch.hh"
54#include "cpu/exetrace.hh"
55#include "debug/Activity.hh"
56#include "debug/Fetch.hh"
57#include "mem/packet.hh"
58#include "mem/request.hh"
59#include "params/DerivO3CPU.hh"
60#include "sim/byteswap.hh"
61#include "sim/core.hh"
62
63#if FULL_SYSTEM
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "sim/system.hh"
67#endif // FULL_SYSTEM
68
69using namespace std;
70
71template<class Impl>
72void
73DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
74{
75    Port::setPeer(port);
76
77    fetch->setIcache();
78}
79
80template<class Impl>
81Tick
82DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
83{
84    panic("DefaultFetch doesn't expect recvAtomic callback!");
85    return curTick();
86}
87
88template<class Impl>
89void
90DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
91{
92    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
93            "functional call.\n");
94}
95
96template<class Impl>
97void
98DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
99{
100    if (status == RangeChange) {
101        if (!snoopRangeSent) {
102            snoopRangeSent = true;
103            sendStatusChange(Port::RangeChange);
104        }
105        return;
106    }
107
108    panic("DefaultFetch doesn't expect recvStatusChange callback!");
109}
110
111template<class Impl>
112bool
113DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
114{
115    DPRINTF(Fetch, "Received timing\n");
116    if (pkt->isResponse()) {
117        // We shouldn't ever get a block in ownership state
118        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
119
120        fetch->processCacheCompletion(pkt);
121    }
122    //else Snooped a coherence request, just return
123    return true;
124}
125
126template<class Impl>
127void
128DefaultFetch<Impl>::IcachePort::recvRetry()
129{
130    fetch->recvRetry();
131}
132
133template<class Impl>
134DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
135    : cpu(_cpu),
136      branchPred(params),
137      predecoder(NULL),
138      decodeToFetchDelay(params->decodeToFetchDelay),
139      renameToFetchDelay(params->renameToFetchDelay),
140      iewToFetchDelay(params->iewToFetchDelay),
141      commitToFetchDelay(params->commitToFetchDelay),
142      fetchWidth(params->fetchWidth),
143      cacheBlocked(false),
144      retryPkt(NULL),
145      retryTid(InvalidThreadID),
146      numThreads(params->numThreads),
147      numFetchingThreads(params->smtNumFetchingThreads),
148      interruptPending(false),
149      drainPending(false),
150      switchedOut(false)
151{
152    if (numThreads > Impl::MaxThreads)
153        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
154              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
155              numThreads, static_cast<int>(Impl::MaxThreads));
156
157    // Set fetch stage's status to inactive.
158    _status = Inactive;
159
160    std::string policy = params->smtFetchPolicy;
161
162    // Convert string to lowercase
163    std::transform(policy.begin(), policy.end(), policy.begin(),
164                   (int(*)(int)) tolower);
165
166    // Figure out fetch policy
167    if (policy == "singlethread") {
168        fetchPolicy = SingleThread;
169        if (numThreads > 1)
170            panic("Invalid Fetch Policy for a SMT workload.");
171    } else if (policy == "roundrobin") {
172        fetchPolicy = RoundRobin;
173        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
174    } else if (policy == "branch") {
175        fetchPolicy = Branch;
176        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
177    } else if (policy == "iqcount") {
178        fetchPolicy = IQ;
179        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
180    } else if (policy == "lsqcount") {
181        fetchPolicy = LSQ;
182        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
183    } else {
184        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
185              " RoundRobin,LSQcount,IQcount}\n");
186    }
187
188    // Get the size of an instruction.
189    instSize = sizeof(TheISA::MachInst);
190
191    // Name is finally available, so create the port.
192    icachePort = new IcachePort(this);
193
194    icachePort->snoopRangeSent = false;
195
196#if USE_CHECKER
197    if (cpu->checker) {
198        cpu->checker->setIcachePort(icachePort);
199    }
200#endif
201}
202
203template <class Impl>
204std::string
205DefaultFetch<Impl>::name() const
206{
207    return cpu->name() + ".fetch";
208}
209
210template <class Impl>
211void
212DefaultFetch<Impl>::regStats()
213{
214    icacheStallCycles
215        .name(name() + ".icacheStallCycles")
216        .desc("Number of cycles fetch is stalled on an Icache miss")
217        .prereq(icacheStallCycles);
218
219    fetchedInsts
220        .name(name() + ".Insts")
221        .desc("Number of instructions fetch has processed")
222        .prereq(fetchedInsts);
223
224    fetchedBranches
225        .name(name() + ".Branches")
226        .desc("Number of branches that fetch encountered")
227        .prereq(fetchedBranches);
228
229    predictedBranches
230        .name(name() + ".predictedBranches")
231        .desc("Number of branches that fetch has predicted taken")
232        .prereq(predictedBranches);
233
234    fetchCycles
235        .name(name() + ".Cycles")
236        .desc("Number of cycles fetch has run and was not squashing or"
237              " blocked")
238        .prereq(fetchCycles);
239
240    fetchSquashCycles
241        .name(name() + ".SquashCycles")
242        .desc("Number of cycles fetch has spent squashing")
243        .prereq(fetchSquashCycles);
244
245    fetchTlbCycles
246        .name(name() + ".TlbCycles")
247        .desc("Number of cycles fetch has spent waiting for tlb")
248        .prereq(fetchTlbCycles);
249
250    fetchIdleCycles
251        .name(name() + ".IdleCycles")
252        .desc("Number of cycles fetch was idle")
253        .prereq(fetchIdleCycles);
254
255    fetchBlockedCycles
256        .name(name() + ".BlockedCycles")
257        .desc("Number of cycles fetch has spent blocked")
258        .prereq(fetchBlockedCycles);
259
260    fetchedCacheLines
261        .name(name() + ".CacheLines")
262        .desc("Number of cache lines fetched")
263        .prereq(fetchedCacheLines);
264
265    fetchMiscStallCycles
266        .name(name() + ".MiscStallCycles")
267        .desc("Number of cycles fetch has spent waiting on interrupts, or "
268              "bad addresses, or out of MSHRs")
269        .prereq(fetchMiscStallCycles);
270
271    fetchIcacheSquashes
272        .name(name() + ".IcacheSquashes")
273        .desc("Number of outstanding Icache misses that were squashed")
274        .prereq(fetchIcacheSquashes);
275
276    fetchTlbSquashes
277        .name(name() + ".ItlbSquashes")
278        .desc("Number of outstanding ITLB misses that were squashed")
279        .prereq(fetchTlbSquashes);
280
281    fetchNisnDist
282        .init(/* base value */ 0,
283              /* last value */ fetchWidth,
284              /* bucket size */ 1)
285        .name(name() + ".rateDist")
286        .desc("Number of instructions fetched each cycle (Total)")
287        .flags(Stats::pdf);
288
289    idleRate
290        .name(name() + ".idleRate")
291        .desc("Percent of cycles fetch was idle")
292        .prereq(idleRate);
293    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
294
295    branchRate
296        .name(name() + ".branchRate")
297        .desc("Number of branch fetches per cycle")
298        .flags(Stats::total);
299    branchRate = fetchedBranches / cpu->numCycles;
300
301    fetchRate
302        .name(name() + ".rate")
303        .desc("Number of inst fetches per cycle")
304        .flags(Stats::total);
305    fetchRate = fetchedInsts / cpu->numCycles;
306
307    branchPred.regStats();
308}
309
310template<class Impl>
311void
312DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
313{
314    timeBuffer = time_buffer;
315
316    // Create wires to get information from proper places in time buffer.
317    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
318    fromRename = timeBuffer->getWire(-renameToFetchDelay);
319    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
320    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
321}
322
323template<class Impl>
324void
325DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
326{
327    activeThreads = at_ptr;
328}
329
330template<class Impl>
331void
332DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
333{
334    fetchQueue = fq_ptr;
335
336    // Create wire to write information to proper place in fetch queue.
337    toDecode = fetchQueue->getWire(0);
338}
339
340template<class Impl>
341void
342DefaultFetch<Impl>::initStage()
343{
344    // Setup PC and nextPC with initial state.
345    for (ThreadID tid = 0; tid < numThreads; tid++) {
346        pc[tid] = cpu->pcState(tid);
347        fetchOffset[tid] = 0;
348        macroop[tid] = NULL;
349        delayedCommit[tid] = false;
350    }
351
352    for (ThreadID tid = 0; tid < numThreads; tid++) {
353
354        fetchStatus[tid] = Running;
355
356        priorityList.push_back(tid);
357
358        memReq[tid] = NULL;
359
360        stalls[tid].decode = false;
361        stalls[tid].rename = false;
362        stalls[tid].iew = false;
363        stalls[tid].commit = false;
364    }
365
366    // Schedule fetch to get the correct PC from the CPU
367    // scheduleFetchStartupEvent(1);
368
369    // Fetch needs to start fetching instructions at the very beginning,
370    // so it must start up in active state.
371    switchToActive();
372}
373
374template<class Impl>
375void
376DefaultFetch<Impl>::setIcache()
377{
378    // Size of cache block.
379    cacheBlkSize = icachePort->peerBlockSize();
380
381    // Create mask to get rid of offset bits.
382    cacheBlkMask = (cacheBlkSize - 1);
383
384    for (ThreadID tid = 0; tid < numThreads; tid++) {
385        // Create space to store a cache line.
386        cacheData[tid] = new uint8_t[cacheBlkSize];
387        cacheDataPC[tid] = 0;
388        cacheDataValid[tid] = false;
389    }
390}
391
392template<class Impl>
393void
394DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
395{
396    ThreadID tid = pkt->req->threadId();
397
398    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
399
400    assert(!pkt->wasNacked());
401
402    // Only change the status if it's still waiting on the icache access
403    // to return.
404    if (fetchStatus[tid] != IcacheWaitResponse ||
405        pkt->req != memReq[tid] ||
406        isSwitchedOut()) {
407        ++fetchIcacheSquashes;
408        delete pkt->req;
409        delete pkt;
410        return;
411    }
412
413    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
414    cacheDataValid[tid] = true;
415
416    if (!drainPending) {
417        // Wake up the CPU (if it went to sleep and was waiting on
418        // this completion event).
419        cpu->wakeCPU();
420
421        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
422                tid);
423
424        switchToActive();
425    }
426
427    // Only switch to IcacheAccessComplete if we're not stalled as well.
428    if (checkStall(tid)) {
429        fetchStatus[tid] = Blocked;
430    } else {
431        fetchStatus[tid] = IcacheAccessComplete;
432    }
433
434    // Reset the mem req to NULL.
435    delete pkt->req;
436    delete pkt;
437    memReq[tid] = NULL;
438}
439
440template <class Impl>
441bool
442DefaultFetch<Impl>::drain()
443{
444    // Fetch is ready to drain at any time.
445    cpu->signalDrained();
446    drainPending = true;
447    return true;
448}
449
450template <class Impl>
451void
452DefaultFetch<Impl>::resume()
453{
454    drainPending = false;
455}
456
457template <class Impl>
458void
459DefaultFetch<Impl>::switchOut()
460{
461    switchedOut = true;
462    // Branch predictor needs to have its state cleared.
463    branchPred.switchOut();
464}
465
466template <class Impl>
467void
468DefaultFetch<Impl>::takeOverFrom()
469{
470    // Reset all state
471    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
472        stalls[i].decode = 0;
473        stalls[i].rename = 0;
474        stalls[i].iew = 0;
475        stalls[i].commit = 0;
476        pc[i] = cpu->pcState(i);
477        fetchStatus[i] = Running;
478    }
479    numInst = 0;
480    wroteToTimeBuffer = false;
481    _status = Inactive;
482    switchedOut = false;
483    interruptPending = false;
484    branchPred.takeOverFrom();
485}
486
487template <class Impl>
488void
489DefaultFetch<Impl>::wakeFromQuiesce()
490{
491    DPRINTF(Fetch, "Waking up from quiesce\n");
492    // Hopefully this is safe
493    // @todo: Allow other threads to wake from quiesce.
494    fetchStatus[0] = Running;
495}
496
497template <class Impl>
498inline void
499DefaultFetch<Impl>::switchToActive()
500{
501    if (_status == Inactive) {
502        DPRINTF(Activity, "Activating stage.\n");
503
504        cpu->activateStage(O3CPU::FetchIdx);
505
506        _status = Active;
507    }
508}
509
510template <class Impl>
511inline void
512DefaultFetch<Impl>::switchToInactive()
513{
514    if (_status == Active) {
515        DPRINTF(Activity, "Deactivating stage.\n");
516
517        cpu->deactivateStage(O3CPU::FetchIdx);
518
519        _status = Inactive;
520    }
521}
522
523template <class Impl>
524bool
525DefaultFetch<Impl>::lookupAndUpdateNextPC(
526        DynInstPtr &inst, TheISA::PCState &nextPC)
527{
528    // Do branch prediction check here.
529    // A bit of a misnomer...next_PC is actually the current PC until
530    // this function updates it.
531    bool predict_taken;
532
533    if (!inst->isControl()) {
534        TheISA::advancePC(nextPC, inst->staticInst);
535        inst->setPredTarg(nextPC);
536        inst->setPredTaken(false);
537        return false;
538    }
539
540    ThreadID tid = inst->threadNumber;
541    predict_taken = branchPred.predict(inst, nextPC, tid);
542
543    if (predict_taken) {
544        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
545                tid, inst->seqNum, nextPC);
546    } else {
547        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
548                tid, inst->seqNum);
549    }
550
551    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
552            tid, inst->seqNum, nextPC);
553    inst->setPredTarg(nextPC);
554    inst->setPredTaken(predict_taken);
555
556    ++fetchedBranches;
557
558    if (predict_taken) {
559        ++predictedBranches;
560    }
561
562    return predict_taken;
563}
564
565template <class Impl>
566bool
567DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
568{
569    Fault fault = NoFault;
570
571    // @todo: not sure if these should block translation.
572    //AlphaDep
573    if (cacheBlocked) {
574        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
575                tid);
576        return false;
577    } else if (isSwitchedOut()) {
578        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
579                tid);
580        return false;
581    } else if (checkInterrupt(pc)) {
582        // Hold off fetch from getting new instructions when:
583        // Cache is blocked, or
584        // while an interrupt is pending and we're not in PAL mode, or
585        // fetch is switched out.
586        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
587                tid);
588        return false;
589    }
590
591    // Align the fetch address so it's at the start of a cache block.
592    Addr block_PC = icacheBlockAlignPC(vaddr);
593
594    DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
595            tid, block_PC, vaddr);
596
597    // Setup the memReq to do a read of the first instruction's address.
598    // Set the appropriate read size and flags as well.
599    // Build request here.
600    RequestPtr mem_req =
601        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
602                    pc, cpu->thread[tid]->contextId(), tid);
603
604    memReq[tid] = mem_req;
605
606    // Initiate translation of the icache block
607    fetchStatus[tid] = ItlbWait;
608    FetchTranslation *trans = new FetchTranslation(this);
609    cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
610                              trans, BaseTLB::Execute);
611    return true;
612}
613
614template <class Impl>
615void
616DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
617{
618    ThreadID tid = mem_req->threadId();
619    Addr block_PC = mem_req->getVaddr();
620
621    // Wake up CPU if it was idle
622    cpu->wakeCPU();
623
624    if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
625        mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
626        DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
627                tid);
628        ++fetchTlbSquashes;
629        delete mem_req;
630        return;
631    }
632
633
634    // If translation was successful, attempt to read the icache block.
635    if (fault == NoFault) {
636        // Check that we're not going off into random memory
637        // If we have, just wait around for commit to squash something and put
638        // us on the right track
639        if (!cpu->system->isMemory(mem_req->getPaddr())) {
640            warn("Address %#x is outside of physical memory, stopping fetch\n",
641                    mem_req->getPaddr());
642            fetchStatus[tid] = NoGoodAddr;
643            delete mem_req;
644            memReq[tid] = NULL;
645            return;
646        }
647
648        // Build packet here.
649        PacketPtr data_pkt = new Packet(mem_req,
650                                        MemCmd::ReadReq, Packet::Broadcast);
651        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
652
653        cacheDataPC[tid] = block_PC;
654        cacheDataValid[tid] = false;
655        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
656
657        fetchedCacheLines++;
658
659        // Access the cache.
660        if (!icachePort->sendTiming(data_pkt)) {
661            assert(retryPkt == NULL);
662            assert(retryTid == InvalidThreadID);
663            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
664
665            fetchStatus[tid] = IcacheWaitRetry;
666            retryPkt = data_pkt;
667            retryTid = tid;
668            cacheBlocked = true;
669        } else {
670            DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
671            DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
672                    "response.\n", tid);
673
674            lastIcacheStall[tid] = curTick();
675            fetchStatus[tid] = IcacheWaitResponse;
676        }
677    } else {
678        DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
679                mem_req->getVaddr(), memReq[tid]->getVaddr());
680        // Translation faulted, icache request won't be sent.
681        delete mem_req;
682        memReq[tid] = NULL;
683
684        // Send the fault to commit.  This thread will not do anything
685        // until commit handles the fault.  The only other way it can
686        // wake up is if a squash comes along and changes the PC.
687        TheISA::PCState fetchPC = pc[tid];
688
689        DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
690        // We will use a nop in ordier to carry the fault.
691        DynInstPtr instruction = buildInst(tid,
692                StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
693                NULL, fetchPC, fetchPC, false);
694
695        instruction->setPredTarg(fetchPC);
696        instruction->fault = fault;
697        wroteToTimeBuffer = true;
698
699        DPRINTF(Activity, "Activity this cycle.\n");
700        cpu->activityThisCycle();
701
702        fetchStatus[tid] = TrapPending;
703
704        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
705        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
706                tid, fault->name(), pc[tid]);
707    }
708    _status = updateFetchStatus();
709}
710
711template <class Impl>
712inline void
713DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
714{
715    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
716            tid, newPC);
717
718    pc[tid] = newPC;
719    fetchOffset[tid] = 0;
720    macroop[tid] = NULL;
721    predecoder.reset();
722
723    // Clear the icache miss if it's outstanding.
724    if (fetchStatus[tid] == IcacheWaitResponse) {
725        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
726                tid);
727        memReq[tid] = NULL;
728    } else if (fetchStatus[tid] == ItlbWait) {
729        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
730                tid);
731        memReq[tid] = NULL;
732    }
733
734    // Get rid of the retrying packet if it was from this thread.
735    if (retryTid == tid) {
736        assert(cacheBlocked);
737        if (retryPkt) {
738            delete retryPkt->req;
739            delete retryPkt;
740        }
741        retryPkt = NULL;
742        retryTid = InvalidThreadID;
743    }
744
745    fetchStatus[tid] = Squashing;
746
747    ++fetchSquashCycles;
748}
749
750template<class Impl>
751void
752DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
753                                     const InstSeqNum &seq_num, ThreadID tid)
754{
755    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
756
757    doSquash(newPC, tid);
758
759    // Tell the CPU to remove any instructions that are in flight between
760    // fetch and decode.
761    cpu->removeInstsUntil(seq_num, tid);
762}
763
764template<class Impl>
765bool
766DefaultFetch<Impl>::checkStall(ThreadID tid) const
767{
768    bool ret_val = false;
769
770    if (cpu->contextSwitch) {
771        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
772        ret_val = true;
773    } else if (stalls[tid].decode) {
774        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
775        ret_val = true;
776    } else if (stalls[tid].rename) {
777        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
778        ret_val = true;
779    } else if (stalls[tid].iew) {
780        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
781        ret_val = true;
782    } else if (stalls[tid].commit) {
783        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
784        ret_val = true;
785    }
786
787    return ret_val;
788}
789
790template<class Impl>
791typename DefaultFetch<Impl>::FetchStatus
792DefaultFetch<Impl>::updateFetchStatus()
793{
794    //Check Running
795    list<ThreadID>::iterator threads = activeThreads->begin();
796    list<ThreadID>::iterator end = activeThreads->end();
797
798    while (threads != end) {
799        ThreadID tid = *threads++;
800
801        if (fetchStatus[tid] == Running ||
802            fetchStatus[tid] == Squashing ||
803            fetchStatus[tid] == IcacheAccessComplete) {
804
805            if (_status == Inactive) {
806                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
807
808                if (fetchStatus[tid] == IcacheAccessComplete) {
809                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
810                            "completion\n",tid);
811                }
812
813                cpu->activateStage(O3CPU::FetchIdx);
814            }
815
816            return Active;
817        }
818    }
819
820    // Stage is switching from active to inactive, notify CPU of it.
821    if (_status == Active) {
822        DPRINTF(Activity, "Deactivating stage.\n");
823
824        cpu->deactivateStage(O3CPU::FetchIdx);
825    }
826
827    return Inactive;
828}
829
830template <class Impl>
831void
832DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
833                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
834                           ThreadID tid)
835{
836    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
837
838    doSquash(newPC, tid);
839
840    // Tell the CPU to remove any instructions that are not in the ROB.
841    cpu->removeInstsNotInROB(tid);
842}
843
844template <class Impl>
845void
846DefaultFetch<Impl>::tick()
847{
848    list<ThreadID>::iterator threads = activeThreads->begin();
849    list<ThreadID>::iterator end = activeThreads->end();
850    bool status_change = false;
851
852    wroteToTimeBuffer = false;
853
854    while (threads != end) {
855        ThreadID tid = *threads++;
856
857        // Check the signals for each thread to determine the proper status
858        // for each thread.
859        bool updated_status = checkSignalsAndUpdate(tid);
860        status_change =  status_change || updated_status;
861    }
862
863    DPRINTF(Fetch, "Running stage.\n");
864
865    // Reset the number of the instruction we're fetching.
866    numInst = 0;
867
868#if FULL_SYSTEM
869    if (fromCommit->commitInfo[0].interruptPending) {
870        interruptPending = true;
871    }
872
873    if (fromCommit->commitInfo[0].clearInterrupt) {
874        interruptPending = false;
875    }
876#endif
877
878    for (threadFetched = 0; threadFetched < numFetchingThreads;
879         threadFetched++) {
880        // Fetch each of the actively fetching threads.
881        fetch(status_change);
882    }
883
884    // Record number of instructions fetched this cycle for distribution.
885    fetchNisnDist.sample(numInst);
886
887    if (status_change) {
888        // Change the fetch stage status if there was a status change.
889        _status = updateFetchStatus();
890    }
891
892    // If there was activity this cycle, inform the CPU of it.
893    if (wroteToTimeBuffer || cpu->contextSwitch) {
894        DPRINTF(Activity, "Activity this cycle.\n");
895
896        cpu->activityThisCycle();
897    }
898}
899
900template <class Impl>
901bool
902DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
903{
904    // Update the per thread stall statuses.
905    if (fromDecode->decodeBlock[tid]) {
906        stalls[tid].decode = true;
907    }
908
909    if (fromDecode->decodeUnblock[tid]) {
910        assert(stalls[tid].decode);
911        assert(!fromDecode->decodeBlock[tid]);
912        stalls[tid].decode = false;
913    }
914
915    if (fromRename->renameBlock[tid]) {
916        stalls[tid].rename = true;
917    }
918
919    if (fromRename->renameUnblock[tid]) {
920        assert(stalls[tid].rename);
921        assert(!fromRename->renameBlock[tid]);
922        stalls[tid].rename = false;
923    }
924
925    if (fromIEW->iewBlock[tid]) {
926        stalls[tid].iew = true;
927    }
928
929    if (fromIEW->iewUnblock[tid]) {
930        assert(stalls[tid].iew);
931        assert(!fromIEW->iewBlock[tid]);
932        stalls[tid].iew = false;
933    }
934
935    if (fromCommit->commitBlock[tid]) {
936        stalls[tid].commit = true;
937    }
938
939    if (fromCommit->commitUnblock[tid]) {
940        assert(stalls[tid].commit);
941        assert(!fromCommit->commitBlock[tid]);
942        stalls[tid].commit = false;
943    }
944
945    // Check squash signals from commit.
946    if (fromCommit->commitInfo[tid].squash) {
947
948        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
949                "from commit.\n",tid);
950        // In any case, squash.
951        squash(fromCommit->commitInfo[tid].pc,
952               fromCommit->commitInfo[tid].doneSeqNum,
953               fromCommit->commitInfo[tid].squashInst, tid);
954
955        // If it was a branch mispredict on a control instruction, update the
956        // branch predictor with that instruction, otherwise just kill the
957        // invalid state we generated in after sequence number
958        if (fromCommit->commitInfo[tid].mispredictInst &&
959            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
960            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
961                              fromCommit->commitInfo[tid].pc,
962                              fromCommit->commitInfo[tid].branchTaken,
963                              tid);
964        } else {
965            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
966                              tid);
967        }
968
969        return true;
970    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
971        // Update the branch predictor if it wasn't a squashed instruction
972        // that was broadcasted.
973        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
974    }
975
976    // Check ROB squash signals from commit.
977    if (fromCommit->commitInfo[tid].robSquashing) {
978        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
979
980        // Continue to squash.
981        fetchStatus[tid] = Squashing;
982
983        return true;
984    }
985
986    // Check squash signals from decode.
987    if (fromDecode->decodeInfo[tid].squash) {
988        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
989                "from decode.\n",tid);
990
991        // Update the branch predictor.
992        if (fromDecode->decodeInfo[tid].branchMispredict) {
993            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
994                              fromDecode->decodeInfo[tid].nextPC,
995                              fromDecode->decodeInfo[tid].branchTaken,
996                              tid);
997        } else {
998            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
999                              tid);
1000        }
1001
1002        if (fetchStatus[tid] != Squashing) {
1003
1004            TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
1005            DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
1006            // Squash unless we're already squashing
1007            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
1008                             fromDecode->decodeInfo[tid].doneSeqNum,
1009                             tid);
1010
1011            return true;
1012        }
1013    }
1014
1015    if (checkStall(tid) &&
1016        fetchStatus[tid] != IcacheWaitResponse &&
1017        fetchStatus[tid] != IcacheWaitRetry) {
1018        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
1019
1020        fetchStatus[tid] = Blocked;
1021
1022        return true;
1023    }
1024
1025    if (fetchStatus[tid] == Blocked ||
1026        fetchStatus[tid] == Squashing) {
1027        // Switch status to running if fetch isn't being told to block or
1028        // squash this cycle.
1029        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1030                tid);
1031
1032        fetchStatus[tid] = Running;
1033
1034        return true;
1035    }
1036
1037    // If we've reached this point, we have not gotten any signals that
1038    // cause fetch to change its status.  Fetch remains the same as before.
1039    return false;
1040}
1041
1042template<class Impl>
1043typename Impl::DynInstPtr
1044DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
1045                              StaticInstPtr curMacroop, TheISA::PCState thisPC,
1046                              TheISA::PCState nextPC, bool trace)
1047{
1048    // Get a sequence number.
1049    InstSeqNum seq = cpu->getAndIncrementInstSeq();
1050
1051    // Create a new DynInst from the instruction fetched.
1052    DynInstPtr instruction =
1053        new DynInst(staticInst, thisPC, nextPC, seq, cpu);
1054    instruction->setTid(tid);
1055
1056    instruction->setASID(tid);
1057
1058    instruction->setThreadState(cpu->thread[tid]);
1059
1060    DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
1061            "[sn:%lli].\n", tid, thisPC.instAddr(),
1062            thisPC.microPC(), seq);
1063
1064    DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1065            instruction->staticInst->
1066            disassemble(thisPC.instAddr()));
1067
1068#if TRACING_ON
1069    if (trace) {
1070        instruction->traceData =
1071            cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1072                    instruction->staticInst, thisPC, curMacroop);
1073    }
1074#else
1075    instruction->traceData = NULL;
1076#endif
1077
1078    // Add instruction to the CPU's list of instructions.
1079    instruction->setInstListIt(cpu->addInst(instruction));
1080
1081    // Write the instruction to the first slot in the queue
1082    // that heads to decode.
1083    assert(numInst < fetchWidth);
1084    toDecode->insts[toDecode->size++] = instruction;
1085
1086    // Keep track of if we can take an interrupt at this boundary
1087    delayedCommit[tid] = instruction->isDelayedCommit();
1088
1089    return instruction;
1090}
1091
1092template<class Impl>
1093void
1094DefaultFetch<Impl>::fetch(bool &status_change)
1095{
1096    //////////////////////////////////////////
1097    // Start actual fetch
1098    //////////////////////////////////////////
1099    ThreadID tid = getFetchingThread(fetchPolicy);
1100
1101    if (tid == InvalidThreadID || drainPending) {
1102        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1103
1104        // Breaks looping condition in tick()
1105        threadFetched = numFetchingThreads;
1106        return;
1107    }
1108
1109    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1110
1111    // The current PC.
1112    TheISA::PCState thisPC = pc[tid];
1113
1114    Addr pcOffset = fetchOffset[tid];
1115    Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1116
1117    bool inRom = isRomMicroPC(thisPC.microPC());
1118
1119    // If returning from the delay of a cache miss, then update the status
1120    // to running, otherwise do the cache access.  Possibly move this up
1121    // to tick() function.
1122    if (fetchStatus[tid] == IcacheAccessComplete) {
1123        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
1124
1125        fetchStatus[tid] = Running;
1126        status_change = true;
1127    } else if (fetchStatus[tid] == Running) {
1128        // Align the fetch PC so its at the start of a cache block.
1129        Addr block_PC = icacheBlockAlignPC(fetchAddr);
1130
1131        // If buffer is no longer valid or fetchAddr has moved to point
1132        // to the next cache block, AND we have no remaining ucode
1133        // from a macro-op, then start fetch from icache.
1134        if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid])
1135            && !inRom && !macroop[tid]) {
1136            DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1137                    "instruction, starting at PC %s.\n", tid, thisPC);
1138
1139            fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
1140
1141            if (fetchStatus[tid] == IcacheWaitResponse)
1142                ++icacheStallCycles;
1143            else if (fetchStatus[tid] == ItlbWait)
1144                ++fetchTlbCycles;
1145            else
1146                ++fetchMiscStallCycles;
1147            return;
1148        } else if ((checkInterrupt(thisPC.instAddr()) && !delayedCommit[tid])
1149                   || isSwitchedOut()) {
1150            // Stall CPU if an interrupt is posted and we're not issuing
1151            // an delayed commit micro-op currently (delayed commit instructions
1152            // are not interruptable by interrupts, only faults)
1153            ++fetchMiscStallCycles;
1154            return;
1155        }
1156    } else {
1157        if (fetchStatus[tid] == Idle) {
1158            ++fetchIdleCycles;
1159            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1160        } else if (fetchStatus[tid] == Blocked) {
1161            ++fetchBlockedCycles;
1162            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1163        } else if (fetchStatus[tid] == Squashing) {
1164            ++fetchSquashCycles;
1165            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1166        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1167            ++icacheStallCycles;
1168            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
1169                    tid);
1170        } else if (fetchStatus[tid] == ItlbWait) {
1171            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
1172                    "finish! \n", tid);
1173            ++fetchTlbCycles;
1174        } else if (fetchStatus[tid] == TrapPending) {
1175            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
1176                    tid);
1177        } else if (fetchStatus[tid] == NoGoodAddr) {
1178            DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable address\n",
1179                    tid);
1180        }
1181
1182
1183
1184        // Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
1185        // so fetch should do nothing.
1186        return;
1187    }
1188
1189    ++fetchCycles;
1190
1191    TheISA::PCState nextPC = thisPC;
1192
1193    StaticInstPtr staticInst = NULL;
1194    StaticInstPtr curMacroop = macroop[tid];
1195
1196    // If the read of the first instruction was successful, then grab the
1197    // instructions from the rest of the cache line and put them into the
1198    // queue heading to decode.
1199
1200    DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1201            "decode.\n", tid);
1202
1203    // Need to keep track of whether or not a predicted branch
1204    // ended this fetch block.
1205    bool predictedBranch = false;
1206
1207    TheISA::MachInst *cacheInsts =
1208        reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
1209
1210    const unsigned numInsts = cacheBlkSize / instSize;
1211    unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
1212
1213    // Loop through instruction memory from the cache.
1214    // Keep issuing while we have not reached the end of the block or a
1215    // macroop is active and fetchWidth is available and branch is not
1216    // predicted taken
1217    while ((blkOffset < numInsts || curMacroop) &&
1218                           numInst < fetchWidth && !predictedBranch) {
1219
1220        // If we need to process more memory, do it now.
1221        if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
1222            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
1223                // Walk past any annulled delay slot instructions.
1224                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
1225                while (fetchAddr != pcAddr && blkOffset < numInsts) {
1226                    blkOffset++;
1227                    fetchAddr += instSize;
1228                }
1229                if (blkOffset >= numInsts)
1230                    break;
1231            }
1232            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
1233
1234            predecoder.setTC(cpu->thread[tid]->getTC());
1235            predecoder.moreBytes(thisPC, fetchAddr, inst);
1236
1237            if (predecoder.needMoreBytes()) {
1238                blkOffset++;
1239                fetchAddr += instSize;
1240                pcOffset += instSize;
1241            }
1242        }
1243
1244        // Extract as many instructions and/or microops as we can from
1245        // the memory we've processed so far.
1246        do {
1247            if (!(curMacroop || inRom)) {
1248                if (predecoder.extMachInstReady()) {
1249                    ExtMachInst extMachInst;
1250
1251                    extMachInst = predecoder.getExtMachInst(thisPC);
1252                    staticInst = StaticInstPtr(extMachInst,
1253                                               thisPC.instAddr());
1254
1255                    // Increment stat of fetched instructions.
1256                    ++fetchedInsts;
1257
1258                    if (staticInst->isMacroop()) {
1259                        curMacroop = staticInst;
1260                    } else {
1261                        pcOffset = 0;
1262                    }
1263                } else {
1264                    // We need more bytes for this instruction so blkOffset and
1265                    // pcOffset will be updated
1266                    break;
1267                }
1268            }
1269            if (curMacroop || inRom) {
1270                if (inRom) {
1271                    staticInst = cpu->microcodeRom.fetchMicroop(
1272                            thisPC.microPC(), curMacroop);
1273                } else {
1274                    staticInst = curMacroop->fetchMicroop(thisPC.microPC());
1275                }
1276                if (staticInst->isLastMicroop()) {
1277                    curMacroop = NULL;
1278                    pcOffset = 0;
1279                }
1280            }
1281
1282            DynInstPtr instruction =
1283                buildInst(tid, staticInst, curMacroop,
1284                          thisPC, nextPC, true);
1285
1286            numInst++;
1287
1288            nextPC = thisPC;
1289
1290            // If we're branching after this instruction, quite fetching
1291            // from the same block then.
1292            predictedBranch |= thisPC.branching();
1293            predictedBranch |=
1294                lookupAndUpdateNextPC(instruction, nextPC);
1295            if (predictedBranch) {
1296                DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1297            }
1298
1299            // Move to the next instruction, unless we have a branch.
1300            thisPC = nextPC;
1301
1302            if (instruction->isQuiesce()) {
1303                DPRINTF(Fetch,
1304                        "Quiesce instruction encountered, halting fetch!");
1305                fetchStatus[tid] = QuiescePending;
1306                status_change = true;
1307                break;
1308            }
1309        } while ((curMacroop || predecoder.extMachInstReady()) &&
1310                 numInst < fetchWidth);
1311    }
1312
1313    if (predictedBranch) {
1314        DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1315                "instruction encountered.\n", tid);
1316    } else if (numInst >= fetchWidth) {
1317        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1318                "for this cycle.\n", tid);
1319    } else if (blkOffset >= cacheBlkSize) {
1320        DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1321                "block.\n", tid);
1322    }
1323
1324    macroop[tid] = curMacroop;
1325    fetchOffset[tid] = pcOffset;
1326
1327    if (numInst > 0) {
1328        wroteToTimeBuffer = true;
1329    }
1330
1331    pc[tid] = thisPC;
1332}
1333
1334template<class Impl>
1335void
1336DefaultFetch<Impl>::recvRetry()
1337{
1338    if (retryPkt != NULL) {
1339        assert(cacheBlocked);
1340        assert(retryTid != InvalidThreadID);
1341        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1342
1343        if (icachePort->sendTiming(retryPkt)) {
1344            fetchStatus[retryTid] = IcacheWaitResponse;
1345            retryPkt = NULL;
1346            retryTid = InvalidThreadID;
1347            cacheBlocked = false;
1348        }
1349    } else {
1350        assert(retryTid == InvalidThreadID);
1351        // Access has been squashed since it was sent out.  Just clear
1352        // the cache being blocked.
1353        cacheBlocked = false;
1354    }
1355}
1356
1357///////////////////////////////////////
1358//                                   //
1359//  SMT FETCH POLICY MAINTAINED HERE //
1360//                                   //
1361///////////////////////////////////////
1362template<class Impl>
1363ThreadID
1364DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1365{
1366    if (numThreads > 1) {
1367        switch (fetch_priority) {
1368
1369          case SingleThread:
1370            return 0;
1371
1372          case RoundRobin:
1373            return roundRobin();
1374
1375          case IQ:
1376            return iqCount();
1377
1378          case LSQ:
1379            return lsqCount();
1380
1381          case Branch:
1382            return branchCount();
1383
1384          default:
1385            return InvalidThreadID;
1386        }
1387    } else {
1388        list<ThreadID>::iterator thread = activeThreads->begin();
1389        if (thread == activeThreads->end()) {
1390            return InvalidThreadID;
1391        }
1392
1393        ThreadID tid = *thread;
1394
1395        if (fetchStatus[tid] == Running ||
1396            fetchStatus[tid] == IcacheAccessComplete ||
1397            fetchStatus[tid] == Idle) {
1398            return tid;
1399        } else {
1400            return InvalidThreadID;
1401        }
1402    }
1403}
1404
1405
1406template<class Impl>
1407ThreadID
1408DefaultFetch<Impl>::roundRobin()
1409{
1410    list<ThreadID>::iterator pri_iter = priorityList.begin();
1411    list<ThreadID>::iterator end      = priorityList.end();
1412
1413    ThreadID high_pri;
1414
1415    while (pri_iter != end) {
1416        high_pri = *pri_iter;
1417
1418        assert(high_pri <= numThreads);
1419
1420        if (fetchStatus[high_pri] == Running ||
1421            fetchStatus[high_pri] == IcacheAccessComplete ||
1422            fetchStatus[high_pri] == Idle) {
1423
1424            priorityList.erase(pri_iter);
1425            priorityList.push_back(high_pri);
1426
1427            return high_pri;
1428        }
1429
1430        pri_iter++;
1431    }
1432
1433    return InvalidThreadID;
1434}
1435
1436template<class Impl>
1437ThreadID
1438DefaultFetch<Impl>::iqCount()
1439{
1440    std::priority_queue<unsigned> PQ;
1441    std::map<unsigned, ThreadID> threadMap;
1442
1443    list<ThreadID>::iterator threads = activeThreads->begin();
1444    list<ThreadID>::iterator end = activeThreads->end();
1445
1446    while (threads != end) {
1447        ThreadID tid = *threads++;
1448        unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
1449
1450        PQ.push(iqCount);
1451        threadMap[iqCount] = tid;
1452    }
1453
1454    while (!PQ.empty()) {
1455        ThreadID high_pri = threadMap[PQ.top()];
1456
1457        if (fetchStatus[high_pri] == Running ||
1458            fetchStatus[high_pri] == IcacheAccessComplete ||
1459            fetchStatus[high_pri] == Idle)
1460            return high_pri;
1461        else
1462            PQ.pop();
1463
1464    }
1465
1466    return InvalidThreadID;
1467}
1468
1469template<class Impl>
1470ThreadID
1471DefaultFetch<Impl>::lsqCount()
1472{
1473    std::priority_queue<unsigned> PQ;
1474    std::map<unsigned, ThreadID> threadMap;
1475
1476    list<ThreadID>::iterator threads = activeThreads->begin();
1477    list<ThreadID>::iterator end = activeThreads->end();
1478
1479    while (threads != end) {
1480        ThreadID tid = *threads++;
1481        unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
1482
1483        PQ.push(ldstqCount);
1484        threadMap[ldstqCount] = tid;
1485    }
1486
1487    while (!PQ.empty()) {
1488        ThreadID high_pri = threadMap[PQ.top()];
1489
1490        if (fetchStatus[high_pri] == Running ||
1491            fetchStatus[high_pri] == IcacheAccessComplete ||
1492            fetchStatus[high_pri] == Idle)
1493            return high_pri;
1494        else
1495            PQ.pop();
1496    }
1497
1498    return InvalidThreadID;
1499}
1500
1501template<class Impl>
1502ThreadID
1503DefaultFetch<Impl>::branchCount()
1504{
1505#if 0
1506    list<ThreadID>::iterator thread = activeThreads->begin();
1507    assert(thread != activeThreads->end());
1508    ThreadID tid = *thread;
1509#endif
1510
1511    panic("Branch Count Fetch policy unimplemented\n");
1512    return InvalidThreadID;
1513}
1514