fetch_impl.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include <algorithm>
33#include <cstring>
34
35#include "arch/isa_traits.hh"
36#include "arch/utility.hh"
37#include "base/types.hh"
38#include "config/the_isa.hh"
39#include "config/use_checker.hh"
40#include "cpu/checker/cpu.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/fetch.hh"
43#include "mem/packet.hh"
44#include "mem/request.hh"
45#include "params/DerivO3CPU.hh"
46#include "sim/byteswap.hh"
47#include "sim/core.hh"
48
49#if FULL_SYSTEM
50#include "arch/tlb.hh"
51#include "arch/vtophys.hh"
52#include "sim/system.hh"
53#endif // FULL_SYSTEM
54
55using namespace std;
56
57template<class Impl>
58void
59DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
60{
61    Port::setPeer(port);
62
63    fetch->setIcache();
64}
65
66template<class Impl>
67Tick
68DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
69{
70    panic("DefaultFetch doesn't expect recvAtomic callback!");
71    return curTick;
72}
73
74template<class Impl>
75void
76DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
77{
78    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
79            "functional call.");
80}
81
82template<class Impl>
83void
84DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
85{
86    if (status == RangeChange) {
87        if (!snoopRangeSent) {
88            snoopRangeSent = true;
89            sendStatusChange(Port::RangeChange);
90        }
91        return;
92    }
93
94    panic("DefaultFetch doesn't expect recvStatusChange callback!");
95}
96
97template<class Impl>
98bool
99DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
100{
101    DPRINTF(Fetch, "Received timing\n");
102    if (pkt->isResponse()) {
103        fetch->processCacheCompletion(pkt);
104    }
105    //else Snooped a coherence request, just return
106    return true;
107}
108
109template<class Impl>
110void
111DefaultFetch<Impl>::IcachePort::recvRetry()
112{
113    fetch->recvRetry();
114}
115
116template<class Impl>
117DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
118    : cpu(_cpu),
119      branchPred(params),
120      predecoder(NULL),
121      decodeToFetchDelay(params->decodeToFetchDelay),
122      renameToFetchDelay(params->renameToFetchDelay),
123      iewToFetchDelay(params->iewToFetchDelay),
124      commitToFetchDelay(params->commitToFetchDelay),
125      fetchWidth(params->fetchWidth),
126      cacheBlocked(false),
127      retryPkt(NULL),
128      retryTid(InvalidThreadID),
129      numThreads(params->numThreads),
130      numFetchingThreads(params->smtNumFetchingThreads),
131      interruptPending(false),
132      drainPending(false),
133      switchedOut(false)
134{
135    if (numThreads > Impl::MaxThreads)
136        fatal("numThreads (%d) is larger than compiled limit (%d),\n"
137              "\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
138              numThreads, static_cast<int>(Impl::MaxThreads));
139
140    // Set fetch stage's status to inactive.
141    _status = Inactive;
142
143    std::string policy = params->smtFetchPolicy;
144
145    // Convert string to lowercase
146    std::transform(policy.begin(), policy.end(), policy.begin(),
147                   (int(*)(int)) tolower);
148
149    // Figure out fetch policy
150    if (policy == "singlethread") {
151        fetchPolicy = SingleThread;
152        if (numThreads > 1)
153            panic("Invalid Fetch Policy for a SMT workload.");
154    } else if (policy == "roundrobin") {
155        fetchPolicy = RoundRobin;
156        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
157    } else if (policy == "branch") {
158        fetchPolicy = Branch;
159        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
160    } else if (policy == "iqcount") {
161        fetchPolicy = IQ;
162        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
163    } else if (policy == "lsqcount") {
164        fetchPolicy = LSQ;
165        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
166    } else {
167        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
168              " RoundRobin,LSQcount,IQcount}\n");
169    }
170
171    // Get the size of an instruction.
172    instSize = sizeof(TheISA::MachInst);
173
174    // Name is finally available, so create the port.
175    icachePort = new IcachePort(this);
176
177    icachePort->snoopRangeSent = false;
178
179#if USE_CHECKER
180    if (cpu->checker) {
181        cpu->checker->setIcachePort(icachePort);
182    }
183#endif
184}
185
186template <class Impl>
187std::string
188DefaultFetch<Impl>::name() const
189{
190    return cpu->name() + ".fetch";
191}
192
193template <class Impl>
194void
195DefaultFetch<Impl>::regStats()
196{
197    icacheStallCycles
198        .name(name() + ".icacheStallCycles")
199        .desc("Number of cycles fetch is stalled on an Icache miss")
200        .prereq(icacheStallCycles);
201
202    fetchedInsts
203        .name(name() + ".Insts")
204        .desc("Number of instructions fetch has processed")
205        .prereq(fetchedInsts);
206
207    fetchedBranches
208        .name(name() + ".Branches")
209        .desc("Number of branches that fetch encountered")
210        .prereq(fetchedBranches);
211
212    predictedBranches
213        .name(name() + ".predictedBranches")
214        .desc("Number of branches that fetch has predicted taken")
215        .prereq(predictedBranches);
216
217    fetchCycles
218        .name(name() + ".Cycles")
219        .desc("Number of cycles fetch has run and was not squashing or"
220              " blocked")
221        .prereq(fetchCycles);
222
223    fetchSquashCycles
224        .name(name() + ".SquashCycles")
225        .desc("Number of cycles fetch has spent squashing")
226        .prereq(fetchSquashCycles);
227
228    fetchIdleCycles
229        .name(name() + ".IdleCycles")
230        .desc("Number of cycles fetch was idle")
231        .prereq(fetchIdleCycles);
232
233    fetchBlockedCycles
234        .name(name() + ".BlockedCycles")
235        .desc("Number of cycles fetch has spent blocked")
236        .prereq(fetchBlockedCycles);
237
238    fetchedCacheLines
239        .name(name() + ".CacheLines")
240        .desc("Number of cache lines fetched")
241        .prereq(fetchedCacheLines);
242
243    fetchMiscStallCycles
244        .name(name() + ".MiscStallCycles")
245        .desc("Number of cycles fetch has spent waiting on interrupts, or "
246              "bad addresses, or out of MSHRs")
247        .prereq(fetchMiscStallCycles);
248
249    fetchIcacheSquashes
250        .name(name() + ".IcacheSquashes")
251        .desc("Number of outstanding Icache misses that were squashed")
252        .prereq(fetchIcacheSquashes);
253
254    fetchNisnDist
255        .init(/* base value */ 0,
256              /* last value */ fetchWidth,
257              /* bucket size */ 1)
258        .name(name() + ".rateDist")
259        .desc("Number of instructions fetched each cycle (Total)")
260        .flags(Stats::pdf);
261
262    idleRate
263        .name(name() + ".idleRate")
264        .desc("Percent of cycles fetch was idle")
265        .prereq(idleRate);
266    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
267
268    branchRate
269        .name(name() + ".branchRate")
270        .desc("Number of branch fetches per cycle")
271        .flags(Stats::total);
272    branchRate = fetchedBranches / cpu->numCycles;
273
274    fetchRate
275        .name(name() + ".rate")
276        .desc("Number of inst fetches per cycle")
277        .flags(Stats::total);
278    fetchRate = fetchedInsts / cpu->numCycles;
279
280    branchPred.regStats();
281}
282
283template<class Impl>
284void
285DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
286{
287    timeBuffer = time_buffer;
288
289    // Create wires to get information from proper places in time buffer.
290    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
291    fromRename = timeBuffer->getWire(-renameToFetchDelay);
292    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
293    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
294}
295
296template<class Impl>
297void
298DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
299{
300    activeThreads = at_ptr;
301}
302
303template<class Impl>
304void
305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
306{
307    fetchQueue = fq_ptr;
308
309    // Create wire to write information to proper place in fetch queue.
310    toDecode = fetchQueue->getWire(0);
311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::initStage()
316{
317    // Setup PC and nextPC with initial state.
318    for (ThreadID tid = 0; tid < numThreads; tid++) {
319        pc[tid] = cpu->pcState(tid);
320    }
321
322    for (ThreadID tid = 0; tid < numThreads; tid++) {
323
324        fetchStatus[tid] = Running;
325
326        priorityList.push_back(tid);
327
328        memReq[tid] = NULL;
329
330        stalls[tid].decode = false;
331        stalls[tid].rename = false;
332        stalls[tid].iew = false;
333        stalls[tid].commit = false;
334    }
335
336    // Schedule fetch to get the correct PC from the CPU
337    // scheduleFetchStartupEvent(1);
338
339    // Fetch needs to start fetching instructions at the very beginning,
340    // so it must start up in active state.
341    switchToActive();
342}
343
344template<class Impl>
345void
346DefaultFetch<Impl>::setIcache()
347{
348    // Size of cache block.
349    cacheBlkSize = icachePort->peerBlockSize();
350
351    // Create mask to get rid of offset bits.
352    cacheBlkMask = (cacheBlkSize - 1);
353
354    for (ThreadID tid = 0; tid < numThreads; tid++) {
355        // Create space to store a cache line.
356        cacheData[tid] = new uint8_t[cacheBlkSize];
357        cacheDataPC[tid] = 0;
358        cacheDataValid[tid] = false;
359    }
360}
361
362template<class Impl>
363void
364DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
365{
366    ThreadID tid = pkt->req->threadId();
367
368    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
369
370    assert(!pkt->wasNacked());
371
372    // Only change the status if it's still waiting on the icache access
373    // to return.
374    if (fetchStatus[tid] != IcacheWaitResponse ||
375        pkt->req != memReq[tid] ||
376        isSwitchedOut()) {
377        ++fetchIcacheSquashes;
378        delete pkt->req;
379        delete pkt;
380        return;
381    }
382
383    memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
384    cacheDataValid[tid] = true;
385
386    if (!drainPending) {
387        // Wake up the CPU (if it went to sleep and was waiting on
388        // this completion event).
389        cpu->wakeCPU();
390
391        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
392                tid);
393
394        switchToActive();
395    }
396
397    // Only switch to IcacheAccessComplete if we're not stalled as well.
398    if (checkStall(tid)) {
399        fetchStatus[tid] = Blocked;
400    } else {
401        fetchStatus[tid] = IcacheAccessComplete;
402    }
403
404    // Reset the mem req to NULL.
405    delete pkt->req;
406    delete pkt;
407    memReq[tid] = NULL;
408}
409
410template <class Impl>
411bool
412DefaultFetch<Impl>::drain()
413{
414    // Fetch is ready to drain at any time.
415    cpu->signalDrained();
416    drainPending = true;
417    return true;
418}
419
420template <class Impl>
421void
422DefaultFetch<Impl>::resume()
423{
424    drainPending = false;
425}
426
427template <class Impl>
428void
429DefaultFetch<Impl>::switchOut()
430{
431    switchedOut = true;
432    // Branch predictor needs to have its state cleared.
433    branchPred.switchOut();
434}
435
436template <class Impl>
437void
438DefaultFetch<Impl>::takeOverFrom()
439{
440    // Reset all state
441    for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
442        stalls[i].decode = 0;
443        stalls[i].rename = 0;
444        stalls[i].iew = 0;
445        stalls[i].commit = 0;
446        pc[i] = cpu->pcState(i);
447        fetchStatus[i] = Running;
448    }
449    numInst = 0;
450    wroteToTimeBuffer = false;
451    _status = Inactive;
452    switchedOut = false;
453    interruptPending = false;
454    branchPred.takeOverFrom();
455}
456
457template <class Impl>
458void
459DefaultFetch<Impl>::wakeFromQuiesce()
460{
461    DPRINTF(Fetch, "Waking up from quiesce\n");
462    // Hopefully this is safe
463    // @todo: Allow other threads to wake from quiesce.
464    fetchStatus[0] = Running;
465}
466
467template <class Impl>
468inline void
469DefaultFetch<Impl>::switchToActive()
470{
471    if (_status == Inactive) {
472        DPRINTF(Activity, "Activating stage.\n");
473
474        cpu->activateStage(O3CPU::FetchIdx);
475
476        _status = Active;
477    }
478}
479
480template <class Impl>
481inline void
482DefaultFetch<Impl>::switchToInactive()
483{
484    if (_status == Active) {
485        DPRINTF(Activity, "Deactivating stage.\n");
486
487        cpu->deactivateStage(O3CPU::FetchIdx);
488
489        _status = Inactive;
490    }
491}
492
493template <class Impl>
494bool
495DefaultFetch<Impl>::lookupAndUpdateNextPC(
496        DynInstPtr &inst, TheISA::PCState &nextPC)
497{
498    // Do branch prediction check here.
499    // A bit of a misnomer...next_PC is actually the current PC until
500    // this function updates it.
501    bool predict_taken;
502
503    if (!inst->isControl()) {
504        TheISA::advancePC(nextPC, inst->staticInst);
505        inst->setPredTarg(nextPC);
506        inst->setPredTaken(false);
507        return false;
508    }
509
510    ThreadID tid = inst->threadNumber;
511    predict_taken = branchPred.predict(inst, nextPC, tid);
512
513    if (predict_taken) {
514        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:  Branch predicted to be taken to %s.\n",
515                tid, inst->seqNum, nextPC);
516    } else {
517        DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
518                tid, inst->seqNum);
519    }
520
521    DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
522            tid, inst->seqNum, nextPC);
523    inst->setPredTarg(nextPC);
524    inst->setPredTaken(predict_taken);
525
526    ++fetchedBranches;
527
528    if (predict_taken) {
529        ++predictedBranches;
530    }
531
532    return predict_taken;
533}
534
535template <class Impl>
536bool
537DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid)
538{
539    Fault fault = NoFault;
540
541    //AlphaDep
542    if (cacheBlocked) {
543        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
544                tid);
545        return false;
546    } else if (isSwitchedOut()) {
547        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
548                tid);
549        return false;
550    } else if (interruptPending && !(fetch_PC & 0x3)) {
551        // Hold off fetch from getting new instructions when:
552        // Cache is blocked, or
553        // while an interrupt is pending and we're not in PAL mode, or
554        // fetch is switched out.
555        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
556                tid);
557        return false;
558    }
559
560    // Align the fetch PC so it's at the start of a cache block.
561    Addr block_PC = icacheBlockAlignPC(fetch_PC);
562
563    // If we've already got the block, no need to try to fetch it again.
564    if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
565        return true;
566    }
567
568    // Setup the memReq to do a read of the first instruction's address.
569    // Set the appropriate read size and flags as well.
570    // Build request here.
571    RequestPtr mem_req =
572        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
573                    fetch_PC, cpu->thread[tid]->contextId(), tid);
574
575    memReq[tid] = mem_req;
576
577    // Translate the instruction request.
578    fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
579                                      BaseTLB::Execute);
580
581    // In the case of faults, the fetch stage may need to stall and wait
582    // for the ITB miss to be handled.
583
584    // If translation was successful, attempt to read the first
585    // instruction.
586    if (fault == NoFault) {
587#if 0
588        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
589            memReq[tid]->isUncacheable()) {
590            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
591                    "misspeculating path)!",
592                    memReq[tid]->paddr);
593            ret_fault = TheISA::genMachineCheckFault();
594            return false;
595        }
596#endif
597
598        // Build packet here.
599        PacketPtr data_pkt = new Packet(mem_req,
600                                        MemCmd::ReadReq, Packet::Broadcast);
601        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
602
603        cacheDataPC[tid] = block_PC;
604        cacheDataValid[tid] = false;
605
606        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
607
608        fetchedCacheLines++;
609
610        // Now do the timing access to see whether or not the instruction
611        // exists within the cache.
612        if (!icachePort->sendTiming(data_pkt)) {
613            assert(retryPkt == NULL);
614            assert(retryTid == InvalidThreadID);
615            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
616            fetchStatus[tid] = IcacheWaitRetry;
617            retryPkt = data_pkt;
618            retryTid = tid;
619            cacheBlocked = true;
620            return false;
621        }
622
623        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
624
625        lastIcacheStall[tid] = curTick;
626
627        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
628                "response.\n", tid);
629
630        fetchStatus[tid] = IcacheWaitResponse;
631    } else {
632        delete mem_req;
633        memReq[tid] = NULL;
634    }
635
636    ret_fault = fault;
637    return true;
638}
639
640template <class Impl>
641inline void
642DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
643{
644    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
645            tid, newPC);
646
647    pc[tid] = newPC;
648
649    // Clear the icache miss if it's outstanding.
650    if (fetchStatus[tid] == IcacheWaitResponse) {
651        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
652                tid);
653        memReq[tid] = NULL;
654    }
655
656    // Get rid of the retrying packet if it was from this thread.
657    if (retryTid == tid) {
658        assert(cacheBlocked);
659        if (retryPkt) {
660            delete retryPkt->req;
661            delete retryPkt;
662        }
663        retryPkt = NULL;
664        retryTid = InvalidThreadID;
665    }
666
667    fetchStatus[tid] = Squashing;
668
669    ++fetchSquashCycles;
670}
671
672template<class Impl>
673void
674DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
675                                     const InstSeqNum &seq_num, ThreadID tid)
676{
677    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
678
679    doSquash(newPC, tid);
680
681    // Tell the CPU to remove any instructions that are in flight between
682    // fetch and decode.
683    cpu->removeInstsUntil(seq_num, tid);
684}
685
686template<class Impl>
687bool
688DefaultFetch<Impl>::checkStall(ThreadID tid) const
689{
690    bool ret_val = false;
691
692    if (cpu->contextSwitch) {
693        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
694        ret_val = true;
695    } else if (stalls[tid].decode) {
696        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
697        ret_val = true;
698    } else if (stalls[tid].rename) {
699        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
700        ret_val = true;
701    } else if (stalls[tid].iew) {
702        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
703        ret_val = true;
704    } else if (stalls[tid].commit) {
705        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
706        ret_val = true;
707    }
708
709    return ret_val;
710}
711
712template<class Impl>
713typename DefaultFetch<Impl>::FetchStatus
714DefaultFetch<Impl>::updateFetchStatus()
715{
716    //Check Running
717    list<ThreadID>::iterator threads = activeThreads->begin();
718    list<ThreadID>::iterator end = activeThreads->end();
719
720    while (threads != end) {
721        ThreadID tid = *threads++;
722
723        if (fetchStatus[tid] == Running ||
724            fetchStatus[tid] == Squashing ||
725            fetchStatus[tid] == IcacheAccessComplete) {
726
727            if (_status == Inactive) {
728                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
729
730                if (fetchStatus[tid] == IcacheAccessComplete) {
731                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
732                            "completion\n",tid);
733                }
734
735                cpu->activateStage(O3CPU::FetchIdx);
736            }
737
738            return Active;
739        }
740    }
741
742    // Stage is switching from active to inactive, notify CPU of it.
743    if (_status == Active) {
744        DPRINTF(Activity, "Deactivating stage.\n");
745
746        cpu->deactivateStage(O3CPU::FetchIdx);
747    }
748
749    return Inactive;
750}
751
752template <class Impl>
753void
754DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
755                           const InstSeqNum &seq_num, ThreadID tid)
756{
757    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
758
759    doSquash(newPC, tid);
760
761    // Tell the CPU to remove any instructions that are not in the ROB.
762    cpu->removeInstsNotInROB(tid);
763}
764
765template <class Impl>
766void
767DefaultFetch<Impl>::tick()
768{
769    list<ThreadID>::iterator threads = activeThreads->begin();
770    list<ThreadID>::iterator end = activeThreads->end();
771    bool status_change = false;
772
773    wroteToTimeBuffer = false;
774
775    while (threads != end) {
776        ThreadID tid = *threads++;
777
778        // Check the signals for each thread to determine the proper status
779        // for each thread.
780        bool updated_status = checkSignalsAndUpdate(tid);
781        status_change =  status_change || updated_status;
782    }
783
784    DPRINTF(Fetch, "Running stage.\n");
785
786    // Reset the number of the instruction we're fetching.
787    numInst = 0;
788
789#if FULL_SYSTEM
790    if (fromCommit->commitInfo[0].interruptPending) {
791        interruptPending = true;
792    }
793
794    if (fromCommit->commitInfo[0].clearInterrupt) {
795        interruptPending = false;
796    }
797#endif
798
799    for (threadFetched = 0; threadFetched < numFetchingThreads;
800         threadFetched++) {
801        // Fetch each of the actively fetching threads.
802        fetch(status_change);
803    }
804
805    // Record number of instructions fetched this cycle for distribution.
806    fetchNisnDist.sample(numInst);
807
808    if (status_change) {
809        // Change the fetch stage status if there was a status change.
810        _status = updateFetchStatus();
811    }
812
813    // If there was activity this cycle, inform the CPU of it.
814    if (wroteToTimeBuffer || cpu->contextSwitch) {
815        DPRINTF(Activity, "Activity this cycle.\n");
816
817        cpu->activityThisCycle();
818    }
819}
820
821template <class Impl>
822bool
823DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
824{
825    // Update the per thread stall statuses.
826    if (fromDecode->decodeBlock[tid]) {
827        stalls[tid].decode = true;
828    }
829
830    if (fromDecode->decodeUnblock[tid]) {
831        assert(stalls[tid].decode);
832        assert(!fromDecode->decodeBlock[tid]);
833        stalls[tid].decode = false;
834    }
835
836    if (fromRename->renameBlock[tid]) {
837        stalls[tid].rename = true;
838    }
839
840    if (fromRename->renameUnblock[tid]) {
841        assert(stalls[tid].rename);
842        assert(!fromRename->renameBlock[tid]);
843        stalls[tid].rename = false;
844    }
845
846    if (fromIEW->iewBlock[tid]) {
847        stalls[tid].iew = true;
848    }
849
850    if (fromIEW->iewUnblock[tid]) {
851        assert(stalls[tid].iew);
852        assert(!fromIEW->iewBlock[tid]);
853        stalls[tid].iew = false;
854    }
855
856    if (fromCommit->commitBlock[tid]) {
857        stalls[tid].commit = true;
858    }
859
860    if (fromCommit->commitUnblock[tid]) {
861        assert(stalls[tid].commit);
862        assert(!fromCommit->commitBlock[tid]);
863        stalls[tid].commit = false;
864    }
865
866    // Check squash signals from commit.
867    if (fromCommit->commitInfo[tid].squash) {
868
869        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
870                "from commit.\n",tid);
871        // In any case, squash.
872        squash(fromCommit->commitInfo[tid].pc,
873               fromCommit->commitInfo[tid].doneSeqNum,
874               tid);
875
876        // Also check if there's a mispredict that happened.
877        if (fromCommit->commitInfo[tid].branchMispredict) {
878            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
879                              fromCommit->commitInfo[tid].pc,
880                              fromCommit->commitInfo[tid].branchTaken,
881                              tid);
882        } else {
883            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
884                              tid);
885        }
886
887        return true;
888    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
889        // Update the branch predictor if it wasn't a squashed instruction
890        // that was broadcasted.
891        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
892    }
893
894    // Check ROB squash signals from commit.
895    if (fromCommit->commitInfo[tid].robSquashing) {
896        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
897
898        // Continue to squash.
899        fetchStatus[tid] = Squashing;
900
901        return true;
902    }
903
904    // Check squash signals from decode.
905    if (fromDecode->decodeInfo[tid].squash) {
906        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
907                "from decode.\n",tid);
908
909        // Update the branch predictor.
910        if (fromDecode->decodeInfo[tid].branchMispredict) {
911            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
912                              fromDecode->decodeInfo[tid].nextPC,
913                              fromDecode->decodeInfo[tid].branchTaken,
914                              tid);
915        } else {
916            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
917                              tid);
918        }
919
920        if (fetchStatus[tid] != Squashing) {
921
922            TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
923            DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
924            // Squash unless we're already squashing
925            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
926                             fromDecode->decodeInfo[tid].doneSeqNum,
927                             tid);
928
929            return true;
930        }
931    }
932
933    if (checkStall(tid) &&
934        fetchStatus[tid] != IcacheWaitResponse &&
935        fetchStatus[tid] != IcacheWaitRetry) {
936        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
937
938        fetchStatus[tid] = Blocked;
939
940        return true;
941    }
942
943    if (fetchStatus[tid] == Blocked ||
944        fetchStatus[tid] == Squashing) {
945        // Switch status to running if fetch isn't being told to block or
946        // squash this cycle.
947        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
948                tid);
949
950        fetchStatus[tid] = Running;
951
952        return true;
953    }
954
955    // If we've reached this point, we have not gotten any signals that
956    // cause fetch to change its status.  Fetch remains the same as before.
957    return false;
958}
959
960template<class Impl>
961void
962DefaultFetch<Impl>::fetch(bool &status_change)
963{
964    //////////////////////////////////////////
965    // Start actual fetch
966    //////////////////////////////////////////
967    ThreadID tid = getFetchingThread(fetchPolicy);
968
969    if (tid == InvalidThreadID || drainPending) {
970        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
971
972        // Breaks looping condition in tick()
973        threadFetched = numFetchingThreads;
974        return;
975    }
976
977    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
978
979    // The current PC.
980    TheISA::PCState fetchPC = pc[tid];
981
982    // Fault code for memory access.
983    Fault fault = NoFault;
984
985    // If returning from the delay of a cache miss, then update the status
986    // to running, otherwise do the cache access.  Possibly move this up
987    // to tick() function.
988    if (fetchStatus[tid] == IcacheAccessComplete) {
989        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
990                tid);
991
992        fetchStatus[tid] = Running;
993        status_change = true;
994    } else if (fetchStatus[tid] == Running) {
995        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
996                "instruction, starting at PC %s.\n", tid, fetchPC);
997
998        bool fetch_success = fetchCacheLine(fetchPC.instAddr(), fault, tid);
999        if (!fetch_success) {
1000            if (cacheBlocked) {
1001                ++icacheStallCycles;
1002            } else {
1003                ++fetchMiscStallCycles;
1004            }
1005            return;
1006        }
1007    } else {
1008        if (fetchStatus[tid] == Idle) {
1009            ++fetchIdleCycles;
1010            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1011        } else if (fetchStatus[tid] == Blocked) {
1012            ++fetchBlockedCycles;
1013            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1014        } else if (fetchStatus[tid] == Squashing) {
1015            ++fetchSquashCycles;
1016            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1017        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1018            ++icacheStallCycles;
1019            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1020        }
1021
1022        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1023        // fetch should do nothing.
1024        return;
1025    }
1026
1027    ++fetchCycles;
1028
1029    // If we had a stall due to an icache miss, then return.
1030    if (fetchStatus[tid] == IcacheWaitResponse) {
1031        ++icacheStallCycles;
1032        status_change = true;
1033        return;
1034    }
1035
1036    TheISA::PCState nextPC = fetchPC;
1037
1038    InstSeqNum inst_seq;
1039    MachInst inst;
1040    ExtMachInst ext_inst;
1041
1042    StaticInstPtr staticInst = NULL;
1043    StaticInstPtr macroop = NULL;
1044
1045    if (fault == NoFault) {
1046        //XXX Masking out pal mode bit. This will break x86. Alpha needs
1047        //to pull the pal mode bit ouf ot the instruction address.
1048        unsigned offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
1049        assert(offset < cacheBlkSize);
1050
1051        // If the read of the first instruction was successful, then grab the
1052        // instructions from the rest of the cache line and put them into the
1053        // queue heading to decode.
1054
1055        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1056                "decode.\n",tid);
1057
1058        // Need to keep track of whether or not a predicted branch
1059        // ended this fetch block.
1060        bool predicted_branch = false;
1061
1062        while (offset < cacheBlkSize &&
1063               numInst < fetchWidth &&
1064               !predicted_branch) {
1065
1066            // Make sure this is a valid index.
1067            assert(offset <= cacheBlkSize - instSize);
1068
1069            if (!macroop) {
1070                // Get the instruction from the array of the cache line.
1071                inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1072                            (&cacheData[tid][offset]));
1073
1074                predecoder.setTC(cpu->thread[tid]->getTC());
1075                predecoder.moreBytes(fetchPC, fetchPC.instAddr(), inst);
1076
1077                ext_inst = predecoder.getExtMachInst(fetchPC);
1078                staticInst = StaticInstPtr(ext_inst, fetchPC.instAddr());
1079                if (staticInst->isMacroop())
1080                    macroop = staticInst;
1081            }
1082            do {
1083                if (macroop) {
1084                    staticInst = macroop->fetchMicroop(fetchPC.microPC());
1085                    if (staticInst->isLastMicroop())
1086                        macroop = NULL;
1087                }
1088
1089                // Get a sequence number.
1090                inst_seq = cpu->getAndIncrementInstSeq();
1091
1092                // Create a new DynInst from the instruction fetched.
1093                DynInstPtr instruction = new DynInst(staticInst,
1094                                                     fetchPC, nextPC,
1095                                                     inst_seq, cpu);
1096                instruction->setTid(tid);
1097
1098                instruction->setASID(tid);
1099
1100                instruction->setThreadState(cpu->thread[tid]);
1101
1102                DPRINTF(Fetch, "[tid:%i]: Instruction PC %s (%d) created "
1103                        "[sn:%lli]\n", tid, instruction->pcState(),
1104                        instruction->microPC(), inst_seq);
1105
1106                //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1107
1108                DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
1109                        instruction->staticInst->
1110                        disassemble(fetchPC.instAddr()));
1111
1112#if TRACING_ON
1113                instruction->traceData =
1114                    cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
1115                            instruction->staticInst, fetchPC, macroop);
1116#else
1117                instruction->traceData = NULL;
1118#endif
1119
1120                // If we're branching after this instruction, quite fetching
1121                // from the same block then.
1122                predicted_branch = fetchPC.branching();
1123                predicted_branch |=
1124                    lookupAndUpdateNextPC(instruction, nextPC);
1125                if (predicted_branch) {
1126                    DPRINTF(Fetch, "Branch detected with PC = %s\n", fetchPC);
1127                }
1128
1129                // Add instruction to the CPU's list of instructions.
1130                instruction->setInstListIt(cpu->addInst(instruction));
1131
1132                // Write the instruction to the first slot in the queue
1133                // that heads to decode.
1134                toDecode->insts[numInst] = instruction;
1135
1136                toDecode->size++;
1137
1138                // Increment stat of fetched instructions.
1139                ++fetchedInsts;
1140
1141                // Move to the next instruction, unless we have a branch.
1142                fetchPC = nextPC;
1143
1144                if (instruction->isQuiesce()) {
1145                    DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1146                            curTick);
1147                    fetchStatus[tid] = QuiescePending;
1148                    ++numInst;
1149                    status_change = true;
1150                    break;
1151                }
1152
1153                ++numInst;
1154            } while (staticInst->isMicroop() &&
1155                     !staticInst->isLastMicroop() &&
1156                     numInst < fetchWidth);
1157            //XXX Masking out pal mode bit.
1158            offset = (fetchPC.instAddr() & ~1) - cacheDataPC[tid];
1159        }
1160
1161        if (predicted_branch) {
1162            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1163                    "instruction encountered.\n", tid);
1164        } else if (numInst >= fetchWidth) {
1165            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1166                    "for this cycle.\n", tid);
1167        } else if (offset >= cacheBlkSize) {
1168            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1169                    "block.\n", tid);
1170        }
1171    }
1172
1173    if (numInst > 0) {
1174        wroteToTimeBuffer = true;
1175    }
1176
1177    // Now that fetching is completed, update the PC to signify what the next
1178    // cycle will be.
1179    if (fault == NoFault) {
1180        pc[tid] = nextPC;
1181        DPRINTF(Fetch, "[tid:%i]: Setting PC to %s.\n", tid, nextPC);
1182    } else {
1183        // We shouldn't be in an icache miss and also have a fault (an ITB
1184        // miss)
1185        if (fetchStatus[tid] == IcacheWaitResponse) {
1186            panic("Fetch should have exited prior to this!");
1187        }
1188
1189        // Send the fault to commit.  This thread will not do anything
1190        // until commit handles the fault.  The only other way it can
1191        // wake up is if a squash comes along and changes the PC.
1192        assert(numInst < fetchWidth);
1193        // Get a sequence number.
1194        inst_seq = cpu->getAndIncrementInstSeq();
1195        // We will use a nop in order to carry the fault.
1196        ext_inst = TheISA::NoopMachInst;
1197
1198        // Create a new DynInst from the dummy nop.
1199        DynInstPtr instruction = new DynInst(ext_inst, fetchPC, nextPC,
1200                                             inst_seq, cpu);
1201        TheISA::advancePC(nextPC, instruction->staticInst);
1202        instruction->setPredTarg(nextPC);
1203        instruction->setTid(tid);
1204
1205        instruction->setASID(tid);
1206
1207        instruction->setThreadState(cpu->thread[tid]);
1208
1209        instruction->traceData = NULL;
1210
1211        instruction->setInstListIt(cpu->addInst(instruction));
1212
1213        instruction->fault = fault;
1214
1215        toDecode->insts[numInst] = instruction;
1216        toDecode->size++;
1217
1218        wroteToTimeBuffer = true;
1219
1220        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1221
1222        fetchStatus[tid] = TrapPending;
1223        status_change = true;
1224
1225        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
1226                tid, fault->name(), pc[tid]);
1227    }
1228}
1229
1230template<class Impl>
1231void
1232DefaultFetch<Impl>::recvRetry()
1233{
1234    if (retryPkt != NULL) {
1235        assert(cacheBlocked);
1236        assert(retryTid != InvalidThreadID);
1237        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1238
1239        if (icachePort->sendTiming(retryPkt)) {
1240            fetchStatus[retryTid] = IcacheWaitResponse;
1241            retryPkt = NULL;
1242            retryTid = InvalidThreadID;
1243            cacheBlocked = false;
1244        }
1245    } else {
1246        assert(retryTid == InvalidThreadID);
1247        // Access has been squashed since it was sent out.  Just clear
1248        // the cache being blocked.
1249        cacheBlocked = false;
1250    }
1251}
1252
1253///////////////////////////////////////
1254//                                   //
1255//  SMT FETCH POLICY MAINTAINED HERE //
1256//                                   //
1257///////////////////////////////////////
1258template<class Impl>
1259ThreadID
1260DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1261{
1262    if (numThreads > 1) {
1263        switch (fetch_priority) {
1264
1265          case SingleThread:
1266            return 0;
1267
1268          case RoundRobin:
1269            return roundRobin();
1270
1271          case IQ:
1272            return iqCount();
1273
1274          case LSQ:
1275            return lsqCount();
1276
1277          case Branch:
1278            return branchCount();
1279
1280          default:
1281            return InvalidThreadID;
1282        }
1283    } else {
1284        list<ThreadID>::iterator thread = activeThreads->begin();
1285        if (thread == activeThreads->end()) {
1286            return InvalidThreadID;
1287        }
1288
1289        ThreadID tid = *thread;
1290
1291        if (fetchStatus[tid] == Running ||
1292            fetchStatus[tid] == IcacheAccessComplete ||
1293            fetchStatus[tid] == Idle) {
1294            return tid;
1295        } else {
1296            return InvalidThreadID;
1297        }
1298    }
1299}
1300
1301
1302template<class Impl>
1303ThreadID
1304DefaultFetch<Impl>::roundRobin()
1305{
1306    list<ThreadID>::iterator pri_iter = priorityList.begin();
1307    list<ThreadID>::iterator end      = priorityList.end();
1308
1309    ThreadID high_pri;
1310
1311    while (pri_iter != end) {
1312        high_pri = *pri_iter;
1313
1314        assert(high_pri <= numThreads);
1315
1316        if (fetchStatus[high_pri] == Running ||
1317            fetchStatus[high_pri] == IcacheAccessComplete ||
1318            fetchStatus[high_pri] == Idle) {
1319
1320            priorityList.erase(pri_iter);
1321            priorityList.push_back(high_pri);
1322
1323            return high_pri;
1324        }
1325
1326        pri_iter++;
1327    }
1328
1329    return InvalidThreadID;
1330}
1331
1332template<class Impl>
1333ThreadID
1334DefaultFetch<Impl>::iqCount()
1335{
1336    std::priority_queue<ThreadID> PQ;
1337
1338    list<ThreadID>::iterator threads = activeThreads->begin();
1339    list<ThreadID>::iterator end = activeThreads->end();
1340
1341    while (threads != end) {
1342        ThreadID tid = *threads++;
1343
1344        PQ.push(fromIEW->iewInfo[tid].iqCount);
1345    }
1346
1347    while (!PQ.empty()) {
1348        ThreadID high_pri = PQ.top();
1349
1350        if (fetchStatus[high_pri] == Running ||
1351            fetchStatus[high_pri] == IcacheAccessComplete ||
1352            fetchStatus[high_pri] == Idle)
1353            return high_pri;
1354        else
1355            PQ.pop();
1356
1357    }
1358
1359    return InvalidThreadID;
1360}
1361
1362template<class Impl>
1363ThreadID
1364DefaultFetch<Impl>::lsqCount()
1365{
1366    std::priority_queue<ThreadID> PQ;
1367
1368    list<ThreadID>::iterator threads = activeThreads->begin();
1369    list<ThreadID>::iterator end = activeThreads->end();
1370
1371    while (threads != end) {
1372        ThreadID tid = *threads++;
1373
1374        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1375    }
1376
1377    while (!PQ.empty()) {
1378        ThreadID high_pri = PQ.top();
1379
1380        if (fetchStatus[high_pri] == Running ||
1381            fetchStatus[high_pri] == IcacheAccessComplete ||
1382            fetchStatus[high_pri] == Idle)
1383            return high_pri;
1384        else
1385            PQ.pop();
1386    }
1387
1388    return InvalidThreadID;
1389}
1390
1391template<class Impl>
1392ThreadID
1393DefaultFetch<Impl>::branchCount()
1394{
1395#if 0
1396    list<ThreadID>::iterator thread = activeThreads->begin();
1397    assert(thread != activeThreads->end());
1398    ThreadID tid = *thread;
1399#endif
1400
1401    panic("Branch Count Fetch policy unimplemented\n");
1402    return InvalidThreadID;
1403}
1404