fetch_impl.hh revision 5890:bdef71accd68
11689SN/A/* 21689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#include <algorithm> 332325SN/A#include <cstring> 341060SN/A 351060SN/A#include "config/use_checker.hh" 361060SN/A 372292SN/A#include "arch/isa_traits.hh" 382292SN/A#include "arch/utility.hh" 391681SN/A#include "cpu/checker/cpu.hh" 401060SN/A#include "cpu/exetrace.hh" 412980Sgblack@eecs.umich.edu#include "cpu/o3/fetch.hh" 421060SN/A#include "mem/packet.hh" 431060SN/A#include "mem/request.hh" 441858SN/A#include "sim/byteswap.hh" 454598Sbinkertn@umich.edu#include "sim/host.hh" 462325SN/A#include "sim/core.hh" 471717SN/A 482683Sktlim@umich.edu#if FULL_SYSTEM 491717SN/A#include "arch/tlb.hh" 501717SN/A#include "arch/vtophys.hh" 512292SN/A#include "sim/system.hh" 522292SN/A#endif // FULL_SYSTEM 532817Sksewell@umich.edu 541060SN/A#include "params/DerivO3CPU.hh" 551060SN/A 565529Snate@binkert.orgtemplate<class Impl> 575529Snate@binkert.orgvoid 582316SN/ADefaultFetch<Impl>::IcachePort::setPeer(Port *port) 592316SN/A{ 602680Sktlim@umich.edu Port::setPeer(port); 612817Sksewell@umich.edu 622817Sksewell@umich.edu fetch->setIcache(); 632843Sktlim@umich.edu} 642843Sktlim@umich.edu 652669Sktlim@umich.edutemplate<class Impl> 661060SN/ATick 671060SN/ADefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) 685529Snate@binkert.org{ 695529Snate@binkert.org panic("DefaultFetch doesn't expect recvAtomic callback!"); 702733Sktlim@umich.edu return curTick; 711060SN/A} 721060SN/A 731060SN/Atemplate<class Impl> 745529Snate@binkert.orgvoid 752292SN/ADefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt) 762292SN/A{ 771060SN/A DPRINTF(Fetch, "DefaultFetch doesn't update its state from a " 781060SN/A "functional call."); 792348SN/A} 802348SN/A 812348SN/Atemplate<class Impl> 822348SN/Avoid 832348SN/ADefaultFetch<Impl>::IcachePort::recvStatusChange(Status status) 841060SN/A{ 852733Sktlim@umich.edu if (status == RangeChange) { 861060SN/A if (!snoopRangeSent) { 871060SN/A snoopRangeSent = true; 882325SN/A sendStatusChange(Port::RangeChange); 891060SN/A } 901061SN/A return; 914329Sktlim@umich.edu } 921060SN/A 935595Sgblack@eecs.umich.edu panic("DefaultFetch doesn't expect recvStatusChange callback!"); 942292SN/A} 952292SN/A 962292SN/Atemplate<class Impl> 972292SN/Abool 982817Sksewell@umich.eduDefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt) 992829Sksewell@umich.edu{ 1001060SN/A DPRINTF(Fetch, "Received timing\n"); 1011060SN/A if (pkt->isResponse()) { 1021060SN/A fetch->processCacheCompletion(pkt); 1031060SN/A } 1041060SN/A //else Snooped a coherence request, just return 1052307SN/A return true; 1062307SN/A} 1071060SN/A 1081060SN/Atemplate<class Impl> 1093781Sgblack@eecs.umich.eduvoid 1103781Sgblack@eecs.umich.eduDefaultFetch<Impl>::IcachePort::recvRetry() 1113781Sgblack@eecs.umich.edu{ 1122292SN/A fetch->recvRetry(); 1131060SN/A} 1141060SN/A 1152829Sksewell@umich.edutemplate<class Impl> 1162829Sksewell@umich.eduDefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) 1172829Sksewell@umich.edu : cpu(_cpu), 1181060SN/A branchPred(params), 1191060SN/A predecoder(NULL), 1201060SN/A decodeToFetchDelay(params->decodeToFetchDelay), 1211060SN/A renameToFetchDelay(params->renameToFetchDelay), 1222292SN/A iewToFetchDelay(params->iewToFetchDelay), 1231755SN/A commitToFetchDelay(params->commitToFetchDelay), 1241060SN/A fetchWidth(params->fetchWidth), 1251060SN/A cacheBlocked(false), 1262292SN/A retryPkt(NULL), 1271755SN/A retryTid(-1), 1282292SN/A numThreads(params->numThreads), 1292292SN/A numFetchingThreads(params->smtNumFetchingThreads), 1301060SN/A interruptPending(false), 1312292SN/A drainPending(false), 1325336Shines@cs.fsu.edu switchedOut(false) 1331060SN/A{ 1341060SN/A if (numThreads > Impl::MaxThreads) 1352292SN/A fatal("numThreads is not a valid value\n"); 1361060SN/A 1371060SN/A // Set fetch stage's status to inactive. 1382292SN/A _status = Inactive; 1391060SN/A 1401060SN/A std::string policy = params->smtFetchPolicy; 1411060SN/A 1425606Snate@binkert.org // Convert string to lowercase 1431060SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1445606Snate@binkert.org (int(*)(int)) tolower); 1451060SN/A 1461060SN/A // Figure out fetch policy 1472292SN/A if (policy == "singlethread") { 1481060SN/A fetchPolicy = SingleThread; 1491060SN/A if (numThreads > 1) 1501060SN/A panic("Invalid Fetch Policy for a SMT workload."); 1511060SN/A } else if (policy == "roundrobin") { 1521060SN/A fetchPolicy = RoundRobin; 1531060SN/A DPRINTF(Fetch, "Fetch policy set to Round Robin\n"); 1542829Sksewell@umich.edu } else if (policy == "branch") { 1552829Sksewell@umich.edu fetchPolicy = Branch; 1562829Sksewell@umich.edu DPRINTF(Fetch, "Fetch policy set to Branch Count\n"); 1572829Sksewell@umich.edu } else if (policy == "iqcount") { 1582829Sksewell@umich.edu fetchPolicy = IQ; 1592829Sksewell@umich.edu DPRINTF(Fetch, "Fetch policy set to IQ count\n"); 1602829Sksewell@umich.edu } else if (policy == "lsqcount") { 1612829Sksewell@umich.edu fetchPolicy = LSQ; 1622829Sksewell@umich.edu DPRINTF(Fetch, "Fetch policy set to LSQ count\n"); 1632829Sksewell@umich.edu } else { 1642829Sksewell@umich.edu fatal("Invalid Fetch Policy. Options Are: {SingleThread," 1652829Sksewell@umich.edu " RoundRobin,LSQcount,IQcount}\n"); 1662829Sksewell@umich.edu } 1672829Sksewell@umich.edu 1682829Sksewell@umich.edu // Get the size of an instruction. 1692829Sksewell@umich.edu instSize = sizeof(TheISA::MachInst); 1702829Sksewell@umich.edu 1712829Sksewell@umich.edu // Name is finally available, so create the port. 1722829Sksewell@umich.edu icachePort = new IcachePort(this); 1732829Sksewell@umich.edu 1745336Shines@cs.fsu.edu icachePort->snoopRangeSent = false; 1752829Sksewell@umich.edu 1762829Sksewell@umich.edu#if USE_CHECKER 1772829Sksewell@umich.edu if (cpu->checker) { 1782829Sksewell@umich.edu cpu->checker->setIcachePort(icachePort); 1792829Sksewell@umich.edu } 1802829Sksewell@umich.edu#endif 1812829Sksewell@umich.edu} 1825606Snate@binkert.org 1835606Snate@binkert.orgtemplate <class Impl> 1842829Sksewell@umich.edustd::string 1855606Snate@binkert.orgDefaultFetch<Impl>::name() const 1865606Snate@binkert.org{ 1872829Sksewell@umich.edu return cpu->name() + ".fetch"; 1882829Sksewell@umich.edu} 1892829Sksewell@umich.edu 1902829Sksewell@umich.edutemplate <class Impl> 1912829Sksewell@umich.eduvoid 1922829Sksewell@umich.eduDefaultFetch<Impl>::regStats() 1932829Sksewell@umich.edu{ 1942829Sksewell@umich.edu icacheStallCycles 1952829Sksewell@umich.edu .name(name() + ".icacheStallCycles") 1965595Sgblack@eecs.umich.edu .desc("Number of cycles fetch is stalled on an Icache miss") 1975595Sgblack@eecs.umich.edu .prereq(icacheStallCycles); 1985595Sgblack@eecs.umich.edu 1995595Sgblack@eecs.umich.edu fetchedInsts 2005595Sgblack@eecs.umich.edu .name(name() + ".Insts") 2015595Sgblack@eecs.umich.edu .desc("Number of instructions fetch has processed") 2025595Sgblack@eecs.umich.edu .prereq(fetchedInsts); 2032829Sksewell@umich.edu 2042829Sksewell@umich.edu fetchedBranches 2052829Sksewell@umich.edu .name(name() + ".Branches") 2062875Sksewell@umich.edu .desc("Number of branches that fetch encountered") 2072875Sksewell@umich.edu .prereq(fetchedBranches); 2082875Sksewell@umich.edu 2093221Sktlim@umich.edu predictedBranches 2102875Sksewell@umich.edu .name(name() + ".predictedBranches") 2112875Sksewell@umich.edu .desc("Number of branches that fetch has predicted taken") 2123221Sktlim@umich.edu .prereq(predictedBranches); 2133221Sktlim@umich.edu 2143221Sktlim@umich.edu fetchCycles 2152875Sksewell@umich.edu .name(name() + ".Cycles") 2162875Sksewell@umich.edu .desc("Number of cycles fetch has run and was not squashing or" 2172875Sksewell@umich.edu " blocked") 2182875Sksewell@umich.edu .prereq(fetchCycles); 2192875Sksewell@umich.edu 2202875Sksewell@umich.edu fetchSquashCycles 2212875Sksewell@umich.edu .name(name() + ".SquashCycles") 2222875Sksewell@umich.edu .desc("Number of cycles fetch has spent squashing") 2232875Sksewell@umich.edu .prereq(fetchSquashCycles); 2242875Sksewell@umich.edu 2252875Sksewell@umich.edu fetchIdleCycles 2262875Sksewell@umich.edu .name(name() + ".IdleCycles") 2272875Sksewell@umich.edu .desc("Number of cycles fetch was idle") 2283221Sktlim@umich.edu .prereq(fetchIdleCycles); 2293221Sktlim@umich.edu 2303221Sktlim@umich.edu fetchBlockedCycles 2312875Sksewell@umich.edu .name(name() + ".BlockedCycles") 2325336Shines@cs.fsu.edu .desc("Number of cycles fetch has spent blocked") 2332875Sksewell@umich.edu .prereq(fetchBlockedCycles); 2342875Sksewell@umich.edu 2352875Sksewell@umich.edu fetchedCacheLines 2363221Sktlim@umich.edu .name(name() + ".CacheLines") 2372875Sksewell@umich.edu .desc("Number of cache lines fetched") 2382875Sksewell@umich.edu .prereq(fetchedCacheLines); 2392875Sksewell@umich.edu 2405606Snate@binkert.org fetchMiscStallCycles 2415606Snate@binkert.org .name(name() + ".MiscStallCycles") 2422875Sksewell@umich.edu .desc("Number of cycles fetch has spent waiting on interrupts, or " 2435606Snate@binkert.org "bad addresses, or out of MSHRs") 2445606Snate@binkert.org .prereq(fetchMiscStallCycles); 2452875Sksewell@umich.edu 2462875Sksewell@umich.edu fetchIcacheSquashes 2472875Sksewell@umich.edu .name(name() + ".IcacheSquashes") 2482875Sksewell@umich.edu .desc("Number of outstanding Icache misses that were squashed") 2492875Sksewell@umich.edu .prereq(fetchIcacheSquashes); 2502875Sksewell@umich.edu 2512875Sksewell@umich.edu fetchNisnDist 2522875Sksewell@umich.edu .init(/* base value */ 0, 2532875Sksewell@umich.edu /* last value */ fetchWidth, 2542875Sksewell@umich.edu /* bucket size */ 1) 2552875Sksewell@umich.edu .name(name() + ".rateDist") 2562875Sksewell@umich.edu .desc("Number of instructions fetched each cycle (Total)") 2571060SN/A .flags(Stats::pdf); 2582292SN/A 2595595Sgblack@eecs.umich.edu idleRate 2602292SN/A .name(name() + ".idleRate") 2611755SN/A .desc("Percent of cycles fetch was idle") 2621060SN/A .prereq(idleRate); 2632292SN/A idleRate = fetchIdleCycles * 100 / cpu->numCycles; 2645595Sgblack@eecs.umich.edu 2651684SN/A branchRate 2665358Sgblack@eecs.umich.edu .name(name() + ".branchRate") 2675358Sgblack@eecs.umich.edu .desc("Number of branch fetches per cycle") 2685358Sgblack@eecs.umich.edu .flags(Stats::total); 2695358Sgblack@eecs.umich.edu branchRate = fetchedBranches / cpu->numCycles; 2705358Sgblack@eecs.umich.edu 2715358Sgblack@eecs.umich.edu fetchRate 2725358Sgblack@eecs.umich.edu .name(name() + ".rate") 2735358Sgblack@eecs.umich.edu .desc("Number of inst fetches per cycle") 2745358Sgblack@eecs.umich.edu .flags(Stats::total); 2755358Sgblack@eecs.umich.edu fetchRate = fetchedInsts / cpu->numCycles; 2765358Sgblack@eecs.umich.edu 2775358Sgblack@eecs.umich.edu branchPred.regStats(); 2785358Sgblack@eecs.umich.edu} 2795358Sgblack@eecs.umich.edu 2805358Sgblack@eecs.umich.edutemplate<class Impl> 2815358Sgblack@eecs.umich.eduvoid 2824988Sgblack@eecs.umich.eduDefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) 2834988Sgblack@eecs.umich.edu{ 2844988Sgblack@eecs.umich.edu timeBuffer = time_buffer; 2854988Sgblack@eecs.umich.edu 2864988Sgblack@eecs.umich.edu // Create wires to get information from proper places in time buffer. 2874988Sgblack@eecs.umich.edu fromDecode = timeBuffer->getWire(-decodeToFetchDelay); 2884988Sgblack@eecs.umich.edu fromRename = timeBuffer->getWire(-renameToFetchDelay); 2894988Sgblack@eecs.umich.edu fromIEW = timeBuffer->getWire(-iewToFetchDelay); 2904988Sgblack@eecs.umich.edu fromCommit = timeBuffer->getWire(-commitToFetchDelay); 2914988Sgblack@eecs.umich.edu} 2924988Sgblack@eecs.umich.edu 2934988Sgblack@eecs.umich.edutemplate<class Impl> 2944988Sgblack@eecs.umich.eduvoid 2954988Sgblack@eecs.umich.eduDefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2964988Sgblack@eecs.umich.edu{ 2974988Sgblack@eecs.umich.edu activeThreads = at_ptr; 2984988Sgblack@eecs.umich.edu} 2994988Sgblack@eecs.umich.edu 3002871Sktlim@umich.edutemplate<class Impl> 3012871Sktlim@umich.eduvoid 3022871Sktlim@umich.eduDefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 3032292SN/A{ 3042292SN/A fetchQueue = fq_ptr; 3052292SN/A 3061684SN/A // Create wire to write information to proper place in fetch queue. 3071684SN/A toDecode = fetchQueue->getWire(0); 3082292SN/A} 3091060SN/A 3101060SN/Atemplate<class Impl> 3112834Sksewell@umich.eduvoid 3122834Sksewell@umich.eduDefaultFetch<Impl>::initStage() 3132834Sksewell@umich.edu{ 3142834Sksewell@umich.edu // Setup PC and nextPC with initial state. 3152829Sksewell@umich.edu for (int tid = 0; tid < numThreads; tid++) { 3162875Sksewell@umich.edu PC[tid] = cpu->readPC(tid); 3172875Sksewell@umich.edu nextPC[tid] = cpu->readNextPC(tid); 3182875Sksewell@umich.edu microPC[tid] = cpu->readMicroPC(tid); 3192875Sksewell@umich.edu } 3202829Sksewell@umich.edu 3212292SN/A for (int tid=0; tid < numThreads; tid++) { 3222292SN/A 3231060SN/A fetchStatus[tid] = Running; 3242292SN/A 3252292SN/A priorityList.push_back(tid); 3262292SN/A 3272292SN/A memReq[tid] = NULL; 3282292SN/A 3292292SN/A stalls[tid].decode = false; 3302292SN/A stalls[tid].rename = false; 3312292SN/A stalls[tid].iew = false; 3322292SN/A stalls[tid].commit = false; 3332292SN/A } 3342292SN/A 3352292SN/A // Schedule fetch to get the correct PC from the CPU 3362292SN/A // scheduleFetchStartupEvent(1); 3372292SN/A 3382292SN/A // Fetch needs to start fetching instructions at the very beginning, 3392292SN/A // so it must start up in active state. 3402292SN/A switchToActive(); 3412292SN/A} 3422292SN/A 3432292SN/Atemplate<class Impl> 3442292SN/Avoid 3453221Sktlim@umich.eduDefaultFetch<Impl>::setIcache() 3462292SN/A{ 3473221Sktlim@umich.edu // Size of cache block. 3482292SN/A cacheBlkSize = icachePort->peerBlockSize(); 3492292SN/A 3502292SN/A // Create mask to get rid of offset bits. 3512292SN/A cacheBlkMask = (cacheBlkSize - 1); 3522292SN/A 3532292SN/A for (int tid=0; tid < numThreads; tid++) { 3542292SN/A // Create space to store a cache line. 3552292SN/A cacheData[tid] = new uint8_t[cacheBlkSize]; 3562292SN/A cacheDataPC[tid] = 0; 3572292SN/A cacheDataValid[tid] = false; 3582292SN/A } 3592292SN/A} 3602292SN/A 3612292SN/Atemplate<class Impl> 3622292SN/Avoid 3632864Sktlim@umich.eduDefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) 3642864Sktlim@umich.edu{ 3652864Sktlim@umich.edu unsigned tid = pkt->req->threadId(); 3662864Sktlim@umich.edu 3672864Sktlim@umich.edu DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); 3682864Sktlim@umich.edu 3692864Sktlim@umich.edu assert(!pkt->wasNacked()); 3705595Sgblack@eecs.umich.edu 3715595Sgblack@eecs.umich.edu // Only change the status if it's still waiting on the icache access 3725595Sgblack@eecs.umich.edu // to return. 3732292SN/A if (fetchStatus[tid] != IcacheWaitResponse || 3745595Sgblack@eecs.umich.edu pkt->req != memReq[tid] || 3755595Sgblack@eecs.umich.edu isSwitchedOut()) { 3765595Sgblack@eecs.umich.edu ++fetchIcacheSquashes; 3775595Sgblack@eecs.umich.edu delete pkt->req; 3785595Sgblack@eecs.umich.edu delete pkt; 3795595Sgblack@eecs.umich.edu return; 3802292SN/A } 3812843Sktlim@umich.edu 3822843Sktlim@umich.edu memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); 3832905Sktlim@umich.edu cacheDataValid[tid] = true; 3842843Sktlim@umich.edu 3852843Sktlim@umich.edu if (!drainPending) { 3862843Sktlim@umich.edu // Wake up the CPU (if it went to sleep and was waiting on 3872292SN/A // this completion event). 3882348SN/A cpu->wakeCPU(); 3892843Sktlim@umich.edu 3902843Sktlim@umich.edu DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", 3912843Sktlim@umich.edu tid); 3922843Sktlim@umich.edu 3932316SN/A switchToActive(); 3942348SN/A } 3952843Sktlim@umich.edu 3961060SN/A // Only switch to IcacheAccessComplete if we're not stalled as well. 3971060SN/A if (checkStall(tid)) { 3982316SN/A fetchStatus[tid] = Blocked; 3992316SN/A } else { 4001060SN/A fetchStatus[tid] = IcacheAccessComplete; 4015595Sgblack@eecs.umich.edu } 4025595Sgblack@eecs.umich.edu 4035595Sgblack@eecs.umich.edu // Reset the mem req to NULL. 4041858SN/A delete pkt->req; 4055595Sgblack@eecs.umich.edu delete pkt; 4065704Snate@binkert.org memReq[tid] = NULL; 4075595Sgblack@eecs.umich.edu} 4085702Ssaidi@eecs.umich.edu 4095702Ssaidi@eecs.umich.edutemplate <class Impl> 4105702Ssaidi@eecs.umich.edubool 4115702Ssaidi@eecs.umich.eduDefaultFetch<Impl>::drain() 4125702Ssaidi@eecs.umich.edu{ 4135595Sgblack@eecs.umich.edu // Fetch is ready to drain at any time. 4145595Sgblack@eecs.umich.edu cpu->signalDrained(); 4155595Sgblack@eecs.umich.edu drainPending = true; 4165595Sgblack@eecs.umich.edu return true; 4175595Sgblack@eecs.umich.edu} 4185595Sgblack@eecs.umich.edu 4195595Sgblack@eecs.umich.edutemplate <class Impl> 4205595Sgblack@eecs.umich.eduvoid 4215595Sgblack@eecs.umich.eduDefaultFetch<Impl>::resume() 4224192Sktlim@umich.edu{ 4234192Sktlim@umich.edu drainPending = false; 4244192Sktlim@umich.edu} 4254192Sktlim@umich.edu 4261060SN/Atemplate <class Impl> 4271060SN/Avoid 4281060SN/ADefaultFetch<Impl>::switchOut() 4291060SN/A{ 4301060SN/A switchedOut = true; 4311060SN/A // Branch predictor needs to have its state cleared. 4321060SN/A branchPred.switchOut(); 4332292SN/A} 4342292SN/A 4351060SN/Atemplate <class Impl> 4361060SN/Avoid 4372292SN/ADefaultFetch<Impl>::takeOverFrom() 4382292SN/A{ 4391060SN/A // Reset all state 4402292SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 4412292SN/A stalls[i].decode = 0; 4422683Sktlim@umich.edu stalls[i].rename = 0; 4431060SN/A stalls[i].iew = 0; 4442292SN/A stalls[i].commit = 0; 4452292SN/A PC[i] = cpu->readPC(i); 4462683Sktlim@umich.edu nextPC[i] = cpu->readNextPC(i); 4471060SN/A microPC[i] = cpu->readMicroPC(i); 4481060SN/A fetchStatus[i] = Running; 4491060SN/A } 4502348SN/A numInst = 0; 4515595Sgblack@eecs.umich.edu wroteToTimeBuffer = false; 4525595Sgblack@eecs.umich.edu _status = Inactive; 4535595Sgblack@eecs.umich.edu switchedOut = false; 4545595Sgblack@eecs.umich.edu interruptPending = false; 4555595Sgblack@eecs.umich.edu branchPred.takeOverFrom(); 4565595Sgblack@eecs.umich.edu} 4575595Sgblack@eecs.umich.edu 4585595Sgblack@eecs.umich.edutemplate <class Impl> 4595595Sgblack@eecs.umich.eduvoid 4605595Sgblack@eecs.umich.eduDefaultFetch<Impl>::wakeFromQuiesce() 4615595Sgblack@eecs.umich.edu{ 4625595Sgblack@eecs.umich.edu DPRINTF(Fetch, "Waking up from quiesce\n"); 4635595Sgblack@eecs.umich.edu // Hopefully this is safe 4645595Sgblack@eecs.umich.edu // @todo: Allow other threads to wake from quiesce. 4655595Sgblack@eecs.umich.edu fetchStatus[0] = Running; 4665595Sgblack@eecs.umich.edu} 4675595Sgblack@eecs.umich.edu 4685595Sgblack@eecs.umich.edutemplate <class Impl> 4691060SN/Ainline void 4701060SN/ADefaultFetch<Impl>::switchToActive() 4713781Sgblack@eecs.umich.edu{ 4721060SN/A if (_status == Inactive) { 4733781Sgblack@eecs.umich.edu DPRINTF(Activity, "Activating stage.\n"); 4741060SN/A 4753781Sgblack@eecs.umich.edu cpu->activateStage(O3CPU::FetchIdx); 4762455SN/A 4773781Sgblack@eecs.umich.edu _status = Active; 4781060SN/A } 4791060SN/A} 4801060SN/A 4813781Sgblack@eecs.umich.edutemplate <class Impl> 4821060SN/Ainline void 4833781Sgblack@eecs.umich.eduDefaultFetch<Impl>::switchToInactive() 4841060SN/A{ 4853781Sgblack@eecs.umich.edu if (_status == Active) { 4862455SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4873781Sgblack@eecs.umich.edu 4881060SN/A cpu->deactivateStage(O3CPU::FetchIdx); 4892292SN/A 4901060SN/A _status = Inactive; 4912292SN/A } 4921060SN/A} 4932292SN/A 4942292SN/Atemplate <class Impl> 4952292SN/Abool 4962292SN/ADefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, 4972348SN/A Addr &next_NPC, Addr &next_MicroPC) 4982348SN/A{ 4992348SN/A // Do branch prediction check here. 5002348SN/A // A bit of a misnomer...next_PC is actually the current PC until 5012348SN/A // this function updates it. 5022292SN/A bool predict_taken; 5032292SN/A 5042292SN/A if (!inst->isControl()) { 5052292SN/A if (inst->isMicroop() && !inst->isLastMicroop()) { 5062292SN/A next_MicroPC++; 5072292SN/A } else { 5082292SN/A next_PC = next_NPC; 5092292SN/A next_NPC = next_NPC + instSize; 5102348SN/A next_MicroPC = 0; 5114636Sgblack@eecs.umich.edu } 5122292SN/A inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 5132348SN/A inst->setPredTaken(false); 5142348SN/A return false; 5152292SN/A } 5164636Sgblack@eecs.umich.edu 5174636Sgblack@eecs.umich.edu //Assume for now that all control flow is to a different macroop which 5184636Sgblack@eecs.umich.edu //would reset the micro pc to 0. 5194636Sgblack@eecs.umich.edu next_MicroPC = 0; 5204636Sgblack@eecs.umich.edu 5214636Sgblack@eecs.umich.edu int tid = inst->threadNumber; 5222348SN/A Addr pred_PC = next_PC; 5234636Sgblack@eecs.umich.edu predict_taken = branchPred.predict(inst, pred_PC, tid); 5242292SN/A 5252348SN/A/* if (predict_taken) { 5264636Sgblack@eecs.umich.edu DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", 5271060SN/A tid, pred_PC); 5282756Sksewell@umich.edu } else { 5294636Sgblack@eecs.umich.edu DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); 5302756Sksewell@umich.edu }*/ 5312756Sksewell@umich.edu 5324636Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 5334636Sgblack@eecs.umich.edu next_PC = next_NPC; 5344636Sgblack@eecs.umich.edu if (predict_taken) 5354636Sgblack@eecs.umich.edu next_NPC = pred_PC; 5364636Sgblack@eecs.umich.edu else 5374636Sgblack@eecs.umich.edu next_NPC += instSize; 5384636Sgblack@eecs.umich.edu#else 5392756Sksewell@umich.edu if (predict_taken) 5405595Sgblack@eecs.umich.edu next_PC = pred_PC; 5415595Sgblack@eecs.umich.edu else 5425595Sgblack@eecs.umich.edu next_PC += instSize; 5435595Sgblack@eecs.umich.edu next_NPC = next_PC + instSize; 5445595Sgblack@eecs.umich.edu#endif 5455595Sgblack@eecs.umich.edu/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", 5461060SN/A tid, next_PC, next_NPC);*/ 5471060SN/A inst->setPredTarg(next_PC, next_NPC, next_MicroPC); 5481060SN/A inst->setPredTaken(predict_taken); 5492292SN/A 5501060SN/A ++fetchedBranches; 5511060SN/A 5522292SN/A if (predict_taken) { 5531060SN/A ++predictedBranches; 5542292SN/A } 5552292SN/A 5561060SN/A return predict_taken; 5572325SN/A} 5582325SN/A 5591060SN/Atemplate <class Impl> 5601061SN/Abool 5611060SN/ADefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid) 5622935Sksewell@umich.edu{ 5632935Sksewell@umich.edu Fault fault = NoFault; 5644632Sgblack@eecs.umich.edu 5651060SN/A //AlphaDep 5661062SN/A if (cacheBlocked) { 5672292SN/A DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", 5682292SN/A tid); 5692348SN/A return false; 5702292SN/A } else if (isSwitchedOut()) { 5712292SN/A DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", 5722348SN/A tid); 5732292SN/A return false; 5741062SN/A } else if (interruptPending && !(fetch_PC & 0x3)) { 5752348SN/A // Hold off fetch from getting new instructions when: 5761060SN/A // Cache is blocked, or 5771060SN/A // while an interrupt is pending and we're not in PAL mode, or 5781060SN/A // fetch is switched out. 5795737Scws3k@cs.virginia.edu DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", 5805737Scws3k@cs.virginia.edu tid); 5815737Scws3k@cs.virginia.edu return false; 5825737Scws3k@cs.virginia.edu } 5835737Scws3k@cs.virginia.edu 5841060SN/A // Align the fetch PC so it's at the start of a cache block. 5852292SN/A Addr block_PC = icacheBlockAlignPC(fetch_PC); 5861060SN/A 5872292SN/A // If we've already got the block, no need to try to fetch it again. 5882292SN/A if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { 5892292SN/A return true; 5902292SN/A } 5912292SN/A 5922325SN/A // Setup the memReq to do a read of the first instruction's address. 5932348SN/A // Set the appropriate read size and flags as well. 5942348SN/A // Build request here. 5952348SN/A RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, 5962292SN/A fetch_PC, cpu->thread[tid]->contextId(), 5972325SN/A tid); 5982292SN/A 5992325SN/A memReq[tid] = mem_req; 6002325SN/A 6012292SN/A // Translate the instruction request. 6022292SN/A fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC()); 6032292SN/A 6041060SN/A // In the case of faults, the fetch stage may need to stall and wait 6051060SN/A // for the ITB miss to be handled. 6061060SN/A 6071060SN/A // If translation was successful, attempt to read the first 6081060SN/A // instruction. 6091060SN/A if (fault == NoFault) { 6101060SN/A#if 0 6111060SN/A if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) || 6121060SN/A memReq[tid]->isUncacheable()) { 6131060SN/A DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a " 6141060SN/A "misspeculating path)!", 6151060SN/A memReq[tid]->paddr); 6161060SN/A ret_fault = TheISA::genMachineCheckFault(); 6171060SN/A return false; 6181060SN/A } 6191060SN/A#endif 6201060SN/A 6211060SN/A // Build packet here. 6221060SN/A PacketPtr data_pkt = new Packet(mem_req, 6231060SN/A MemCmd::ReadReq, Packet::Broadcast); 6241060SN/A data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); 6251060SN/A 6261060SN/A cacheDataPC[tid] = block_PC; 6272292SN/A cacheDataValid[tid] = false; 6282292SN/A 6292292SN/A DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); 6302292SN/A 6311060SN/A fetchedCacheLines++; 6321060SN/A 6331060SN/A // Now do the timing access to see whether or not the instruction 6341060SN/A // exists within the cache. 6352292SN/A if (!icachePort->sendTiming(data_pkt)) { 6362292SN/A assert(retryPkt == NULL); 6372292SN/A assert(retryTid == -1); 6382292SN/A DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid); 6392292SN/A fetchStatus[tid] = IcacheWaitRetry; 6402292SN/A retryPkt = data_pkt; 6411060SN/A retryTid = tid; 6422292SN/A cacheBlocked = true; 6432292SN/A return false; 6442292SN/A } 6452292SN/A 6462292SN/A DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid); 6472292SN/A 6482292SN/A lastIcacheStall[tid] = curTick; 6492292SN/A 6502292SN/A DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache " 6512292SN/A "response.\n", tid); 6522292SN/A 6532292SN/A fetchStatus[tid] = IcacheWaitResponse; 6541060SN/A } else { 6551060SN/A delete mem_req; 6561060SN/A memReq[tid] = NULL; 6571061SN/A } 6581060SN/A 6591061SN/A ret_fault = fault; 6601060SN/A return true; 6611061SN/A} 6621060SN/A 6631061SN/Atemplate <class Impl> 6641060SN/Ainline void 6651061SN/ADefaultFetch<Impl>::doSquash(const Addr &new_PC, 6661060SN/A const Addr &new_NPC, const Addr &new_microPC, unsigned tid) 6671060SN/A{ 6681060SN/A DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n", 6691060SN/A tid, new_PC, new_NPC); 6701060SN/A 6711060SN/A PC[tid] = new_PC; 6721060SN/A nextPC[tid] = new_NPC; 6731060SN/A microPC[tid] = new_microPC; 6741060SN/A 6751060SN/A // Clear the icache miss if it's outstanding. 6761060SN/A if (fetchStatus[tid] == IcacheWaitResponse) { 6771060SN/A DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n", 6781060SN/A tid); 6791060SN/A memReq[tid] = NULL; 6801060SN/A } 6811060SN/A 6822348SN/A // Get rid of the retrying packet if it was from this thread. 6832348SN/A if (retryTid == tid) { 6842348SN/A assert(cacheBlocked); 6852348SN/A if (retryPkt) { 6862348SN/A delete retryPkt->req; 6872325SN/A delete retryPkt; 6881060SN/A } 6892348SN/A retryPkt = NULL; 6902348SN/A retryTid = -1; 6912325SN/A } 6922292SN/A 6932348SN/A fetchStatus[tid] = Squashing; 6942325SN/A 6952325SN/A ++fetchSquashCycles; 6962292SN/A} 6972348SN/A 6982325SN/Atemplate<class Impl> 6992325SN/Avoid 7002292SN/ADefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 7012292SN/A const Addr &new_MicroPC, 7022292SN/A const InstSeqNum &seq_num, unsigned tid) 7032260SN/A{ 7042292SN/A DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid); 7052292SN/A 7062292SN/A doSquash(new_PC, new_NPC, new_MicroPC, tid); 7072292SN/A 7082680Sktlim@umich.edu // Tell the CPU to remove any instructions that are in flight between 7092680Sktlim@umich.edu // fetch and decode. 7101681SN/A cpu->removeInstsUntil(seq_num, tid); 7112680Sktlim@umich.edu} 7122190SN/A 7132190SN/Atemplate<class Impl> 7142292SN/Abool 7153093Sksewell@umich.eduDefaultFetch<Impl>::checkStall(unsigned tid) const 7161060SN/A{ 7174598Sbinkertn@umich.edu bool ret_val = false; 7182348SN/A 7192348SN/A if (cpu->contextSwitch) { 7202348SN/A DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); 7212348SN/A ret_val = true; 7222316SN/A } else if (stalls[tid].decode) { 7234598Sbinkertn@umich.edu DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid); 7242316SN/A ret_val = true; 7251858SN/A } else if (stalls[tid].rename) { 7262292SN/A DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid); 7271060SN/A ret_val = true; 7281060SN/A } else if (stalls[tid].iew) { 7292292SN/A DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid); 7301060SN/A ret_val = true; 7312292SN/A } else if (stalls[tid].commit) { 7321060SN/A DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7332843Sktlim@umich.edu ret_val = true; 7342843Sktlim@umich.edu } 7352843Sktlim@umich.edu 7362843Sktlim@umich.edu return ret_val; 7372843Sktlim@umich.edu} 7382316SN/A 7392348SN/Atemplate<class Impl> 7402292SN/Atypename DefaultFetch<Impl>::FetchStatus 7412260SN/ADefaultFetch<Impl>::updateFetchStatus() 7422292SN/A{ 7431060SN/A //Check Running 7441060SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 7452292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 7462292SN/A 7471060SN/A while (threads != end) { 7482292SN/A unsigned tid = *threads++; 7492292SN/A 7502292SN/A if (fetchStatus[tid] == Running || 7512292SN/A fetchStatus[tid] == Squashing || 7522292SN/A fetchStatus[tid] == IcacheAccessComplete) { 7532292SN/A 7542829Sksewell@umich.edu if (_status == Inactive) { 7552829Sksewell@umich.edu DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid); 7562829Sksewell@umich.edu 7572292SN/A if (fetchStatus[tid] == IcacheAccessComplete) { 7582292SN/A DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache" 7592292SN/A "completion\n",tid); 7602292SN/A } 7612292SN/A 7622292SN/A cpu->activateStage(O3CPU::FetchIdx); 7632292SN/A } 7642292SN/A 7652292SN/A return Active; 7665595Sgblack@eecs.umich.edu } 7675595Sgblack@eecs.umich.edu } 7685595Sgblack@eecs.umich.edu 7695595Sgblack@eecs.umich.edu // Stage is switching from active to inactive, notify CPU of it. 7705595Sgblack@eecs.umich.edu if (_status == Active) { 7715595Sgblack@eecs.umich.edu DPRINTF(Activity, "Deactivating stage.\n"); 7725595Sgblack@eecs.umich.edu 7735595Sgblack@eecs.umich.edu cpu->deactivateStage(O3CPU::FetchIdx); 7745595Sgblack@eecs.umich.edu } 7755595Sgblack@eecs.umich.edu 7765595Sgblack@eecs.umich.edu return Inactive; 7775595Sgblack@eecs.umich.edu} 7785595Sgblack@eecs.umich.edu 7795595Sgblack@eecs.umich.edutemplate <class Impl> 7805595Sgblack@eecs.umich.eduvoid 7815595Sgblack@eecs.umich.eduDefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC, 7825595Sgblack@eecs.umich.edu const Addr &new_MicroPC, 7835595Sgblack@eecs.umich.edu const InstSeqNum &seq_num, unsigned tid) 7845595Sgblack@eecs.umich.edu{ 7852292SN/A DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid); 7862292SN/A 7872292SN/A doSquash(new_PC, new_NPC, new_MicroPC, tid); 7882292SN/A 7892292SN/A // Tell the CPU to remove any instructions that are not in the ROB. 7902292SN/A cpu->removeInstsNotInROB(tid); 7912292SN/A} 7922292SN/A 7932292SN/Atemplate <class Impl> 7942292SN/Avoid 7952292SN/ADefaultFetch<Impl>::tick() 7962292SN/A{ 7972292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 7982292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 7992292SN/A bool status_change = false; 8002292SN/A 8011060SN/A wroteToTimeBuffer = false; 8021060SN/A 8032325SN/A while (threads != end) { 804 unsigned tid = *threads++; 805 806 // Check the signals for each thread to determine the proper status 807 // for each thread. 808 bool updated_status = checkSignalsAndUpdate(tid); 809 status_change = status_change || updated_status; 810 } 811 812 DPRINTF(Fetch, "Running stage.\n"); 813 814 // Reset the number of the instruction we're fetching. 815 numInst = 0; 816 817#if FULL_SYSTEM 818 if (fromCommit->commitInfo[0].interruptPending) { 819 interruptPending = true; 820 } 821 822 if (fromCommit->commitInfo[0].clearInterrupt) { 823 interruptPending = false; 824 } 825#endif 826 827 for (threadFetched = 0; threadFetched < numFetchingThreads; 828 threadFetched++) { 829 // Fetch each of the actively fetching threads. 830 fetch(status_change); 831 } 832 833 // Record number of instructions fetched this cycle for distribution. 834 fetchNisnDist.sample(numInst); 835 836 if (status_change) { 837 // Change the fetch stage status if there was a status change. 838 _status = updateFetchStatus(); 839 } 840 841 // If there was activity this cycle, inform the CPU of it. 842 if (wroteToTimeBuffer || cpu->contextSwitch) { 843 DPRINTF(Activity, "Activity this cycle.\n"); 844 845 cpu->activityThisCycle(); 846 } 847} 848 849template <class Impl> 850bool 851DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) 852{ 853 // Update the per thread stall statuses. 854 if (fromDecode->decodeBlock[tid]) { 855 stalls[tid].decode = true; 856 } 857 858 if (fromDecode->decodeUnblock[tid]) { 859 assert(stalls[tid].decode); 860 assert(!fromDecode->decodeBlock[tid]); 861 stalls[tid].decode = false; 862 } 863 864 if (fromRename->renameBlock[tid]) { 865 stalls[tid].rename = true; 866 } 867 868 if (fromRename->renameUnblock[tid]) { 869 assert(stalls[tid].rename); 870 assert(!fromRename->renameBlock[tid]); 871 stalls[tid].rename = false; 872 } 873 874 if (fromIEW->iewBlock[tid]) { 875 stalls[tid].iew = true; 876 } 877 878 if (fromIEW->iewUnblock[tid]) { 879 assert(stalls[tid].iew); 880 assert(!fromIEW->iewBlock[tid]); 881 stalls[tid].iew = false; 882 } 883 884 if (fromCommit->commitBlock[tid]) { 885 stalls[tid].commit = true; 886 } 887 888 if (fromCommit->commitUnblock[tid]) { 889 assert(stalls[tid].commit); 890 assert(!fromCommit->commitBlock[tid]); 891 stalls[tid].commit = false; 892 } 893 894 // Check squash signals from commit. 895 if (fromCommit->commitInfo[tid].squash) { 896 897 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 898 "from commit.\n",tid); 899 // In any case, squash. 900 squash(fromCommit->commitInfo[tid].nextPC, 901 fromCommit->commitInfo[tid].nextNPC, 902 fromCommit->commitInfo[tid].nextMicroPC, 903 fromCommit->commitInfo[tid].doneSeqNum, 904 tid); 905 906 // Also check if there's a mispredict that happened. 907 if (fromCommit->commitInfo[tid].branchMispredict) { 908 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 909 fromCommit->commitInfo[tid].nextPC, 910 fromCommit->commitInfo[tid].branchTaken, 911 tid); 912 } else { 913 branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum, 914 tid); 915 } 916 917 return true; 918 } else if (fromCommit->commitInfo[tid].doneSeqNum) { 919 // Update the branch predictor if it wasn't a squashed instruction 920 // that was broadcasted. 921 branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid); 922 } 923 924 // Check ROB squash signals from commit. 925 if (fromCommit->commitInfo[tid].robSquashing) { 926 DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid); 927 928 // Continue to squash. 929 fetchStatus[tid] = Squashing; 930 931 return true; 932 } 933 934 // Check squash signals from decode. 935 if (fromDecode->decodeInfo[tid].squash) { 936 DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " 937 "from decode.\n",tid); 938 939 // Update the branch predictor. 940 if (fromDecode->decodeInfo[tid].branchMispredict) { 941 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 942 fromDecode->decodeInfo[tid].nextPC, 943 fromDecode->decodeInfo[tid].branchTaken, 944 tid); 945 } else { 946 branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum, 947 tid); 948 } 949 950 if (fetchStatus[tid] != Squashing) { 951 952 DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n", 953 fromDecode->decodeInfo[tid].nextPC, 954 fromDecode->decodeInfo[tid].nextNPC); 955 // Squash unless we're already squashing 956 squashFromDecode(fromDecode->decodeInfo[tid].nextPC, 957 fromDecode->decodeInfo[tid].nextNPC, 958 fromDecode->decodeInfo[tid].nextMicroPC, 959 fromDecode->decodeInfo[tid].doneSeqNum, 960 tid); 961 962 return true; 963 } 964 } 965 966 if (checkStall(tid) && 967 fetchStatus[tid] != IcacheWaitResponse && 968 fetchStatus[tid] != IcacheWaitRetry) { 969 DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); 970 971 fetchStatus[tid] = Blocked; 972 973 return true; 974 } 975 976 if (fetchStatus[tid] == Blocked || 977 fetchStatus[tid] == Squashing) { 978 // Switch status to running if fetch isn't being told to block or 979 // squash this cycle. 980 DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n", 981 tid); 982 983 fetchStatus[tid] = Running; 984 985 return true; 986 } 987 988 // If we've reached this point, we have not gotten any signals that 989 // cause fetch to change its status. Fetch remains the same as before. 990 return false; 991} 992 993template<class Impl> 994void 995DefaultFetch<Impl>::fetch(bool &status_change) 996{ 997 ////////////////////////////////////////// 998 // Start actual fetch 999 ////////////////////////////////////////// 1000 int tid = getFetchingThread(fetchPolicy); 1001 1002 if (tid == -1 || drainPending) { 1003 DPRINTF(Fetch,"There are no more threads available to fetch from.\n"); 1004 1005 // Breaks looping condition in tick() 1006 threadFetched = numFetchingThreads; 1007 return; 1008 } 1009 1010 DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid); 1011 1012 // The current PC. 1013 Addr fetch_PC = PC[tid]; 1014 Addr fetch_NPC = nextPC[tid]; 1015 Addr fetch_MicroPC = microPC[tid]; 1016 1017 // Fault code for memory access. 1018 Fault fault = NoFault; 1019 1020 // If returning from the delay of a cache miss, then update the status 1021 // to running, otherwise do the cache access. Possibly move this up 1022 // to tick() function. 1023 if (fetchStatus[tid] == IcacheAccessComplete) { 1024 DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", 1025 tid); 1026 1027 fetchStatus[tid] = Running; 1028 status_change = true; 1029 } else if (fetchStatus[tid] == Running) { 1030 DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " 1031 "instruction, starting at PC %08p.\n", 1032 tid, fetch_PC); 1033 1034 bool fetch_success = fetchCacheLine(fetch_PC, fault, tid); 1035 if (!fetch_success) { 1036 if (cacheBlocked) { 1037 ++icacheStallCycles; 1038 } else { 1039 ++fetchMiscStallCycles; 1040 } 1041 return; 1042 } 1043 } else { 1044 if (fetchStatus[tid] == Idle) { 1045 ++fetchIdleCycles; 1046 DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); 1047 } else if (fetchStatus[tid] == Blocked) { 1048 ++fetchBlockedCycles; 1049 DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); 1050 } else if (fetchStatus[tid] == Squashing) { 1051 ++fetchSquashCycles; 1052 DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); 1053 } else if (fetchStatus[tid] == IcacheWaitResponse) { 1054 ++icacheStallCycles; 1055 DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); 1056 } 1057 1058 // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so 1059 // fetch should do nothing. 1060 return; 1061 } 1062 1063 ++fetchCycles; 1064 1065 // If we had a stall due to an icache miss, then return. 1066 if (fetchStatus[tid] == IcacheWaitResponse) { 1067 ++icacheStallCycles; 1068 status_change = true; 1069 return; 1070 } 1071 1072 Addr next_PC = fetch_PC; 1073 Addr next_NPC = fetch_NPC; 1074 Addr next_MicroPC = fetch_MicroPC; 1075 1076 InstSeqNum inst_seq; 1077 MachInst inst; 1078 ExtMachInst ext_inst; 1079 // @todo: Fix this hack. 1080 unsigned offset = (fetch_PC & cacheBlkMask) & ~3; 1081 1082 StaticInstPtr staticInst = NULL; 1083 StaticInstPtr macroop = NULL; 1084 1085 if (fault == NoFault) { 1086 // If the read of the first instruction was successful, then grab the 1087 // instructions from the rest of the cache line and put them into the 1088 // queue heading to decode. 1089 1090 DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to " 1091 "decode.\n",tid); 1092 1093 // Need to keep track of whether or not a predicted branch 1094 // ended this fetch block. 1095 bool predicted_branch = false; 1096 1097 while (offset < cacheBlkSize && 1098 numInst < fetchWidth && 1099 !predicted_branch) { 1100 1101 // If we're branching after this instruction, quite fetching 1102 // from the same block then. 1103 predicted_branch = 1104 (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC); 1105 if (predicted_branch) { 1106 DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n", 1107 fetch_PC, fetch_NPC); 1108 } 1109 1110 // Make sure this is a valid index. 1111 assert(offset <= cacheBlkSize - instSize); 1112 1113 if (!macroop) { 1114 // Get the instruction from the array of the cache line. 1115 inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> 1116 (&cacheData[tid][offset])); 1117 1118 predecoder.setTC(cpu->thread[tid]->getTC()); 1119 predecoder.moreBytes(fetch_PC, fetch_PC, inst); 1120 1121 ext_inst = predecoder.getExtMachInst(); 1122 staticInst = StaticInstPtr(ext_inst, fetch_PC); 1123 if (staticInst->isMacroop()) 1124 macroop = staticInst; 1125 } 1126 do { 1127 if (macroop) { 1128 staticInst = macroop->fetchMicroop(fetch_MicroPC); 1129 if (staticInst->isLastMicroop()) 1130 macroop = NULL; 1131 } 1132 1133 // Get a sequence number. 1134 inst_seq = cpu->getAndIncrementInstSeq(); 1135 1136 // Create a new DynInst from the instruction fetched. 1137 DynInstPtr instruction = new DynInst(staticInst, 1138 fetch_PC, fetch_NPC, fetch_MicroPC, 1139 next_PC, next_NPC, next_MicroPC, 1140 inst_seq, cpu); 1141 instruction->setTid(tid); 1142 1143 instruction->setASID(tid); 1144 1145 instruction->setThreadState(cpu->thread[tid]); 1146 1147 DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " 1148 "[sn:%lli]\n", 1149 tid, instruction->readPC(), inst_seq); 1150 1151 //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); 1152 1153 DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", 1154 tid, instruction->staticInst->disassemble(fetch_PC)); 1155 1156#if TRACING_ON 1157 instruction->traceData = 1158 cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid), 1159 instruction->staticInst, instruction->readPC()); 1160#else 1161 instruction->traceData = NULL; 1162#endif 1163 1164 ///FIXME This needs to be more robust in dealing with delay slots 1165 predicted_branch |= 1166 lookupAndUpdateNextPC(instruction, next_PC, next_NPC, next_MicroPC); 1167 1168 // Add instruction to the CPU's list of instructions. 1169 instruction->setInstListIt(cpu->addInst(instruction)); 1170 1171 // Write the instruction to the first slot in the queue 1172 // that heads to decode. 1173 toDecode->insts[numInst] = instruction; 1174 1175 toDecode->size++; 1176 1177 // Increment stat of fetched instructions. 1178 ++fetchedInsts; 1179 1180 // Move to the next instruction, unless we have a branch. 1181 fetch_PC = next_PC; 1182 fetch_NPC = next_NPC; 1183 fetch_MicroPC = next_MicroPC; 1184 1185 if (instruction->isQuiesce()) { 1186 DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!", 1187 curTick); 1188 fetchStatus[tid] = QuiescePending; 1189 ++numInst; 1190 status_change = true; 1191 break; 1192 } 1193 1194 ++numInst; 1195 } while (staticInst->isMicroop() && 1196 !staticInst->isLastMicroop() && 1197 numInst < fetchWidth); 1198 offset += instSize; 1199 } 1200 1201 if (predicted_branch) { 1202 DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch " 1203 "instruction encountered.\n", tid); 1204 } else if (numInst >= fetchWidth) { 1205 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth " 1206 "for this cycle.\n", tid); 1207 } else if (offset >= cacheBlkSize) { 1208 DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache " 1209 "block.\n", tid); 1210 } 1211 } 1212 1213 if (numInst > 0) { 1214 wroteToTimeBuffer = true; 1215 } 1216 1217 // Now that fetching is completed, update the PC to signify what the next 1218 // cycle will be. 1219 if (fault == NoFault) { 1220 PC[tid] = next_PC; 1221 nextPC[tid] = next_NPC; 1222 microPC[tid] = next_MicroPC; 1223 DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC); 1224 } else { 1225 // We shouldn't be in an icache miss and also have a fault (an ITB 1226 // miss) 1227 if (fetchStatus[tid] == IcacheWaitResponse) { 1228 panic("Fetch should have exited prior to this!"); 1229 } 1230 1231 // Send the fault to commit. This thread will not do anything 1232 // until commit handles the fault. The only other way it can 1233 // wake up is if a squash comes along and changes the PC. 1234 assert(numInst < fetchWidth); 1235 // Get a sequence number. 1236 inst_seq = cpu->getAndIncrementInstSeq(); 1237 // We will use a nop in order to carry the fault. 1238 ext_inst = TheISA::NoopMachInst; 1239 1240 // Create a new DynInst from the dummy nop. 1241 DynInstPtr instruction = new DynInst(ext_inst, 1242 fetch_PC, fetch_NPC, fetch_MicroPC, 1243 next_PC, next_NPC, next_MicroPC, 1244 inst_seq, cpu); 1245 instruction->setPredTarg(next_NPC, next_NPC + instSize, 0); 1246 instruction->setTid(tid); 1247 1248 instruction->setASID(tid); 1249 1250 instruction->setThreadState(cpu->thread[tid]); 1251 1252 instruction->traceData = NULL; 1253 1254 instruction->setInstListIt(cpu->addInst(instruction)); 1255 1256 instruction->fault = fault; 1257 1258 toDecode->insts[numInst] = instruction; 1259 toDecode->size++; 1260 1261 DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid); 1262 1263 fetchStatus[tid] = TrapPending; 1264 status_change = true; 1265 1266 DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", 1267 tid, fault->name(), PC[tid]); 1268 } 1269} 1270 1271template<class Impl> 1272void 1273DefaultFetch<Impl>::recvRetry() 1274{ 1275 if (retryPkt != NULL) { 1276 assert(cacheBlocked); 1277 assert(retryTid != -1); 1278 assert(fetchStatus[retryTid] == IcacheWaitRetry); 1279 1280 if (icachePort->sendTiming(retryPkt)) { 1281 fetchStatus[retryTid] = IcacheWaitResponse; 1282 retryPkt = NULL; 1283 retryTid = -1; 1284 cacheBlocked = false; 1285 } 1286 } else { 1287 assert(retryTid == -1); 1288 // Access has been squashed since it was sent out. Just clear 1289 // the cache being blocked. 1290 cacheBlocked = false; 1291 } 1292} 1293 1294/////////////////////////////////////// 1295// // 1296// SMT FETCH POLICY MAINTAINED HERE // 1297// // 1298/////////////////////////////////////// 1299template<class Impl> 1300int 1301DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority) 1302{ 1303 if (numThreads > 1) { 1304 switch (fetch_priority) { 1305 1306 case SingleThread: 1307 return 0; 1308 1309 case RoundRobin: 1310 return roundRobin(); 1311 1312 case IQ: 1313 return iqCount(); 1314 1315 case LSQ: 1316 return lsqCount(); 1317 1318 case Branch: 1319 return branchCount(); 1320 1321 default: 1322 return -1; 1323 } 1324 } else { 1325 std::list<unsigned>::iterator thread = activeThreads->begin(); 1326 assert(thread != activeThreads->end()); 1327 int tid = *thread; 1328 1329 if (fetchStatus[tid] == Running || 1330 fetchStatus[tid] == IcacheAccessComplete || 1331 fetchStatus[tid] == Idle) { 1332 return tid; 1333 } else { 1334 return -1; 1335 } 1336 } 1337 1338} 1339 1340 1341template<class Impl> 1342int 1343DefaultFetch<Impl>::roundRobin() 1344{ 1345 std::list<unsigned>::iterator pri_iter = priorityList.begin(); 1346 std::list<unsigned>::iterator end = priorityList.end(); 1347 1348 int high_pri; 1349 1350 while (pri_iter != end) { 1351 high_pri = *pri_iter; 1352 1353 assert(high_pri <= numThreads); 1354 1355 if (fetchStatus[high_pri] == Running || 1356 fetchStatus[high_pri] == IcacheAccessComplete || 1357 fetchStatus[high_pri] == Idle) { 1358 1359 priorityList.erase(pri_iter); 1360 priorityList.push_back(high_pri); 1361 1362 return high_pri; 1363 } 1364 1365 pri_iter++; 1366 } 1367 1368 return -1; 1369} 1370 1371template<class Impl> 1372int 1373DefaultFetch<Impl>::iqCount() 1374{ 1375 std::priority_queue<unsigned> PQ; 1376 1377 std::list<unsigned>::iterator threads = activeThreads->begin(); 1378 std::list<unsigned>::iterator end = activeThreads->end(); 1379 1380 while (threads != end) { 1381 unsigned tid = *threads++; 1382 1383 PQ.push(fromIEW->iewInfo[tid].iqCount); 1384 } 1385 1386 while (!PQ.empty()) { 1387 1388 unsigned high_pri = PQ.top(); 1389 1390 if (fetchStatus[high_pri] == Running || 1391 fetchStatus[high_pri] == IcacheAccessComplete || 1392 fetchStatus[high_pri] == Idle) 1393 return high_pri; 1394 else 1395 PQ.pop(); 1396 1397 } 1398 1399 return -1; 1400} 1401 1402template<class Impl> 1403int 1404DefaultFetch<Impl>::lsqCount() 1405{ 1406 std::priority_queue<unsigned> PQ; 1407 1408 std::list<unsigned>::iterator threads = activeThreads->begin(); 1409 std::list<unsigned>::iterator end = activeThreads->end(); 1410 1411 while (threads != end) { 1412 unsigned tid = *threads++; 1413 1414 PQ.push(fromIEW->iewInfo[tid].ldstqCount); 1415 } 1416 1417 while (!PQ.empty()) { 1418 1419 unsigned high_pri = PQ.top(); 1420 1421 if (fetchStatus[high_pri] == Running || 1422 fetchStatus[high_pri] == IcacheAccessComplete || 1423 fetchStatus[high_pri] == Idle) 1424 return high_pri; 1425 else 1426 PQ.pop(); 1427 1428 } 1429 1430 return -1; 1431} 1432 1433template<class Impl> 1434int 1435DefaultFetch<Impl>::branchCount() 1436{ 1437 std::list<unsigned>::iterator thread = activeThreads->begin(); 1438 assert(thread != activeThreads->end()); 1439 unsigned tid = *thread; 1440 1441 panic("Branch Count Fetch policy unimplemented\n"); 1442 return 0 * tid; 1443} 1444