fetch_impl.hh revision 4302:c45514c856b0 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/core.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53template<class Impl>
54void
55DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
56{
57    Port::setPeer(port);
58
59    fetch->setIcache();
60}
61
62template<class Impl>
63Tick
64DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
65{
66    panic("DefaultFetch doesn't expect recvAtomic callback!");
67    return curTick;
68}
69
70template<class Impl>
71void
72DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
73{
74    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
75            "functional call.");
76}
77
78template<class Impl>
79void
80DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
81{
82    if (status == RangeChange) {
83        if (!snoopRangeSent) {
84            snoopRangeSent = true;
85            sendStatusChange(Port::RangeChange);
86        }
87        return;
88    }
89
90    panic("DefaultFetch doesn't expect recvStatusChange callback!");
91}
92
93template<class Impl>
94bool
95DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
96{
97    DPRINTF(Fetch, "Received timing\n");
98    if (pkt->isResponse()) {
99        fetch->processCacheCompletion(pkt);
100    }
101    //else Snooped a coherence request, just return
102    return true;
103}
104
105template<class Impl>
106void
107DefaultFetch<Impl>::IcachePort::recvRetry()
108{
109    fetch->recvRetry();
110}
111
112template<class Impl>
113DefaultFetch<Impl>::DefaultFetch(Params *params)
114    : branchPred(params),
115      predecoder(NULL),
116      decodeToFetchDelay(params->decodeToFetchDelay),
117      renameToFetchDelay(params->renameToFetchDelay),
118      iewToFetchDelay(params->iewToFetchDelay),
119      commitToFetchDelay(params->commitToFetchDelay),
120      fetchWidth(params->fetchWidth),
121      cacheBlocked(false),
122      retryPkt(NULL),
123      retryTid(-1),
124      numThreads(params->numberOfThreads),
125      numFetchingThreads(params->smtNumFetchingThreads),
126      interruptPending(false),
127      drainPending(false),
128      switchedOut(false)
129{
130    if (numThreads > Impl::MaxThreads)
131        fatal("numThreads is not a valid value\n");
132
133    // Set fetch stage's status to inactive.
134    _status = Inactive;
135
136    std::string policy = params->smtFetchPolicy;
137
138    // Convert string to lowercase
139    std::transform(policy.begin(), policy.end(), policy.begin(),
140                   (int(*)(int)) tolower);
141
142    // Figure out fetch policy
143    if (policy == "singlethread") {
144        fetchPolicy = SingleThread;
145        if (numThreads > 1)
146            panic("Invalid Fetch Policy for a SMT workload.");
147    } else if (policy == "roundrobin") {
148        fetchPolicy = RoundRobin;
149        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
150    } else if (policy == "branch") {
151        fetchPolicy = Branch;
152        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
153    } else if (policy == "iqcount") {
154        fetchPolicy = IQ;
155        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
156    } else if (policy == "lsqcount") {
157        fetchPolicy = LSQ;
158        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
159    } else {
160        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
161              " RoundRobin,LSQcount,IQcount}\n");
162    }
163
164    // Get the size of an instruction.
165    instSize = sizeof(TheISA::MachInst);
166}
167
168template <class Impl>
169std::string
170DefaultFetch<Impl>::name() const
171{
172    return cpu->name() + ".fetch";
173}
174
175template <class Impl>
176void
177DefaultFetch<Impl>::regStats()
178{
179    icacheStallCycles
180        .name(name() + ".icacheStallCycles")
181        .desc("Number of cycles fetch is stalled on an Icache miss")
182        .prereq(icacheStallCycles);
183
184    fetchedInsts
185        .name(name() + ".Insts")
186        .desc("Number of instructions fetch has processed")
187        .prereq(fetchedInsts);
188
189    fetchedBranches
190        .name(name() + ".Branches")
191        .desc("Number of branches that fetch encountered")
192        .prereq(fetchedBranches);
193
194    predictedBranches
195        .name(name() + ".predictedBranches")
196        .desc("Number of branches that fetch has predicted taken")
197        .prereq(predictedBranches);
198
199    fetchCycles
200        .name(name() + ".Cycles")
201        .desc("Number of cycles fetch has run and was not squashing or"
202              " blocked")
203        .prereq(fetchCycles);
204
205    fetchSquashCycles
206        .name(name() + ".SquashCycles")
207        .desc("Number of cycles fetch has spent squashing")
208        .prereq(fetchSquashCycles);
209
210    fetchIdleCycles
211        .name(name() + ".IdleCycles")
212        .desc("Number of cycles fetch was idle")
213        .prereq(fetchIdleCycles);
214
215    fetchBlockedCycles
216        .name(name() + ".BlockedCycles")
217        .desc("Number of cycles fetch has spent blocked")
218        .prereq(fetchBlockedCycles);
219
220    fetchedCacheLines
221        .name(name() + ".CacheLines")
222        .desc("Number of cache lines fetched")
223        .prereq(fetchedCacheLines);
224
225    fetchMiscStallCycles
226        .name(name() + ".MiscStallCycles")
227        .desc("Number of cycles fetch has spent waiting on interrupts, or "
228              "bad addresses, or out of MSHRs")
229        .prereq(fetchMiscStallCycles);
230
231    fetchIcacheSquashes
232        .name(name() + ".IcacheSquashes")
233        .desc("Number of outstanding Icache misses that were squashed")
234        .prereq(fetchIcacheSquashes);
235
236    fetchNisnDist
237        .init(/* base value */ 0,
238              /* last value */ fetchWidth,
239              /* bucket size */ 1)
240        .name(name() + ".rateDist")
241        .desc("Number of instructions fetched each cycle (Total)")
242        .flags(Stats::pdf);
243
244    idleRate
245        .name(name() + ".idleRate")
246        .desc("Percent of cycles fetch was idle")
247        .prereq(idleRate);
248    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
249
250    branchRate
251        .name(name() + ".branchRate")
252        .desc("Number of branch fetches per cycle")
253        .flags(Stats::total);
254    branchRate = fetchedBranches / cpu->numCycles;
255
256    fetchRate
257        .name(name() + ".rate")
258        .desc("Number of inst fetches per cycle")
259        .flags(Stats::total);
260    fetchRate = fetchedInsts / cpu->numCycles;
261
262    branchPred.regStats();
263}
264
265template<class Impl>
266void
267DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
268{
269    DPRINTF(Fetch, "Setting the CPU pointer.\n");
270    cpu = cpu_ptr;
271
272    // Name is finally available, so create the port.
273    icachePort = new IcachePort(this);
274
275    icachePort->snoopRangeSent = false;
276
277#if USE_CHECKER
278    if (cpu->checker) {
279        cpu->checker->setIcachePort(icachePort);
280    }
281#endif
282
283    // Schedule fetch to get the correct PC from the CPU
284    // scheduleFetchStartupEvent(1);
285
286    // Fetch needs to start fetching instructions at the very beginning,
287    // so it must start up in active state.
288    switchToActive();
289}
290
291template<class Impl>
292void
293DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
294{
295    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
296    timeBuffer = time_buffer;
297
298    // Create wires to get information from proper places in time buffer.
299    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
300    fromRename = timeBuffer->getWire(-renameToFetchDelay);
301    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
302    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
303}
304
305template<class Impl>
306void
307DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
308{
309    DPRINTF(Fetch, "Setting active threads list pointer.\n");
310    activeThreads = at_ptr;
311}
312
313template<class Impl>
314void
315DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
316{
317    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
318    fetchQueue = fq_ptr;
319
320    // Create wire to write information to proper place in fetch queue.
321    toDecode = fetchQueue->getWire(0);
322}
323
324template<class Impl>
325void
326DefaultFetch<Impl>::initStage()
327{
328    // Setup PC and nextPC with initial state.
329    for (int tid = 0; tid < numThreads; tid++) {
330        PC[tid] = cpu->readPC(tid);
331        nextPC[tid] = cpu->readNextPC(tid);
332        nextNPC[tid] = cpu->readNextNPC(tid);
333    }
334
335    for (int tid=0; tid < numThreads; tid++) {
336
337        fetchStatus[tid] = Running;
338
339        priorityList.push_back(tid);
340
341        memReq[tid] = NULL;
342
343        stalls[tid].decode = false;
344        stalls[tid].rename = false;
345        stalls[tid].iew = false;
346        stalls[tid].commit = false;
347    }
348}
349
350template<class Impl>
351void
352DefaultFetch<Impl>::setIcache()
353{
354    // Size of cache block.
355    cacheBlkSize = icachePort->peerBlockSize();
356
357    // Create mask to get rid of offset bits.
358    cacheBlkMask = (cacheBlkSize - 1);
359
360    for (int tid=0; tid < numThreads; tid++) {
361        // Create space to store a cache line.
362        cacheData[tid] = new uint8_t[cacheBlkSize];
363        cacheDataPC[tid] = 0;
364        cacheDataValid[tid] = false;
365    }
366}
367
368template<class Impl>
369void
370DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
371{
372    unsigned tid = pkt->req->getThreadNum();
373
374    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
375
376    // Only change the status if it's still waiting on the icache access
377    // to return.
378    if (fetchStatus[tid] != IcacheWaitResponse ||
379        pkt->req != memReq[tid] ||
380        isSwitchedOut()) {
381        ++fetchIcacheSquashes;
382        delete pkt->req;
383        delete pkt;
384        return;
385    }
386
387    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
388    cacheDataValid[tid] = true;
389
390    if (!drainPending) {
391        // Wake up the CPU (if it went to sleep and was waiting on
392        // this completion event).
393        cpu->wakeCPU();
394
395        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
396                tid);
397
398        switchToActive();
399    }
400
401    // Only switch to IcacheAccessComplete if we're not stalled as well.
402    if (checkStall(tid)) {
403        fetchStatus[tid] = Blocked;
404    } else {
405        fetchStatus[tid] = IcacheAccessComplete;
406    }
407
408    // Reset the mem req to NULL.
409    delete pkt->req;
410    delete pkt;
411    memReq[tid] = NULL;
412}
413
414template <class Impl>
415bool
416DefaultFetch<Impl>::drain()
417{
418    // Fetch is ready to drain at any time.
419    cpu->signalDrained();
420    drainPending = true;
421    return true;
422}
423
424template <class Impl>
425void
426DefaultFetch<Impl>::resume()
427{
428    drainPending = false;
429}
430
431template <class Impl>
432void
433DefaultFetch<Impl>::switchOut()
434{
435    switchedOut = true;
436    // Branch predictor needs to have its state cleared.
437    branchPred.switchOut();
438}
439
440template <class Impl>
441void
442DefaultFetch<Impl>::takeOverFrom()
443{
444    // Reset all state
445    for (int i = 0; i < Impl::MaxThreads; ++i) {
446        stalls[i].decode = 0;
447        stalls[i].rename = 0;
448        stalls[i].iew = 0;
449        stalls[i].commit = 0;
450        PC[i] = cpu->readPC(i);
451        nextPC[i] = cpu->readNextPC(i);
452#if ISA_HAS_DELAY_SLOT
453        nextNPC[i] = cpu->readNextNPC(i);
454#else
455        nextNPC[i] = nextPC[i] + sizeof(TheISA::MachInst);
456#endif
457        fetchStatus[i] = Running;
458    }
459    numInst = 0;
460    wroteToTimeBuffer = false;
461    _status = Inactive;
462    switchedOut = false;
463    interruptPending = false;
464    branchPred.takeOverFrom();
465}
466
467template <class Impl>
468void
469DefaultFetch<Impl>::wakeFromQuiesce()
470{
471    DPRINTF(Fetch, "Waking up from quiesce\n");
472    // Hopefully this is safe
473    // @todo: Allow other threads to wake from quiesce.
474    fetchStatus[0] = Running;
475}
476
477template <class Impl>
478inline void
479DefaultFetch<Impl>::switchToActive()
480{
481    if (_status == Inactive) {
482        DPRINTF(Activity, "Activating stage.\n");
483
484        cpu->activateStage(O3CPU::FetchIdx);
485
486        _status = Active;
487    }
488}
489
490template <class Impl>
491inline void
492DefaultFetch<Impl>::switchToInactive()
493{
494    if (_status == Active) {
495        DPRINTF(Activity, "Deactivating stage.\n");
496
497        cpu->deactivateStage(O3CPU::FetchIdx);
498
499        _status = Inactive;
500    }
501}
502
503template <class Impl>
504bool
505DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
506                                          Addr &next_NPC)
507{
508    // Do branch prediction check here.
509    // A bit of a misnomer...next_PC is actually the current PC until
510    // this function updates it.
511    bool predict_taken;
512
513    if (!inst->isControl()) {
514        next_PC  = next_NPC;
515        next_NPC = next_NPC + instSize;
516        inst->setPredTarg(next_PC, next_NPC);
517        inst->setPredTaken(false);
518        return false;
519    }
520
521    int tid = inst->threadNumber;
522    Addr pred_PC = next_PC;
523    predict_taken = branchPred.predict(inst, pred_PC, tid);
524
525/*    if (predict_taken) {
526        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n",
527                tid, pred_PC);
528    } else {
529        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid);
530    }*/
531
532#if ISA_HAS_DELAY_SLOT
533    next_PC = next_NPC;
534    if (predict_taken)
535        next_NPC = pred_PC;
536    else
537        next_NPC += instSize;
538#else
539    if (predict_taken)
540        next_PC = pred_PC;
541    else
542        next_PC += instSize;
543    next_NPC = next_PC + instSize;
544#endif
545/*    DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n",
546            tid, next_PC, next_NPC);*/
547    inst->setPredTarg(next_PC, next_NPC);
548    inst->setPredTaken(predict_taken);
549
550    ++fetchedBranches;
551
552    if (predict_taken) {
553        ++predictedBranches;
554    }
555
556    return predict_taken;
557}
558
559template <class Impl>
560bool
561DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
562{
563    Fault fault = NoFault;
564
565    //AlphaDep
566    if (cacheBlocked) {
567        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
568                tid);
569        return false;
570    } else if (isSwitchedOut()) {
571        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
572                tid);
573        return false;
574    } else if (interruptPending && !(fetch_PC & 0x3)) {
575        // Hold off fetch from getting new instructions when:
576        // Cache is blocked, or
577        // while an interrupt is pending and we're not in PAL mode, or
578        // fetch is switched out.
579        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
580                tid);
581        return false;
582    }
583
584    // Align the fetch PC so it's at the start of a cache block.
585    Addr block_PC = icacheBlockAlignPC(fetch_PC);
586
587    // If we've already got the block, no need to try to fetch it again.
588    if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
589        return true;
590    }
591
592    // Setup the memReq to do a read of the first instruction's address.
593    // Set the appropriate read size and flags as well.
594    // Build request here.
595    RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
596                                     fetch_PC, cpu->readCpuId(), tid);
597
598    memReq[tid] = mem_req;
599
600    // Translate the instruction request.
601    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
602
603    // In the case of faults, the fetch stage may need to stall and wait
604    // for the ITB miss to be handled.
605
606    // If translation was successful, attempt to read the first
607    // instruction.
608    if (fault == NoFault) {
609#if 0
610        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
611            memReq[tid]->isUncacheable()) {
612            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
613                    "misspeculating path)!",
614                    memReq[tid]->paddr);
615            ret_fault = TheISA::genMachineCheckFault();
616            return false;
617        }
618#endif
619
620        // Build packet here.
621        PacketPtr data_pkt = new Packet(mem_req,
622                                        MemCmd::ReadReq, Packet::Broadcast);
623        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
624
625        cacheDataPC[tid] = block_PC;
626        cacheDataValid[tid] = false;
627
628        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
629
630        fetchedCacheLines++;
631
632        // Now do the timing access to see whether or not the instruction
633        // exists within the cache.
634        if (!icachePort->sendTiming(data_pkt)) {
635            if (data_pkt->result == Packet::BadAddress) {
636                fault = TheISA::genMachineCheckFault();
637                delete mem_req;
638                memReq[tid] = NULL;
639                warn("Bad address!\n");
640            }
641            assert(retryPkt == NULL);
642            assert(retryTid == -1);
643            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
644            fetchStatus[tid] = IcacheWaitRetry;
645            retryPkt = data_pkt;
646            retryTid = tid;
647            cacheBlocked = true;
648            return false;
649        }
650
651        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
652
653        lastIcacheStall[tid] = curTick;
654
655        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
656                "response.\n", tid);
657
658        fetchStatus[tid] = IcacheWaitResponse;
659    } else {
660        delete mem_req;
661        memReq[tid] = NULL;
662    }
663
664    ret_fault = fault;
665    return true;
666}
667
668template <class Impl>
669inline void
670DefaultFetch<Impl>::doSquash(const Addr &new_PC,
671        const Addr &new_NPC, unsigned tid)
672{
673    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
674            tid, new_PC, new_NPC);
675
676    PC[tid] = new_PC;
677    nextPC[tid] = new_NPC;
678    nextNPC[tid] = new_NPC + instSize;
679
680    // Clear the icache miss if it's outstanding.
681    if (fetchStatus[tid] == IcacheWaitResponse) {
682        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
683                tid);
684        memReq[tid] = NULL;
685    }
686
687    // Get rid of the retrying packet if it was from this thread.
688    if (retryTid == tid) {
689        assert(cacheBlocked);
690        if (retryPkt) {
691            delete retryPkt->req;
692            delete retryPkt;
693        }
694        retryPkt = NULL;
695        retryTid = -1;
696    }
697
698    fetchStatus[tid] = Squashing;
699
700    ++fetchSquashCycles;
701}
702
703template<class Impl>
704void
705DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
706                                     const InstSeqNum &seq_num,
707                                     unsigned tid)
708{
709    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
710
711    doSquash(new_PC, new_NPC, tid);
712
713    // Tell the CPU to remove any instructions that are in flight between
714    // fetch and decode.
715    cpu->removeInstsUntil(seq_num, tid);
716}
717
718template<class Impl>
719bool
720DefaultFetch<Impl>::checkStall(unsigned tid) const
721{
722    bool ret_val = false;
723
724    if (cpu->contextSwitch) {
725        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
726        ret_val = true;
727    } else if (stalls[tid].decode) {
728        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
729        ret_val = true;
730    } else if (stalls[tid].rename) {
731        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
732        ret_val = true;
733    } else if (stalls[tid].iew) {
734        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
735        ret_val = true;
736    } else if (stalls[tid].commit) {
737        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
738        ret_val = true;
739    }
740
741    return ret_val;
742}
743
744template<class Impl>
745typename DefaultFetch<Impl>::FetchStatus
746DefaultFetch<Impl>::updateFetchStatus()
747{
748    //Check Running
749    std::list<unsigned>::iterator threads = activeThreads->begin();
750    std::list<unsigned>::iterator end = activeThreads->end();
751
752    while (threads != end) {
753        unsigned tid = *threads++;
754
755        if (fetchStatus[tid] == Running ||
756            fetchStatus[tid] == Squashing ||
757            fetchStatus[tid] == IcacheAccessComplete) {
758
759            if (_status == Inactive) {
760                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
761
762                if (fetchStatus[tid] == IcacheAccessComplete) {
763                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
764                            "completion\n",tid);
765                }
766
767                cpu->activateStage(O3CPU::FetchIdx);
768            }
769
770            return Active;
771        }
772    }
773
774    // Stage is switching from active to inactive, notify CPU of it.
775    if (_status == Active) {
776        DPRINTF(Activity, "Deactivating stage.\n");
777
778        cpu->deactivateStage(O3CPU::FetchIdx);
779    }
780
781    return Inactive;
782}
783
784template <class Impl>
785void
786DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
787                           const InstSeqNum &seq_num,
788                           bool squash_delay_slot, unsigned tid)
789{
790    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
791
792    doSquash(new_PC, new_NPC, tid);
793
794#if ISA_HAS_DELAY_SLOT
795    // Tell the CPU to remove any instructions that are not in the ROB.
796    cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
797#else
798    // Tell the CPU to remove any instructions that are not in the ROB.
799    cpu->removeInstsNotInROB(tid, true, 0);
800#endif
801}
802
803template <class Impl>
804void
805DefaultFetch<Impl>::tick()
806{
807    std::list<unsigned>::iterator threads = activeThreads->begin();
808    std::list<unsigned>::iterator end = activeThreads->end();
809    bool status_change = false;
810
811    wroteToTimeBuffer = false;
812
813    while (threads != end) {
814        unsigned tid = *threads++;
815
816        // Check the signals for each thread to determine the proper status
817        // for each thread.
818        bool updated_status = checkSignalsAndUpdate(tid);
819        status_change =  status_change || updated_status;
820    }
821
822    DPRINTF(Fetch, "Running stage.\n");
823
824    // Reset the number of the instruction we're fetching.
825    numInst = 0;
826
827#if FULL_SYSTEM
828    if (fromCommit->commitInfo[0].interruptPending) {
829        interruptPending = true;
830    }
831
832    if (fromCommit->commitInfo[0].clearInterrupt) {
833        interruptPending = false;
834    }
835#endif
836
837    for (threadFetched = 0; threadFetched < numFetchingThreads;
838         threadFetched++) {
839        // Fetch each of the actively fetching threads.
840        fetch(status_change);
841    }
842
843    // Record number of instructions fetched this cycle for distribution.
844    fetchNisnDist.sample(numInst);
845
846    if (status_change) {
847        // Change the fetch stage status if there was a status change.
848        _status = updateFetchStatus();
849    }
850
851    // If there was activity this cycle, inform the CPU of it.
852    if (wroteToTimeBuffer || cpu->contextSwitch) {
853        DPRINTF(Activity, "Activity this cycle.\n");
854
855        cpu->activityThisCycle();
856    }
857}
858
859template <class Impl>
860bool
861DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
862{
863    // Update the per thread stall statuses.
864    if (fromDecode->decodeBlock[tid]) {
865        stalls[tid].decode = true;
866    }
867
868    if (fromDecode->decodeUnblock[tid]) {
869        assert(stalls[tid].decode);
870        assert(!fromDecode->decodeBlock[tid]);
871        stalls[tid].decode = false;
872    }
873
874    if (fromRename->renameBlock[tid]) {
875        stalls[tid].rename = true;
876    }
877
878    if (fromRename->renameUnblock[tid]) {
879        assert(stalls[tid].rename);
880        assert(!fromRename->renameBlock[tid]);
881        stalls[tid].rename = false;
882    }
883
884    if (fromIEW->iewBlock[tid]) {
885        stalls[tid].iew = true;
886    }
887
888    if (fromIEW->iewUnblock[tid]) {
889        assert(stalls[tid].iew);
890        assert(!fromIEW->iewBlock[tid]);
891        stalls[tid].iew = false;
892    }
893
894    if (fromCommit->commitBlock[tid]) {
895        stalls[tid].commit = true;
896    }
897
898    if (fromCommit->commitUnblock[tid]) {
899        assert(stalls[tid].commit);
900        assert(!fromCommit->commitBlock[tid]);
901        stalls[tid].commit = false;
902    }
903
904    // Check squash signals from commit.
905    if (fromCommit->commitInfo[tid].squash) {
906
907        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
908                "from commit.\n",tid);
909
910#if ISA_HAS_DELAY_SLOT
911    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
912#else
913    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
914#endif
915        // In any case, squash.
916        squash(fromCommit->commitInfo[tid].nextPC,
917               fromCommit->commitInfo[tid].nextNPC,
918               doneSeqNum,
919               fromCommit->commitInfo[tid].squashDelaySlot,
920               tid);
921
922        // Also check if there's a mispredict that happened.
923        if (fromCommit->commitInfo[tid].branchMispredict) {
924            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
925                              fromCommit->commitInfo[tid].nextPC,
926                              fromCommit->commitInfo[tid].branchTaken,
927                              tid);
928        } else {
929            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
930                              tid);
931        }
932
933        return true;
934    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
935        // Update the branch predictor if it wasn't a squashed instruction
936        // that was broadcasted.
937        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
938    }
939
940    // Check ROB squash signals from commit.
941    if (fromCommit->commitInfo[tid].robSquashing) {
942        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
943
944        // Continue to squash.
945        fetchStatus[tid] = Squashing;
946
947        return true;
948    }
949
950    // Check squash signals from decode.
951    if (fromDecode->decodeInfo[tid].squash) {
952        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
953                "from decode.\n",tid);
954
955        // Update the branch predictor.
956        if (fromDecode->decodeInfo[tid].branchMispredict) {
957            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
958                              fromDecode->decodeInfo[tid].nextPC,
959                              fromDecode->decodeInfo[tid].branchTaken,
960                              tid);
961        } else {
962            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
963                              tid);
964        }
965
966        if (fetchStatus[tid] != Squashing) {
967
968#if ISA_HAS_DELAY_SLOT
969            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
970#else
971            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
972#endif
973            DPRINTF(Fetch, "Squashing from decode with PC = %#x, NPC = %#x\n",
974                    fromDecode->decodeInfo[tid].nextPC,
975                    fromDecode->decodeInfo[tid].nextNPC);
976            // Squash unless we're already squashing
977            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
978                             fromDecode->decodeInfo[tid].nextNPC,
979                             doneSeqNum,
980                             tid);
981
982            return true;
983        }
984    }
985
986    if (checkStall(tid) &&
987        fetchStatus[tid] != IcacheWaitResponse &&
988        fetchStatus[tid] != IcacheWaitRetry) {
989        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
990
991        fetchStatus[tid] = Blocked;
992
993        return true;
994    }
995
996    if (fetchStatus[tid] == Blocked ||
997        fetchStatus[tid] == Squashing) {
998        // Switch status to running if fetch isn't being told to block or
999        // squash this cycle.
1000        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1001                tid);
1002
1003        fetchStatus[tid] = Running;
1004
1005        return true;
1006    }
1007
1008    // If we've reached this point, we have not gotten any signals that
1009    // cause fetch to change its status.  Fetch remains the same as before.
1010    return false;
1011}
1012
1013template<class Impl>
1014void
1015DefaultFetch<Impl>::fetch(bool &status_change)
1016{
1017    //////////////////////////////////////////
1018    // Start actual fetch
1019    //////////////////////////////////////////
1020    int tid = getFetchingThread(fetchPolicy);
1021
1022    if (tid == -1 || drainPending) {
1023        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1024
1025        // Breaks looping condition in tick()
1026        threadFetched = numFetchingThreads;
1027        return;
1028    }
1029
1030    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1031
1032    // The current PC.
1033    Addr &fetch_PC = PC[tid];
1034
1035    Addr &fetch_NPC = nextPC[tid];
1036
1037    // Fault code for memory access.
1038    Fault fault = NoFault;
1039
1040    // If returning from the delay of a cache miss, then update the status
1041    // to running, otherwise do the cache access.  Possibly move this up
1042    // to tick() function.
1043    if (fetchStatus[tid] == IcacheAccessComplete) {
1044        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1045                tid);
1046
1047        fetchStatus[tid] = Running;
1048        status_change = true;
1049    } else if (fetchStatus[tid] == Running) {
1050        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1051                "instruction, starting at PC %08p.\n",
1052                tid, fetch_PC);
1053
1054        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1055        if (!fetch_success) {
1056            if (cacheBlocked) {
1057                ++icacheStallCycles;
1058            } else {
1059                ++fetchMiscStallCycles;
1060            }
1061            return;
1062        }
1063    } else {
1064        if (fetchStatus[tid] == Idle) {
1065            ++fetchIdleCycles;
1066            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1067        } else if (fetchStatus[tid] == Blocked) {
1068            ++fetchBlockedCycles;
1069            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1070        } else if (fetchStatus[tid] == Squashing) {
1071            ++fetchSquashCycles;
1072            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1073        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1074            ++icacheStallCycles;
1075            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1076        }
1077
1078        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1079        // fetch should do nothing.
1080        return;
1081    }
1082
1083    ++fetchCycles;
1084
1085    // If we had a stall due to an icache miss, then return.
1086    if (fetchStatus[tid] == IcacheWaitResponse) {
1087        ++icacheStallCycles;
1088        status_change = true;
1089        return;
1090    }
1091
1092    Addr next_PC = fetch_PC;
1093    Addr next_NPC = fetch_NPC;
1094
1095    InstSeqNum inst_seq;
1096    MachInst inst;
1097    ExtMachInst ext_inst;
1098    // @todo: Fix this hack.
1099    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1100
1101    if (fault == NoFault) {
1102        // If the read of the first instruction was successful, then grab the
1103        // instructions from the rest of the cache line and put them into the
1104        // queue heading to decode.
1105
1106        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1107                "decode.\n",tid);
1108
1109        // Need to keep track of whether or not a predicted branch
1110        // ended this fetch block.
1111        bool predicted_branch = false;
1112
1113        for (;
1114             offset < cacheBlkSize &&
1115                 numInst < fetchWidth &&
1116                 !predicted_branch;
1117             ++numInst) {
1118
1119            // If we're branching after this instruction, quite fetching
1120            // from the same block then.
1121            predicted_branch =
1122                (fetch_PC + sizeof(TheISA::MachInst) != fetch_NPC);
1123            if (predicted_branch) {
1124                DPRINTF(Fetch, "Branch detected with PC = %#x, NPC = %#x\n",
1125                        fetch_PC, fetch_NPC);
1126            }
1127
1128
1129            // Get a sequence number.
1130            inst_seq = cpu->getAndIncrementInstSeq();
1131
1132            // Make sure this is a valid index.
1133            assert(offset <= cacheBlkSize - instSize);
1134
1135            // Get the instruction from the array of the cache line.
1136            inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1137                        (&cacheData[tid][offset]));
1138
1139            predecoder.setTC(cpu->thread[tid]->getTC());
1140            predecoder.moreBytes(fetch_PC, 0, inst);
1141
1142            ext_inst = predecoder.getExtMachInst();
1143
1144            // Create a new DynInst from the instruction fetched.
1145            DynInstPtr instruction = new DynInst(ext_inst,
1146                                                 fetch_PC, fetch_NPC,
1147                                                 next_PC, next_NPC,
1148                                                 inst_seq, cpu);
1149            instruction->setTid(tid);
1150
1151            instruction->setASID(tid);
1152
1153            instruction->setThreadState(cpu->thread[tid]);
1154
1155            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1156                    "[sn:%lli]\n",
1157                    tid, instruction->readPC(), inst_seq);
1158
1159            //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1160
1161            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1162                    tid, instruction->staticInst->disassemble(fetch_PC));
1163
1164            instruction->traceData =
1165                Trace::getInstRecord(curTick, cpu->tcBase(tid),
1166                                     instruction->staticInst,
1167                                     instruction->readPC());
1168
1169            ///FIXME This needs to be more robust in dealing with delay slots
1170#if !ISA_HAS_DELAY_SLOT
1171//	    predicted_branch |=
1172#endif
1173            lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
1174            predicted_branch |= (next_PC != fetch_NPC);
1175
1176            // Add instruction to the CPU's list of instructions.
1177            instruction->setInstListIt(cpu->addInst(instruction));
1178
1179            // Write the instruction to the first slot in the queue
1180            // that heads to decode.
1181            toDecode->insts[numInst] = instruction;
1182
1183            toDecode->size++;
1184
1185            // Increment stat of fetched instructions.
1186            ++fetchedInsts;
1187
1188            // Move to the next instruction, unless we have a branch.
1189            fetch_PC = next_PC;
1190            fetch_NPC = next_NPC;
1191
1192            if (instruction->isQuiesce()) {
1193                DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1194                        curTick);
1195                fetchStatus[tid] = QuiescePending;
1196                ++numInst;
1197                status_change = true;
1198                break;
1199            }
1200
1201            offset += instSize;
1202        }
1203
1204        if (offset >= cacheBlkSize) {
1205            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1206                    "block.\n", tid);
1207        } else if (numInst >= fetchWidth) {
1208            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1209                    "for this cycle.\n", tid);
1210        } else if (predicted_branch) {
1211            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1212                    "instruction encountered.\n", tid);
1213        }
1214    }
1215
1216    if (numInst > 0) {
1217        wroteToTimeBuffer = true;
1218    }
1219
1220    // Now that fetching is completed, update the PC to signify what the next
1221    // cycle will be.
1222    if (fault == NoFault) {
1223        PC[tid] = next_PC;
1224        nextPC[tid] = next_NPC;
1225        nextNPC[tid] = next_NPC + instSize;
1226#if ISA_HAS_DELAY_SLOT
1227        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1228#else
1229        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, next_PC);
1230#endif
1231    } else {
1232        // We shouldn't be in an icache miss and also have a fault (an ITB
1233        // miss)
1234        if (fetchStatus[tid] == IcacheWaitResponse) {
1235            panic("Fetch should have exited prior to this!");
1236        }
1237
1238        // Send the fault to commit.  This thread will not do anything
1239        // until commit handles the fault.  The only other way it can
1240        // wake up is if a squash comes along and changes the PC.
1241#if FULL_SYSTEM
1242        assert(numInst < fetchWidth);
1243        // Get a sequence number.
1244        inst_seq = cpu->getAndIncrementInstSeq();
1245        // We will use a nop in order to carry the fault.
1246        ext_inst = TheISA::NoopMachInst;
1247
1248        // Create a new DynInst from the dummy nop.
1249        DynInstPtr instruction = new DynInst(ext_inst,
1250                                             fetch_PC, fetch_NPC,
1251                                             next_PC, next_NPC,
1252                                             inst_seq, cpu);
1253        instruction->setPredTarg(next_PC, next_NPC);
1254        instruction->setTid(tid);
1255
1256        instruction->setASID(tid);
1257
1258        instruction->setThreadState(cpu->thread[tid]);
1259
1260        instruction->traceData = NULL;
1261
1262        instruction->setInstListIt(cpu->addInst(instruction));
1263
1264        instruction->fault = fault;
1265
1266        toDecode->insts[numInst] = instruction;
1267        toDecode->size++;
1268
1269        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1270
1271        fetchStatus[tid] = TrapPending;
1272        status_change = true;
1273#else // !FULL_SYSTEM
1274        fetchStatus[tid] = TrapPending;
1275        status_change = true;
1276
1277#endif // FULL_SYSTEM
1278        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1279                tid, fault->name(), PC[tid]);
1280    }
1281}
1282
1283template<class Impl>
1284void
1285DefaultFetch<Impl>::recvRetry()
1286{
1287    if (retryPkt != NULL) {
1288        assert(cacheBlocked);
1289        assert(retryTid != -1);
1290        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1291
1292        if (icachePort->sendTiming(retryPkt)) {
1293            fetchStatus[retryTid] = IcacheWaitResponse;
1294            retryPkt = NULL;
1295            retryTid = -1;
1296            cacheBlocked = false;
1297        }
1298    } else {
1299        assert(retryTid == -1);
1300        // Access has been squashed since it was sent out.  Just clear
1301        // the cache being blocked.
1302        cacheBlocked = false;
1303    }
1304}
1305
1306///////////////////////////////////////
1307//                                   //
1308//  SMT FETCH POLICY MAINTAINED HERE //
1309//                                   //
1310///////////////////////////////////////
1311template<class Impl>
1312int
1313DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1314{
1315    if (numThreads > 1) {
1316        switch (fetch_priority) {
1317
1318          case SingleThread:
1319            return 0;
1320
1321          case RoundRobin:
1322            return roundRobin();
1323
1324          case IQ:
1325            return iqCount();
1326
1327          case LSQ:
1328            return lsqCount();
1329
1330          case Branch:
1331            return branchCount();
1332
1333          default:
1334            return -1;
1335        }
1336    } else {
1337        std::list<unsigned>::iterator thread = activeThreads->begin();
1338        assert(thread != activeThreads->end());
1339        int tid = *thread;
1340
1341        if (fetchStatus[tid] == Running ||
1342            fetchStatus[tid] == IcacheAccessComplete ||
1343            fetchStatus[tid] == Idle) {
1344            return tid;
1345        } else {
1346            return -1;
1347        }
1348    }
1349
1350}
1351
1352
1353template<class Impl>
1354int
1355DefaultFetch<Impl>::roundRobin()
1356{
1357    std::list<unsigned>::iterator pri_iter = priorityList.begin();
1358    std::list<unsigned>::iterator end      = priorityList.end();
1359
1360    int high_pri;
1361
1362    while (pri_iter != end) {
1363        high_pri = *pri_iter;
1364
1365        assert(high_pri <= numThreads);
1366
1367        if (fetchStatus[high_pri] == Running ||
1368            fetchStatus[high_pri] == IcacheAccessComplete ||
1369            fetchStatus[high_pri] == Idle) {
1370
1371            priorityList.erase(pri_iter);
1372            priorityList.push_back(high_pri);
1373
1374            return high_pri;
1375        }
1376
1377        pri_iter++;
1378    }
1379
1380    return -1;
1381}
1382
1383template<class Impl>
1384int
1385DefaultFetch<Impl>::iqCount()
1386{
1387    std::priority_queue<unsigned> PQ;
1388
1389    std::list<unsigned>::iterator threads = activeThreads->begin();
1390    std::list<unsigned>::iterator end = activeThreads->end();
1391
1392    while (threads != end) {
1393        unsigned tid = *threads++;
1394
1395        PQ.push(fromIEW->iewInfo[tid].iqCount);
1396    }
1397
1398    while (!PQ.empty()) {
1399
1400        unsigned high_pri = PQ.top();
1401
1402        if (fetchStatus[high_pri] == Running ||
1403            fetchStatus[high_pri] == IcacheAccessComplete ||
1404            fetchStatus[high_pri] == Idle)
1405            return high_pri;
1406        else
1407            PQ.pop();
1408
1409    }
1410
1411    return -1;
1412}
1413
1414template<class Impl>
1415int
1416DefaultFetch<Impl>::lsqCount()
1417{
1418    std::priority_queue<unsigned> PQ;
1419
1420    std::list<unsigned>::iterator threads = activeThreads->begin();
1421    std::list<unsigned>::iterator end = activeThreads->end();
1422
1423    while (threads != end) {
1424        unsigned tid = *threads++;
1425
1426        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1427    }
1428
1429    while (!PQ.empty()) {
1430
1431        unsigned high_pri = PQ.top();
1432
1433        if (fetchStatus[high_pri] == Running ||
1434            fetchStatus[high_pri] == IcacheAccessComplete ||
1435            fetchStatus[high_pri] == Idle)
1436            return high_pri;
1437        else
1438            PQ.pop();
1439
1440    }
1441
1442    return -1;
1443}
1444
1445template<class Impl>
1446int
1447DefaultFetch<Impl>::branchCount()
1448{
1449    std::list<unsigned>::iterator thread = activeThreads->begin();
1450    assert(thread != activeThreads->end());
1451    unsigned tid = *thread;
1452
1453    panic("Branch Count Fetch policy unimplemented\n");
1454    return 0 * tid;
1455}
1456