fetch_impl.hh revision 3791:f1783bae1afe 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "sim/system.hh"
49#endif // FULL_SYSTEM
50
51#include <algorithm>
52
53template<class Impl>
54Tick
55DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
56{
57    panic("DefaultFetch doesn't expect recvAtomic callback!");
58    return curTick;
59}
60
61template<class Impl>
62void
63DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
64{
65    DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
66            "functional call.");
67}
68
69template<class Impl>
70void
71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
72{
73    if (status == RangeChange) {
74        if (!snoopRangeSent) {
75            snoopRangeSent = true;
76            sendStatusChange(Port::RangeChange);
77        }
78        return;
79    }
80
81    panic("DefaultFetch doesn't expect recvStatusChange callback!");
82}
83
84template<class Impl>
85bool
86DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
87{
88    DPRINTF(Fetch, "Received timing\n");
89    if (pkt->isResponse()) {
90        fetch->processCacheCompletion(pkt);
91    }
92    //else Snooped a coherence request, just return
93    return true;
94}
95
96template<class Impl>
97void
98DefaultFetch<Impl>::IcachePort::recvRetry()
99{
100    fetch->recvRetry();
101}
102
103template<class Impl>
104DefaultFetch<Impl>::DefaultFetch(Params *params)
105    : branchPred(params),
106      decodeToFetchDelay(params->decodeToFetchDelay),
107      renameToFetchDelay(params->renameToFetchDelay),
108      iewToFetchDelay(params->iewToFetchDelay),
109      commitToFetchDelay(params->commitToFetchDelay),
110      fetchWidth(params->fetchWidth),
111      cacheBlocked(false),
112      retryPkt(NULL),
113      retryTid(-1),
114      numThreads(params->numberOfThreads),
115      numFetchingThreads(params->smtNumFetchingThreads),
116      interruptPending(false),
117      drainPending(false),
118      switchedOut(false)
119{
120    if (numThreads > Impl::MaxThreads)
121        fatal("numThreads is not a valid value\n");
122
123    // Set fetch stage's status to inactive.
124    _status = Inactive;
125
126    std::string policy = params->smtFetchPolicy;
127
128    // Convert string to lowercase
129    std::transform(policy.begin(), policy.end(), policy.begin(),
130                   (int(*)(int)) tolower);
131
132    // Figure out fetch policy
133    if (policy == "singlethread") {
134        fetchPolicy = SingleThread;
135        if (numThreads > 1)
136            panic("Invalid Fetch Policy for a SMT workload.");
137    } else if (policy == "roundrobin") {
138        fetchPolicy = RoundRobin;
139        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
140    } else if (policy == "branch") {
141        fetchPolicy = Branch;
142        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
143    } else if (policy == "iqcount") {
144        fetchPolicy = IQ;
145        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
146    } else if (policy == "lsqcount") {
147        fetchPolicy = LSQ;
148        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
149    } else {
150        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
151              " RoundRobin,LSQcount,IQcount}\n");
152    }
153
154    // Get the size of an instruction.
155    instSize = sizeof(TheISA::MachInst);
156}
157
158template <class Impl>
159std::string
160DefaultFetch<Impl>::name() const
161{
162    return cpu->name() + ".fetch";
163}
164
165template <class Impl>
166void
167DefaultFetch<Impl>::regStats()
168{
169    icacheStallCycles
170        .name(name() + ".icacheStallCycles")
171        .desc("Number of cycles fetch is stalled on an Icache miss")
172        .prereq(icacheStallCycles);
173
174    fetchedInsts
175        .name(name() + ".Insts")
176        .desc("Number of instructions fetch has processed")
177        .prereq(fetchedInsts);
178
179    fetchedBranches
180        .name(name() + ".Branches")
181        .desc("Number of branches that fetch encountered")
182        .prereq(fetchedBranches);
183
184    predictedBranches
185        .name(name() + ".predictedBranches")
186        .desc("Number of branches that fetch has predicted taken")
187        .prereq(predictedBranches);
188
189    fetchCycles
190        .name(name() + ".Cycles")
191        .desc("Number of cycles fetch has run and was not squashing or"
192              " blocked")
193        .prereq(fetchCycles);
194
195    fetchSquashCycles
196        .name(name() + ".SquashCycles")
197        .desc("Number of cycles fetch has spent squashing")
198        .prereq(fetchSquashCycles);
199
200    fetchIdleCycles
201        .name(name() + ".IdleCycles")
202        .desc("Number of cycles fetch was idle")
203        .prereq(fetchIdleCycles);
204
205    fetchBlockedCycles
206        .name(name() + ".BlockedCycles")
207        .desc("Number of cycles fetch has spent blocked")
208        .prereq(fetchBlockedCycles);
209
210    fetchedCacheLines
211        .name(name() + ".CacheLines")
212        .desc("Number of cache lines fetched")
213        .prereq(fetchedCacheLines);
214
215    fetchMiscStallCycles
216        .name(name() + ".MiscStallCycles")
217        .desc("Number of cycles fetch has spent waiting on interrupts, or "
218              "bad addresses, or out of MSHRs")
219        .prereq(fetchMiscStallCycles);
220
221    fetchIcacheSquashes
222        .name(name() + ".IcacheSquashes")
223        .desc("Number of outstanding Icache misses that were squashed")
224        .prereq(fetchIcacheSquashes);
225
226    fetchNisnDist
227        .init(/* base value */ 0,
228              /* last value */ fetchWidth,
229              /* bucket size */ 1)
230        .name(name() + ".rateDist")
231        .desc("Number of instructions fetched each cycle (Total)")
232        .flags(Stats::pdf);
233
234    idleRate
235        .name(name() + ".idleRate")
236        .desc("Percent of cycles fetch was idle")
237        .prereq(idleRate);
238    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
239
240    branchRate
241        .name(name() + ".branchRate")
242        .desc("Number of branch fetches per cycle")
243        .flags(Stats::total);
244    branchRate = fetchedBranches / cpu->numCycles;
245
246    fetchRate
247        .name(name() + ".rate")
248        .desc("Number of inst fetches per cycle")
249        .flags(Stats::total);
250    fetchRate = fetchedInsts / cpu->numCycles;
251
252    branchPred.regStats();
253}
254
255template<class Impl>
256void
257DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
258{
259    DPRINTF(Fetch, "Setting the CPU pointer.\n");
260    cpu = cpu_ptr;
261
262    // Name is finally available, so create the port.
263    icachePort = new IcachePort(this);
264
265    icachePort->snoopRangeSent = false;
266
267#if USE_CHECKER
268    if (cpu->checker) {
269        cpu->checker->setIcachePort(icachePort);
270    }
271#endif
272
273    // Schedule fetch to get the correct PC from the CPU
274    // scheduleFetchStartupEvent(1);
275
276    // Fetch needs to start fetching instructions at the very beginning,
277    // so it must start up in active state.
278    switchToActive();
279}
280
281template<class Impl>
282void
283DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
284{
285    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
286    timeBuffer = time_buffer;
287
288    // Create wires to get information from proper places in time buffer.
289    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
290    fromRename = timeBuffer->getWire(-renameToFetchDelay);
291    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
292    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
293}
294
295template<class Impl>
296void
297DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
298{
299    DPRINTF(Fetch, "Setting active threads list pointer.\n");
300    activeThreads = at_ptr;
301}
302
303template<class Impl>
304void
305DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
306{
307    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
308    fetchQueue = fq_ptr;
309
310    // Create wire to write information to proper place in fetch queue.
311    toDecode = fetchQueue->getWire(0);
312}
313
314template<class Impl>
315void
316DefaultFetch<Impl>::initStage()
317{
318    // Setup PC and nextPC with initial state.
319    for (int tid = 0; tid < numThreads; tid++) {
320        PC[tid] = cpu->readPC(tid);
321        nextPC[tid] = cpu->readNextPC(tid);
322#if ISA_HAS_DELAY_SLOT
323        nextNPC[tid] = cpu->readNextNPC(tid);
324#endif
325    }
326
327    // Size of cache block.
328    cacheBlkSize = icachePort->peerBlockSize();
329
330    // Create mask to get rid of offset bits.
331    cacheBlkMask = (cacheBlkSize - 1);
332
333    for (int tid=0; tid < numThreads; tid++) {
334
335        fetchStatus[tid] = Running;
336
337        priorityList.push_back(tid);
338
339        memReq[tid] = NULL;
340
341        // Create space to store a cache line.
342        cacheData[tid] = new uint8_t[cacheBlkSize];
343        cacheDataPC[tid] = 0;
344        cacheDataValid[tid] = false;
345
346        delaySlotInfo[tid].branchSeqNum = -1;
347        delaySlotInfo[tid].numInsts = 0;
348        delaySlotInfo[tid].targetAddr = 0;
349        delaySlotInfo[tid].targetReady = false;
350
351        stalls[tid].decode = false;
352        stalls[tid].rename = false;
353        stalls[tid].iew = false;
354        stalls[tid].commit = false;
355    }
356}
357
358template<class Impl>
359void
360DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
361{
362    unsigned tid = pkt->req->getThreadNum();
363
364    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
365
366    // Only change the status if it's still waiting on the icache access
367    // to return.
368    if (fetchStatus[tid] != IcacheWaitResponse ||
369        pkt->req != memReq[tid] ||
370        isSwitchedOut()) {
371        ++fetchIcacheSquashes;
372        delete pkt->req;
373        delete pkt;
374        return;
375    }
376
377    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
378    cacheDataValid[tid] = true;
379
380    if (!drainPending) {
381        // Wake up the CPU (if it went to sleep and was waiting on
382        // this completion event).
383        cpu->wakeCPU();
384
385        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
386                tid);
387
388        switchToActive();
389    }
390
391    // Only switch to IcacheAccessComplete if we're not stalled as well.
392    if (checkStall(tid)) {
393        fetchStatus[tid] = Blocked;
394    } else {
395        fetchStatus[tid] = IcacheAccessComplete;
396    }
397
398    // Reset the mem req to NULL.
399    delete pkt->req;
400    delete pkt;
401    memReq[tid] = NULL;
402}
403
404template <class Impl>
405bool
406DefaultFetch<Impl>::drain()
407{
408    // Fetch is ready to drain at any time.
409    cpu->signalDrained();
410    drainPending = true;
411    return true;
412}
413
414template <class Impl>
415void
416DefaultFetch<Impl>::resume()
417{
418    drainPending = false;
419}
420
421template <class Impl>
422void
423DefaultFetch<Impl>::switchOut()
424{
425    switchedOut = true;
426    // Branch predictor needs to have its state cleared.
427    branchPred.switchOut();
428}
429
430template <class Impl>
431void
432DefaultFetch<Impl>::takeOverFrom()
433{
434    // Reset all state
435    for (int i = 0; i < Impl::MaxThreads; ++i) {
436        stalls[i].decode = 0;
437        stalls[i].rename = 0;
438        stalls[i].iew = 0;
439        stalls[i].commit = 0;
440        PC[i] = cpu->readPC(i);
441        nextPC[i] = cpu->readNextPC(i);
442#if ISA_HAS_DELAY_SLOT
443        nextNPC[i] = cpu->readNextNPC(i);
444        delaySlotInfo[i].branchSeqNum = -1;
445        delaySlotInfo[i].numInsts = 0;
446        delaySlotInfo[i].targetAddr = 0;
447        delaySlotInfo[i].targetReady = false;
448#endif
449        fetchStatus[i] = Running;
450    }
451    numInst = 0;
452    wroteToTimeBuffer = false;
453    _status = Inactive;
454    switchedOut = false;
455    interruptPending = false;
456    branchPred.takeOverFrom();
457}
458
459template <class Impl>
460void
461DefaultFetch<Impl>::wakeFromQuiesce()
462{
463    DPRINTF(Fetch, "Waking up from quiesce\n");
464    // Hopefully this is safe
465    // @todo: Allow other threads to wake from quiesce.
466    fetchStatus[0] = Running;
467}
468
469template <class Impl>
470inline void
471DefaultFetch<Impl>::switchToActive()
472{
473    if (_status == Inactive) {
474        DPRINTF(Activity, "Activating stage.\n");
475
476        cpu->activateStage(O3CPU::FetchIdx);
477
478        _status = Active;
479    }
480}
481
482template <class Impl>
483inline void
484DefaultFetch<Impl>::switchToInactive()
485{
486    if (_status == Active) {
487        DPRINTF(Activity, "Deactivating stage.\n");
488
489        cpu->deactivateStage(O3CPU::FetchIdx);
490
491        _status = Inactive;
492    }
493}
494
495template <class Impl>
496bool
497DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
498                                          Addr &next_NPC)
499{
500    // Do branch prediction check here.
501    // A bit of a misnomer...next_PC is actually the current PC until
502    // this function updates it.
503    bool predict_taken;
504
505    if (!inst->isControl()) {
506#if ISA_HAS_DELAY_SLOT
507        Addr cur_PC = next_PC;
508        next_PC  = cur_PC + instSize;      //next_NPC;
509        next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
510        inst->setPredTarg(next_NPC);
511#else
512        next_PC = next_PC + instSize;
513        inst->setPredTarg(next_PC);
514#endif
515        return false;
516    }
517
518    int tid = inst->threadNumber;
519#if ISA_HAS_DELAY_SLOT
520    Addr pred_PC = next_PC;
521    predict_taken = branchPred.predict(inst, pred_PC, tid);
522
523    if (predict_taken) {
524        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
525    } else {
526        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
527    }
528
529    if (predict_taken) {
530        next_PC = next_NPC;
531        next_NPC = pred_PC;
532
533        // Update delay slot info
534        ++delaySlotInfo[tid].numInsts;
535        delaySlotInfo[tid].targetAddr = pred_PC;
536        DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
537                delaySlotInfo[tid].numInsts);
538    } else { // !predict_taken
539        if (inst->isCondDelaySlot()) {
540            next_PC = pred_PC;
541            // The delay slot is skipped here if there is on
542            // prediction
543        } else {
544            next_PC = next_NPC;
545            // No need to declare a delay slot here since
546            // there is no for the pred. target to jump
547        }
548
549        next_NPC = next_NPC + instSize;
550    }
551#else
552    predict_taken = branchPred.predict(inst, next_PC, tid);
553#endif
554
555    ++fetchedBranches;
556
557    if (predict_taken) {
558        ++predictedBranches;
559    }
560
561    return predict_taken;
562}
563
564template <class Impl>
565bool
566DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
567{
568    Fault fault = NoFault;
569
570    //AlphaDep
571    if (cacheBlocked) {
572        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
573                tid);
574        return false;
575    } else if (isSwitchedOut()) {
576        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
577                tid);
578        return false;
579    } else if (interruptPending && !(fetch_PC & 0x3)) {
580        // Hold off fetch from getting new instructions when:
581        // Cache is blocked, or
582        // while an interrupt is pending and we're not in PAL mode, or
583        // fetch is switched out.
584        DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
585                tid);
586        return false;
587    }
588
589    // Align the fetch PC so it's at the start of a cache block.
590    Addr block_PC = icacheBlockAlignPC(fetch_PC);
591
592    // If we've already got the block, no need to try to fetch it again.
593    if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
594        return true;
595    }
596
597    // Setup the memReq to do a read of the first instruction's address.
598    // Set the appropriate read size and flags as well.
599    // Build request here.
600    RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
601                                     fetch_PC, cpu->readCpuId(), tid);
602
603    memReq[tid] = mem_req;
604
605    // Translate the instruction request.
606    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
607
608    // In the case of faults, the fetch stage may need to stall and wait
609    // for the ITB miss to be handled.
610
611    // If translation was successful, attempt to read the first
612    // instruction.
613    if (fault == NoFault) {
614#if 0
615        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
616            memReq[tid]->isUncacheable()) {
617            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
618                    "misspeculating path)!",
619                    memReq[tid]->paddr);
620            ret_fault = TheISA::genMachineCheckFault();
621            return false;
622        }
623#endif
624
625        // Build packet here.
626        PacketPtr data_pkt = new Packet(mem_req,
627                                        Packet::ReadReq, Packet::Broadcast);
628        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
629
630        cacheDataPC[tid] = block_PC;
631        cacheDataValid[tid] = false;
632
633        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
634
635        fetchedCacheLines++;
636
637        // Now do the timing access to see whether or not the instruction
638        // exists within the cache.
639        if (!icachePort->sendTiming(data_pkt)) {
640            if (data_pkt->result == Packet::BadAddress) {
641                fault = TheISA::genMachineCheckFault();
642                delete mem_req;
643                memReq[tid] = NULL;
644            }
645            assert(retryPkt == NULL);
646            assert(retryTid == -1);
647            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
648            fetchStatus[tid] = IcacheWaitRetry;
649            retryPkt = data_pkt;
650            retryTid = tid;
651            cacheBlocked = true;
652            return false;
653        }
654
655        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
656
657        lastIcacheStall[tid] = curTick;
658
659        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
660                "response.\n", tid);
661
662        fetchStatus[tid] = IcacheWaitResponse;
663    } else {
664        delete mem_req;
665        memReq[tid] = NULL;
666    }
667
668    ret_fault = fault;
669    return true;
670}
671
672template <class Impl>
673inline void
674DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
675{
676    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
677            tid, new_PC);
678
679    PC[tid] = new_PC;
680    nextPC[tid] = new_PC + instSize;
681    nextNPC[tid] = new_PC + (2 * instSize);
682
683    // Clear the icache miss if it's outstanding.
684    if (fetchStatus[tid] == IcacheWaitResponse) {
685        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
686                tid);
687        memReq[tid] = NULL;
688    }
689
690    // Get rid of the retrying packet if it was from this thread.
691    if (retryTid == tid) {
692        assert(cacheBlocked);
693        cacheBlocked = false;
694        retryTid = -1;
695        delete retryPkt->req;
696        delete retryPkt;
697        retryPkt = NULL;
698    }
699
700    fetchStatus[tid] = Squashing;
701
702    ++fetchSquashCycles;
703}
704
705template<class Impl>
706void
707DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
708                                     const InstSeqNum &seq_num,
709                                     unsigned tid)
710{
711    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
712
713    doSquash(new_PC, tid);
714
715#if ISA_HAS_DELAY_SLOT
716    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
717        delaySlotInfo[tid].numInsts = 0;
718        delaySlotInfo[tid].targetAddr = 0;
719        delaySlotInfo[tid].targetReady = false;
720    }
721#endif
722
723    // Tell the CPU to remove any instructions that are in flight between
724    // fetch and decode.
725    cpu->removeInstsUntil(seq_num, tid);
726}
727
728template<class Impl>
729bool
730DefaultFetch<Impl>::checkStall(unsigned tid) const
731{
732    bool ret_val = false;
733
734    if (cpu->contextSwitch) {
735        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
736        ret_val = true;
737    } else if (stalls[tid].decode) {
738        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
739        ret_val = true;
740    } else if (stalls[tid].rename) {
741        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
742        ret_val = true;
743    } else if (stalls[tid].iew) {
744        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
745        ret_val = true;
746    } else if (stalls[tid].commit) {
747        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
748        ret_val = true;
749    }
750
751    return ret_val;
752}
753
754template<class Impl>
755typename DefaultFetch<Impl>::FetchStatus
756DefaultFetch<Impl>::updateFetchStatus()
757{
758    //Check Running
759    std::list<unsigned>::iterator threads = (*activeThreads).begin();
760
761    while (threads != (*activeThreads).end()) {
762
763        unsigned tid = *threads++;
764
765        if (fetchStatus[tid] == Running ||
766            fetchStatus[tid] == Squashing ||
767            fetchStatus[tid] == IcacheAccessComplete) {
768
769            if (_status == Inactive) {
770                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
771
772                if (fetchStatus[tid] == IcacheAccessComplete) {
773                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
774                            "completion\n",tid);
775                }
776
777                cpu->activateStage(O3CPU::FetchIdx);
778            }
779
780            return Active;
781        }
782    }
783
784    // Stage is switching from active to inactive, notify CPU of it.
785    if (_status == Active) {
786        DPRINTF(Activity, "Deactivating stage.\n");
787
788        cpu->deactivateStage(O3CPU::FetchIdx);
789    }
790
791    return Inactive;
792}
793
794template <class Impl>
795void
796DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
797                           bool squash_delay_slot, unsigned tid)
798{
799    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
800
801    doSquash(new_PC, tid);
802
803#if ISA_HAS_DELAY_SLOT
804    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
805        delaySlotInfo[tid].numInsts = 0;
806        delaySlotInfo[tid].targetAddr = 0;
807        delaySlotInfo[tid].targetReady = false;
808    }
809
810    // Tell the CPU to remove any instructions that are not in the ROB.
811    cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
812#else
813    // Tell the CPU to remove any instructions that are not in the ROB.
814    cpu->removeInstsNotInROB(tid, true, 0);
815#endif
816}
817
818template <class Impl>
819void
820DefaultFetch<Impl>::tick()
821{
822    std::list<unsigned>::iterator threads = (*activeThreads).begin();
823    bool status_change = false;
824
825    wroteToTimeBuffer = false;
826
827    while (threads != (*activeThreads).end()) {
828        unsigned tid = *threads++;
829
830        // Check the signals for each thread to determine the proper status
831        // for each thread.
832        bool updated_status = checkSignalsAndUpdate(tid);
833        status_change =  status_change || updated_status;
834    }
835
836    DPRINTF(Fetch, "Running stage.\n");
837
838    // Reset the number of the instruction we're fetching.
839    numInst = 0;
840
841#if FULL_SYSTEM
842    if (fromCommit->commitInfo[0].interruptPending) {
843        interruptPending = true;
844    }
845
846    if (fromCommit->commitInfo[0].clearInterrupt) {
847        interruptPending = false;
848    }
849#endif
850
851    for (threadFetched = 0; threadFetched < numFetchingThreads;
852         threadFetched++) {
853        // Fetch each of the actively fetching threads.
854        fetch(status_change);
855    }
856
857    // Record number of instructions fetched this cycle for distribution.
858    fetchNisnDist.sample(numInst);
859
860    if (status_change) {
861        // Change the fetch stage status if there was a status change.
862        _status = updateFetchStatus();
863    }
864
865    // If there was activity this cycle, inform the CPU of it.
866    if (wroteToTimeBuffer || cpu->contextSwitch) {
867        DPRINTF(Activity, "Activity this cycle.\n");
868
869        cpu->activityThisCycle();
870    }
871}
872
873template <class Impl>
874bool
875DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
876{
877    // Update the per thread stall statuses.
878    if (fromDecode->decodeBlock[tid]) {
879        stalls[tid].decode = true;
880    }
881
882    if (fromDecode->decodeUnblock[tid]) {
883        assert(stalls[tid].decode);
884        assert(!fromDecode->decodeBlock[tid]);
885        stalls[tid].decode = false;
886    }
887
888    if (fromRename->renameBlock[tid]) {
889        stalls[tid].rename = true;
890    }
891
892    if (fromRename->renameUnblock[tid]) {
893        assert(stalls[tid].rename);
894        assert(!fromRename->renameBlock[tid]);
895        stalls[tid].rename = false;
896    }
897
898    if (fromIEW->iewBlock[tid]) {
899        stalls[tid].iew = true;
900    }
901
902    if (fromIEW->iewUnblock[tid]) {
903        assert(stalls[tid].iew);
904        assert(!fromIEW->iewBlock[tid]);
905        stalls[tid].iew = false;
906    }
907
908    if (fromCommit->commitBlock[tid]) {
909        stalls[tid].commit = true;
910    }
911
912    if (fromCommit->commitUnblock[tid]) {
913        assert(stalls[tid].commit);
914        assert(!fromCommit->commitBlock[tid]);
915        stalls[tid].commit = false;
916    }
917
918    // Check squash signals from commit.
919    if (fromCommit->commitInfo[tid].squash) {
920
921        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
922                "from commit.\n",tid);
923
924#if ISA_HAS_DELAY_SLOT
925    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
926#else
927    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
928#endif
929        // In any case, squash.
930        squash(fromCommit->commitInfo[tid].nextPC,
931               doneSeqNum,
932               fromCommit->commitInfo[tid].squashDelaySlot,
933               tid);
934
935        // Also check if there's a mispredict that happened.
936        if (fromCommit->commitInfo[tid].branchMispredict) {
937            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
938                              fromCommit->commitInfo[tid].nextPC,
939                              fromCommit->commitInfo[tid].branchTaken,
940                              tid);
941        } else {
942            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
943                              tid);
944        }
945
946        return true;
947    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
948        // Update the branch predictor if it wasn't a squashed instruction
949        // that was broadcasted.
950        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
951    }
952
953    // Check ROB squash signals from commit.
954    if (fromCommit->commitInfo[tid].robSquashing) {
955        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
956
957        // Continue to squash.
958        fetchStatus[tid] = Squashing;
959
960        return true;
961    }
962
963    // Check squash signals from decode.
964    if (fromDecode->decodeInfo[tid].squash) {
965        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
966                "from decode.\n",tid);
967
968        // Update the branch predictor.
969        if (fromDecode->decodeInfo[tid].branchMispredict) {
970            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
971                              fromDecode->decodeInfo[tid].nextPC,
972                              fromDecode->decodeInfo[tid].branchTaken,
973                              tid);
974        } else {
975            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
976                              tid);
977        }
978
979        if (fetchStatus[tid] != Squashing) {
980
981#if ISA_HAS_DELAY_SLOT
982            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
983#else
984            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
985#endif
986            // Squash unless we're already squashing
987            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
988                             doneSeqNum,
989                             tid);
990
991            return true;
992        }
993    }
994
995    if (checkStall(tid) &&
996        fetchStatus[tid] != IcacheWaitResponse &&
997        fetchStatus[tid] != IcacheWaitRetry) {
998        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
999
1000        fetchStatus[tid] = Blocked;
1001
1002        return true;
1003    }
1004
1005    if (fetchStatus[tid] == Blocked ||
1006        fetchStatus[tid] == Squashing) {
1007        // Switch status to running if fetch isn't being told to block or
1008        // squash this cycle.
1009        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
1010                tid);
1011
1012        fetchStatus[tid] = Running;
1013
1014        return true;
1015    }
1016
1017    // If we've reached this point, we have not gotten any signals that
1018    // cause fetch to change its status.  Fetch remains the same as before.
1019    return false;
1020}
1021
1022template<class Impl>
1023void
1024DefaultFetch<Impl>::fetch(bool &status_change)
1025{
1026    //////////////////////////////////////////
1027    // Start actual fetch
1028    //////////////////////////////////////////
1029    int tid = getFetchingThread(fetchPolicy);
1030
1031    if (tid == -1 || drainPending) {
1032        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1033
1034        // Breaks looping condition in tick()
1035        threadFetched = numFetchingThreads;
1036        return;
1037    }
1038
1039    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1040
1041    // The current PC.
1042    Addr &fetch_PC = PC[tid];
1043
1044    // Fault code for memory access.
1045    Fault fault = NoFault;
1046
1047    // If returning from the delay of a cache miss, then update the status
1048    // to running, otherwise do the cache access.  Possibly move this up
1049    // to tick() function.
1050    if (fetchStatus[tid] == IcacheAccessComplete) {
1051        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1052                tid);
1053
1054        fetchStatus[tid] = Running;
1055        status_change = true;
1056    } else if (fetchStatus[tid] == Running) {
1057        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1058                "instruction, starting at PC %08p.\n",
1059                tid, fetch_PC);
1060
1061        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1062        if (!fetch_success) {
1063            if (cacheBlocked) {
1064                ++icacheStallCycles;
1065            } else {
1066                ++fetchMiscStallCycles;
1067            }
1068            return;
1069        }
1070    } else {
1071        if (fetchStatus[tid] == Idle) {
1072            ++fetchIdleCycles;
1073            DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
1074        } else if (fetchStatus[tid] == Blocked) {
1075            ++fetchBlockedCycles;
1076            DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
1077        } else if (fetchStatus[tid] == Squashing) {
1078            ++fetchSquashCycles;
1079            DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
1080        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1081            ++icacheStallCycles;
1082            DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid);
1083        }
1084
1085        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1086        // fetch should do nothing.
1087        return;
1088    }
1089
1090    ++fetchCycles;
1091
1092    // If we had a stall due to an icache miss, then return.
1093    if (fetchStatus[tid] == IcacheWaitResponse) {
1094        ++icacheStallCycles;
1095        status_change = true;
1096        return;
1097    }
1098
1099    Addr next_PC = fetch_PC;
1100    Addr next_NPC = next_PC + instSize;
1101    InstSeqNum inst_seq;
1102    MachInst inst;
1103    ExtMachInst ext_inst;
1104    // @todo: Fix this hack.
1105    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1106
1107    if (fault == NoFault) {
1108        // If the read of the first instruction was successful, then grab the
1109        // instructions from the rest of the cache line and put them into the
1110        // queue heading to decode.
1111
1112        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1113                "decode.\n",tid);
1114
1115        // Need to keep track of whether or not a predicted branch
1116        // ended this fetch block.
1117        bool predicted_branch = false;
1118
1119        // Need to keep track of whether or not a delay slot
1120        // instruction has been fetched
1121
1122        for (;
1123             offset < cacheBlkSize &&
1124                 numInst < fetchWidth &&
1125                 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1126             ++numInst) {
1127
1128            // Get a sequence number.
1129            inst_seq = cpu->getAndIncrementInstSeq();
1130
1131            // Make sure this is a valid index.
1132            assert(offset <= cacheBlkSize - instSize);
1133
1134            // Get the instruction from the array of the cache line.
1135            inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1136                        (&cacheData[tid][offset]));
1137
1138#if THE_ISA == ALPHA_ISA
1139            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1140#elif THE_ISA == SPARC_ISA
1141            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1142#elif THE_ISA == MIPS_ISA
1143            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
1144#endif
1145
1146            // Create a new DynInst from the instruction fetched.
1147            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1148                                                 next_PC,
1149                                                 inst_seq, cpu);
1150            instruction->setTid(tid);
1151
1152            instruction->setASID(tid);
1153
1154            instruction->setThreadState(cpu->thread[tid]);
1155
1156            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1157                    "[sn:%lli]\n",
1158                    tid, instruction->readPC(), inst_seq);
1159
1160            DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst);
1161
1162            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1163                    tid, instruction->staticInst->disassemble(fetch_PC));
1164
1165            instruction->traceData =
1166                Trace::getInstRecord(curTick, cpu->tcBase(tid),
1167                                     instruction->staticInst,
1168                                     instruction->readPC());
1169
1170            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1171                                                     next_NPC);
1172
1173            // Add instruction to the CPU's list of instructions.
1174            instruction->setInstListIt(cpu->addInst(instruction));
1175
1176            // Write the instruction to the first slot in the queue
1177            // that heads to decode.
1178            toDecode->insts[numInst] = instruction;
1179
1180            toDecode->size++;
1181
1182            // Increment stat of fetched instructions.
1183            ++fetchedInsts;
1184
1185            // Move to the next instruction, unless we have a branch.
1186            fetch_PC = next_PC;
1187
1188            if (instruction->isQuiesce()) {
1189                DPRINTF(Fetch, "Quiesce instruction encountered, halting fetch!",
1190                        curTick);
1191                fetchStatus[tid] = QuiescePending;
1192                ++numInst;
1193                status_change = true;
1194                break;
1195            }
1196
1197            offset += instSize;
1198
1199#if ISA_HAS_DELAY_SLOT
1200            if (predicted_branch) {
1201                delaySlotInfo[tid].branchSeqNum = inst_seq;
1202
1203                DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1204                        tid, inst_seq);
1205                continue;
1206            } else if (delaySlotInfo[tid].numInsts > 0) {
1207                --delaySlotInfo[tid].numInsts;
1208
1209                // It's OK to set PC to target of branch
1210                if (delaySlotInfo[tid].numInsts == 0) {
1211                    delaySlotInfo[tid].targetReady = true;
1212
1213                    // Break the looping condition
1214                    predicted_branch = true;
1215                }
1216
1217                DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1218                        " process.\n", tid, delaySlotInfo[tid].numInsts);
1219            }
1220#endif
1221        }
1222
1223        if (offset >= cacheBlkSize) {
1224            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1225                    "block.\n", tid);
1226        } else if (numInst >= fetchWidth) {
1227            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1228                    "for this cycle.\n", tid);
1229        } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1230            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1231                    "instruction encountered.\n", tid);
1232        }
1233    }
1234
1235    if (numInst > 0) {
1236        wroteToTimeBuffer = true;
1237    }
1238
1239    // Now that fetching is completed, update the PC to signify what the next
1240    // cycle will be.
1241    if (fault == NoFault) {
1242#if ISA_HAS_DELAY_SLOT
1243        if (delaySlotInfo[tid].targetReady &&
1244            delaySlotInfo[tid].numInsts == 0) {
1245            // Set PC to target
1246            PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1247            nextPC[tid] = next_PC + instSize;        //next_NPC
1248            nextNPC[tid] = next_PC + (2 * instSize);
1249
1250            delaySlotInfo[tid].targetReady = false;
1251        } else {
1252            PC[tid] = next_PC;
1253            nextPC[tid] = next_NPC;
1254            nextNPC[tid] = next_NPC + instSize;
1255        }
1256
1257        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1258#else
1259        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1260        PC[tid] = next_PC;
1261        nextPC[tid] = next_PC + instSize;
1262#endif
1263    } else {
1264        // We shouldn't be in an icache miss and also have a fault (an ITB
1265        // miss)
1266        if (fetchStatus[tid] == IcacheWaitResponse) {
1267            panic("Fetch should have exited prior to this!");
1268        }
1269
1270        // Send the fault to commit.  This thread will not do anything
1271        // until commit handles the fault.  The only other way it can
1272        // wake up is if a squash comes along and changes the PC.
1273#if FULL_SYSTEM
1274        assert(numInst != fetchWidth);
1275        // Get a sequence number.
1276        inst_seq = cpu->getAndIncrementInstSeq();
1277        // We will use a nop in order to carry the fault.
1278        ext_inst = TheISA::NoopMachInst;
1279
1280        // Create a new DynInst from the dummy nop.
1281        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1282                                             next_PC,
1283                                             inst_seq, cpu);
1284        instruction->setPredTarg(next_PC + instSize);
1285        instruction->setTid(tid);
1286
1287        instruction->setASID(tid);
1288
1289        instruction->setThreadState(cpu->thread[tid]);
1290
1291        instruction->traceData = NULL;
1292
1293        instruction->setInstListIt(cpu->addInst(instruction));
1294
1295        instruction->fault = fault;
1296
1297        toDecode->insts[numInst] = instruction;
1298        toDecode->size++;
1299
1300        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1301
1302        fetchStatus[tid] = TrapPending;
1303        status_change = true;
1304#else // !FULL_SYSTEM
1305        fetchStatus[tid] = TrapPending;
1306        status_change = true;
1307
1308#endif // FULL_SYSTEM
1309        DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
1310                tid, fault->name(), PC[tid]);
1311    }
1312}
1313
1314template<class Impl>
1315void
1316DefaultFetch<Impl>::recvRetry()
1317{
1318    if (retryPkt != NULL) {
1319        assert(cacheBlocked);
1320        assert(retryTid != -1);
1321        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1322
1323        if (icachePort->sendTiming(retryPkt)) {
1324            fetchStatus[retryTid] = IcacheWaitResponse;
1325            retryPkt = NULL;
1326            retryTid = -1;
1327            cacheBlocked = false;
1328        }
1329    } else {
1330        assert(retryTid == -1);
1331        // Access has been squashed since it was sent out.  Just clear
1332        // the cache being blocked.
1333        cacheBlocked = false;
1334    }
1335}
1336
1337///////////////////////////////////////
1338//                                   //
1339//  SMT FETCH POLICY MAINTAINED HERE //
1340//                                   //
1341///////////////////////////////////////
1342template<class Impl>
1343int
1344DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1345{
1346    if (numThreads > 1) {
1347        switch (fetch_priority) {
1348
1349          case SingleThread:
1350            return 0;
1351
1352          case RoundRobin:
1353            return roundRobin();
1354
1355          case IQ:
1356            return iqCount();
1357
1358          case LSQ:
1359            return lsqCount();
1360
1361          case Branch:
1362            return branchCount();
1363
1364          default:
1365            return -1;
1366        }
1367    } else {
1368        int tid = *((*activeThreads).begin());
1369
1370        if (fetchStatus[tid] == Running ||
1371            fetchStatus[tid] == IcacheAccessComplete ||
1372            fetchStatus[tid] == Idle) {
1373            return tid;
1374        } else {
1375            return -1;
1376        }
1377    }
1378
1379}
1380
1381
1382template<class Impl>
1383int
1384DefaultFetch<Impl>::roundRobin()
1385{
1386    std::list<unsigned>::iterator pri_iter = priorityList.begin();
1387    std::list<unsigned>::iterator end      = priorityList.end();
1388
1389    int high_pri;
1390
1391    while (pri_iter != end) {
1392        high_pri = *pri_iter;
1393
1394        assert(high_pri <= numThreads);
1395
1396        if (fetchStatus[high_pri] == Running ||
1397            fetchStatus[high_pri] == IcacheAccessComplete ||
1398            fetchStatus[high_pri] == Idle) {
1399
1400            priorityList.erase(pri_iter);
1401            priorityList.push_back(high_pri);
1402
1403            return high_pri;
1404        }
1405
1406        pri_iter++;
1407    }
1408
1409    return -1;
1410}
1411
1412template<class Impl>
1413int
1414DefaultFetch<Impl>::iqCount()
1415{
1416    std::priority_queue<unsigned> PQ;
1417
1418    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1419
1420    while (threads != (*activeThreads).end()) {
1421        unsigned tid = *threads++;
1422
1423        PQ.push(fromIEW->iewInfo[tid].iqCount);
1424    }
1425
1426    while (!PQ.empty()) {
1427
1428        unsigned high_pri = PQ.top();
1429
1430        if (fetchStatus[high_pri] == Running ||
1431            fetchStatus[high_pri] == IcacheAccessComplete ||
1432            fetchStatus[high_pri] == Idle)
1433            return high_pri;
1434        else
1435            PQ.pop();
1436
1437    }
1438
1439    return -1;
1440}
1441
1442template<class Impl>
1443int
1444DefaultFetch<Impl>::lsqCount()
1445{
1446    std::priority_queue<unsigned> PQ;
1447
1448
1449    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1450
1451    while (threads != (*activeThreads).end()) {
1452        unsigned tid = *threads++;
1453
1454        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1455    }
1456
1457    while (!PQ.empty()) {
1458
1459        unsigned high_pri = PQ.top();
1460
1461        if (fetchStatus[high_pri] == Running ||
1462            fetchStatus[high_pri] == IcacheAccessComplete ||
1463            fetchStatus[high_pri] == Idle)
1464            return high_pri;
1465        else
1466            PQ.pop();
1467
1468    }
1469
1470    return -1;
1471}
1472
1473template<class Impl>
1474int
1475DefaultFetch<Impl>::branchCount()
1476{
1477    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1478    panic("Branch Count Fetch policy unimplemented\n");
1479    return *threads;
1480}
1481