fetch_impl.hh revision 3172:2c84db071850 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54template<class Impl>
55Tick
56DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
57{
58    panic("DefaultFetch doesn't expect recvAtomic callback!");
59    return curTick;
60}
61
62template<class Impl>
63void
64DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
65{
66    panic("DefaultFetch doesn't expect recvFunctional callback!");
67}
68
69template<class Impl>
70void
71DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
72{
73    if (status == RangeChange)
74        return;
75
76    panic("DefaultFetch doesn't expect recvStatusChange callback!");
77}
78
79template<class Impl>
80bool
81DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
82{
83    fetch->processCacheCompletion(pkt);
84    return true;
85}
86
87template<class Impl>
88void
89DefaultFetch<Impl>::IcachePort::recvRetry()
90{
91    fetch->recvRetry();
92}
93
94template<class Impl>
95DefaultFetch<Impl>::DefaultFetch(Params *params)
96    : mem(params->mem),
97      branchPred(params),
98      decodeToFetchDelay(params->decodeToFetchDelay),
99      renameToFetchDelay(params->renameToFetchDelay),
100      iewToFetchDelay(params->iewToFetchDelay),
101      commitToFetchDelay(params->commitToFetchDelay),
102      fetchWidth(params->fetchWidth),
103      cacheBlocked(false),
104      retryPkt(NULL),
105      retryTid(-1),
106      numThreads(params->numberOfThreads),
107      numFetchingThreads(params->smtNumFetchingThreads),
108      interruptPending(false),
109      drainPending(false),
110      switchedOut(false)
111{
112    if (numThreads > Impl::MaxThreads)
113        fatal("numThreads is not a valid value\n");
114
115    // Set fetch stage's status to inactive.
116    _status = Inactive;
117
118    std::string policy = params->smtFetchPolicy;
119
120    // Convert string to lowercase
121    std::transform(policy.begin(), policy.end(), policy.begin(),
122                   (int(*)(int)) tolower);
123
124    // Figure out fetch policy
125    if (policy == "singlethread") {
126        fetchPolicy = SingleThread;
127        if (numThreads > 1)
128            panic("Invalid Fetch Policy for a SMT workload.");
129    } else if (policy == "roundrobin") {
130        fetchPolicy = RoundRobin;
131        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
132    } else if (policy == "branch") {
133        fetchPolicy = Branch;
134        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
135    } else if (policy == "iqcount") {
136        fetchPolicy = IQ;
137        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
138    } else if (policy == "lsqcount") {
139        fetchPolicy = LSQ;
140        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
141    } else {
142        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
143              " RoundRobin,LSQcount,IQcount}\n");
144    }
145
146    // Size of cache block.
147    cacheBlkSize = 64;
148
149    // Create mask to get rid of offset bits.
150    cacheBlkMask = (cacheBlkSize - 1);
151
152    for (int tid=0; tid < numThreads; tid++) {
153
154        fetchStatus[tid] = Running;
155
156        priorityList.push_back(tid);
157
158        memReq[tid] = NULL;
159
160        // Create space to store a cache line.
161        cacheData[tid] = new uint8_t[cacheBlkSize];
162        cacheDataPC[tid] = 0;
163        cacheDataValid[tid] = false;
164
165        delaySlotInfo[tid].branchSeqNum = -1;
166        delaySlotInfo[tid].numInsts = 0;
167        delaySlotInfo[tid].targetAddr = 0;
168        delaySlotInfo[tid].targetReady = false;
169
170        stalls[tid].decode = false;
171        stalls[tid].rename = false;
172        stalls[tid].iew = false;
173        stalls[tid].commit = false;
174    }
175
176    // Get the size of an instruction.
177    instSize = sizeof(TheISA::MachInst);
178}
179
180template <class Impl>
181std::string
182DefaultFetch<Impl>::name() const
183{
184    return cpu->name() + ".fetch";
185}
186
187template <class Impl>
188void
189DefaultFetch<Impl>::regStats()
190{
191    icacheStallCycles
192        .name(name() + ".icacheStallCycles")
193        .desc("Number of cycles fetch is stalled on an Icache miss")
194        .prereq(icacheStallCycles);
195
196    fetchedInsts
197        .name(name() + ".Insts")
198        .desc("Number of instructions fetch has processed")
199        .prereq(fetchedInsts);
200
201    fetchedBranches
202        .name(name() + ".Branches")
203        .desc("Number of branches that fetch encountered")
204        .prereq(fetchedBranches);
205
206    predictedBranches
207        .name(name() + ".predictedBranches")
208        .desc("Number of branches that fetch has predicted taken")
209        .prereq(predictedBranches);
210
211    fetchCycles
212        .name(name() + ".Cycles")
213        .desc("Number of cycles fetch has run and was not squashing or"
214              " blocked")
215        .prereq(fetchCycles);
216
217    fetchSquashCycles
218        .name(name() + ".SquashCycles")
219        .desc("Number of cycles fetch has spent squashing")
220        .prereq(fetchSquashCycles);
221
222    fetchIdleCycles
223        .name(name() + ".IdleCycles")
224        .desc("Number of cycles fetch was idle")
225        .prereq(fetchIdleCycles);
226
227    fetchBlockedCycles
228        .name(name() + ".BlockedCycles")
229        .desc("Number of cycles fetch has spent blocked")
230        .prereq(fetchBlockedCycles);
231
232    fetchedCacheLines
233        .name(name() + ".CacheLines")
234        .desc("Number of cache lines fetched")
235        .prereq(fetchedCacheLines);
236
237    fetchMiscStallCycles
238        .name(name() + ".MiscStallCycles")
239        .desc("Number of cycles fetch has spent waiting on interrupts, or "
240              "bad addresses, or out of MSHRs")
241        .prereq(fetchMiscStallCycles);
242
243    fetchIcacheSquashes
244        .name(name() + ".IcacheSquashes")
245        .desc("Number of outstanding Icache misses that were squashed")
246        .prereq(fetchIcacheSquashes);
247
248    fetchNisnDist
249        .init(/* base value */ 0,
250              /* last value */ fetchWidth,
251              /* bucket size */ 1)
252        .name(name() + ".rateDist")
253        .desc("Number of instructions fetched each cycle (Total)")
254        .flags(Stats::pdf);
255
256    idleRate
257        .name(name() + ".idleRate")
258        .desc("Percent of cycles fetch was idle")
259        .prereq(idleRate);
260    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
261
262    branchRate
263        .name(name() + ".branchRate")
264        .desc("Number of branch fetches per cycle")
265        .flags(Stats::total);
266    branchRate = fetchedBranches / cpu->numCycles;
267
268    fetchRate
269        .name(name() + ".rate")
270        .desc("Number of inst fetches per cycle")
271        .flags(Stats::total);
272    fetchRate = fetchedInsts / cpu->numCycles;
273
274    branchPred.regStats();
275}
276
277template<class Impl>
278void
279DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
280{
281    DPRINTF(Fetch, "Setting the CPU pointer.\n");
282    cpu = cpu_ptr;
283
284    // Name is finally available, so create the port.
285    icachePort = new IcachePort(this);
286
287#if USE_CHECKER
288    if (cpu->checker) {
289        cpu->checker->setIcachePort(icachePort);
290    }
291#endif
292
293    // Schedule fetch to get the correct PC from the CPU
294    // scheduleFetchStartupEvent(1);
295
296    // Fetch needs to start fetching instructions at the very beginning,
297    // so it must start up in active state.
298    switchToActive();
299}
300
301template<class Impl>
302void
303DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
304{
305    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
306    timeBuffer = time_buffer;
307
308    // Create wires to get information from proper places in time buffer.
309    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
310    fromRename = timeBuffer->getWire(-renameToFetchDelay);
311    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
312    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
313}
314
315template<class Impl>
316void
317DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
318{
319    DPRINTF(Fetch, "Setting active threads list pointer.\n");
320    activeThreads = at_ptr;
321}
322
323template<class Impl>
324void
325DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
326{
327    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
328    fetchQueue = fq_ptr;
329
330    // Create wire to write information to proper place in fetch queue.
331    toDecode = fetchQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultFetch<Impl>::initStage()
337{
338    // Setup PC and nextPC with initial state.
339    for (int tid = 0; tid < numThreads; tid++) {
340        PC[tid] = cpu->readPC(tid);
341        nextPC[tid] = cpu->readNextPC(tid);
342#if ISA_HAS_DELAY_SLOT
343        nextNPC[tid] = cpu->readNextNPC(tid);
344#endif
345    }
346}
347
348template<class Impl>
349void
350DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
351{
352    unsigned tid = pkt->req->getThreadNum();
353
354    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
355
356    // Only change the status if it's still waiting on the icache access
357    // to return.
358    if (fetchStatus[tid] != IcacheWaitResponse ||
359        pkt->req != memReq[tid] ||
360        isSwitchedOut()) {
361        ++fetchIcacheSquashes;
362        delete pkt->req;
363        delete pkt;
364        return;
365    }
366
367    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
368    cacheDataValid[tid] = true;
369
370    if (!drainPending) {
371        // Wake up the CPU (if it went to sleep and was waiting on
372        // this completion event).
373        cpu->wakeCPU();
374
375        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
376                tid);
377
378        switchToActive();
379    }
380
381    // Only switch to IcacheAccessComplete if we're not stalled as well.
382    if (checkStall(tid)) {
383        fetchStatus[tid] = Blocked;
384    } else {
385        fetchStatus[tid] = IcacheAccessComplete;
386    }
387
388    // Reset the mem req to NULL.
389    delete pkt->req;
390    delete pkt;
391    memReq[tid] = NULL;
392}
393
394template <class Impl>
395bool
396DefaultFetch<Impl>::drain()
397{
398    // Fetch is ready to drain at any time.
399    cpu->signalDrained();
400    drainPending = true;
401    return true;
402}
403
404template <class Impl>
405void
406DefaultFetch<Impl>::resume()
407{
408    drainPending = false;
409}
410
411template <class Impl>
412void
413DefaultFetch<Impl>::switchOut()
414{
415    switchedOut = true;
416    // Branch predictor needs to have its state cleared.
417    branchPred.switchOut();
418}
419
420template <class Impl>
421void
422DefaultFetch<Impl>::takeOverFrom()
423{
424    // Reset all state
425    for (int i = 0; i < Impl::MaxThreads; ++i) {
426        stalls[i].decode = 0;
427        stalls[i].rename = 0;
428        stalls[i].iew = 0;
429        stalls[i].commit = 0;
430        PC[i] = cpu->readPC(i);
431        nextPC[i] = cpu->readNextPC(i);
432#if ISA_HAS_DELAY_SLOT
433        nextNPC[i] = cpu->readNextNPC(i);
434        delaySlotInfo[i].branchSeqNum = -1;
435        delaySlotInfo[i].numInsts = 0;
436        delaySlotInfo[i].targetAddr = 0;
437        delaySlotInfo[i].targetReady = false;
438#endif
439        fetchStatus[i] = Running;
440    }
441    numInst = 0;
442    wroteToTimeBuffer = false;
443    _status = Inactive;
444    switchedOut = false;
445    interruptPending = false;
446    branchPred.takeOverFrom();
447}
448
449template <class Impl>
450void
451DefaultFetch<Impl>::wakeFromQuiesce()
452{
453    DPRINTF(Fetch, "Waking up from quiesce\n");
454    // Hopefully this is safe
455    // @todo: Allow other threads to wake from quiesce.
456    fetchStatus[0] = Running;
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToActive()
462{
463    if (_status == Inactive) {
464        DPRINTF(Activity, "Activating stage.\n");
465
466        cpu->activateStage(O3CPU::FetchIdx);
467
468        _status = Active;
469    }
470}
471
472template <class Impl>
473inline void
474DefaultFetch<Impl>::switchToInactive()
475{
476    if (_status == Active) {
477        DPRINTF(Activity, "Deactivating stage.\n");
478
479        cpu->deactivateStage(O3CPU::FetchIdx);
480
481        _status = Inactive;
482    }
483}
484
485template <class Impl>
486bool
487DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
488                                          Addr &next_NPC)
489{
490    // Do branch prediction check here.
491    // A bit of a misnomer...next_PC is actually the current PC until
492    // this function updates it.
493    bool predict_taken;
494
495    if (!inst->isControl()) {
496#if ISA_HAS_DELAY_SLOT
497        Addr cur_PC = next_PC;
498        next_PC  = cur_PC + instSize;      //next_NPC;
499        next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
500        inst->setPredTarg(next_NPC);
501#else
502        next_PC = next_PC + instSize;
503        inst->setPredTarg(next_PC);
504#endif
505        return false;
506    }
507
508    int tid = inst->threadNumber;
509#if ISA_HAS_DELAY_SLOT
510    Addr pred_PC = next_PC;
511    predict_taken = branchPred.predict(inst, pred_PC, tid);
512
513    if (predict_taken) {
514        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be true.\n", tid);
515    } else {
516        DPRINTF(Fetch, "[tid:%i]: Branch predicted to be false.\n", tid);
517    }
518
519    if (predict_taken) {
520        next_PC = next_NPC;
521        next_NPC = pred_PC;
522
523        // Update delay slot info
524        ++delaySlotInfo[tid].numInsts;
525        delaySlotInfo[tid].targetAddr = pred_PC;
526        DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) to process.\n", tid,
527                delaySlotInfo[tid].numInsts);
528    } else { // !predict_taken
529        if (inst->isCondDelaySlot()) {
530            next_PC = pred_PC;
531            // The delay slot is skipped here if there is on
532            // prediction
533        } else {
534            next_PC = next_NPC;
535            // No need to declare a delay slot here since
536            // there is no for the pred. target to jump
537        }
538
539        next_NPC = next_NPC + instSize;
540    }
541#else
542    predict_taken = branchPred.predict(inst, next_PC, tid);
543#endif
544
545    ++fetchedBranches;
546
547    if (predict_taken) {
548        ++predictedBranches;
549    }
550
551    return predict_taken;
552}
553
554template <class Impl>
555bool
556DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
557{
558    Fault fault = NoFault;
559
560#if FULL_SYSTEM
561    // Flag to say whether or not address is physical addr.
562    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
563#else
564    unsigned flags = 0;
565#endif // FULL_SYSTEM
566
567    if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
568        // Hold off fetch from getting new instructions when:
569        // Cache is blocked, or
570        // while an interrupt is pending and we're not in PAL mode, or
571        // fetch is switched out.
572        return false;
573    }
574
575    // Align the fetch PC so it's at the start of a cache block.
576    fetch_PC = icacheBlockAlignPC(fetch_PC);
577
578    // If we've already got the block, no need to try to fetch it again.
579    if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) {
580        return true;
581    }
582
583    // Setup the memReq to do a read of the first instruction's address.
584    // Set the appropriate read size and flags as well.
585    // Build request here.
586    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
587                                     fetch_PC, cpu->readCpuId(), tid);
588
589    memReq[tid] = mem_req;
590
591    // Translate the instruction request.
592    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
593
594    // In the case of faults, the fetch stage may need to stall and wait
595    // for the ITB miss to be handled.
596
597    // If translation was successful, attempt to read the first
598    // instruction.
599    if (fault == NoFault) {
600#if 0
601        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
602            memReq[tid]->isUncacheable()) {
603            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
604                    "misspeculating path)!",
605                    memReq[tid]->paddr);
606            ret_fault = TheISA::genMachineCheckFault();
607            return false;
608        }
609#endif
610
611        // Build packet here.
612        PacketPtr data_pkt = new Packet(mem_req,
613                                        Packet::ReadReq, Packet::Broadcast);
614        data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
615
616        cacheDataPC[tid] = fetch_PC;
617        cacheDataValid[tid] = false;
618
619        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
620
621        fetchedCacheLines++;
622
623        // Now do the timing access to see whether or not the instruction
624        // exists within the cache.
625        if (!icachePort->sendTiming(data_pkt)) {
626            assert(retryPkt == NULL);
627            assert(retryTid == -1);
628            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
629            fetchStatus[tid] = IcacheWaitRetry;
630            retryPkt = data_pkt;
631            retryTid = tid;
632            cacheBlocked = true;
633            return false;
634        }
635
636        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
637
638        lastIcacheStall[tid] = curTick;
639
640        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
641                "response.\n", tid);
642
643        fetchStatus[tid] = IcacheWaitResponse;
644    } else {
645        delete mem_req;
646        memReq[tid] = NULL;
647    }
648
649    ret_fault = fault;
650    return true;
651}
652
653template <class Impl>
654inline void
655DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
656{
657    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
658            tid, new_PC);
659
660    PC[tid] = new_PC;
661    nextPC[tid] = new_PC + instSize;
662    nextNPC[tid] = new_PC + (2 * instSize);
663
664    // Clear the icache miss if it's outstanding.
665    if (fetchStatus[tid] == IcacheWaitResponse) {
666        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
667                tid);
668        memReq[tid] = NULL;
669    }
670
671    // Get rid of the retrying packet if it was from this thread.
672    if (retryTid == tid) {
673        assert(cacheBlocked);
674        cacheBlocked = false;
675        retryTid = -1;
676        delete retryPkt->req;
677        delete retryPkt;
678        retryPkt = NULL;
679    }
680
681    fetchStatus[tid] = Squashing;
682
683    ++fetchSquashCycles;
684}
685
686template<class Impl>
687void
688DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
689                                     const InstSeqNum &seq_num,
690                                     unsigned tid)
691{
692    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
693
694    doSquash(new_PC, tid);
695
696#if ISA_HAS_DELAY_SLOT
697    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
698        delaySlotInfo[tid].numInsts = 0;
699        delaySlotInfo[tid].targetAddr = 0;
700        delaySlotInfo[tid].targetReady = false;
701    }
702#endif
703
704    // Tell the CPU to remove any instructions that are in flight between
705    // fetch and decode.
706    cpu->removeInstsUntil(seq_num, tid);
707}
708
709template<class Impl>
710bool
711DefaultFetch<Impl>::checkStall(unsigned tid) const
712{
713    bool ret_val = false;
714
715    if (cpu->contextSwitch) {
716        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
717        ret_val = true;
718    } else if (stalls[tid].decode) {
719        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
720        ret_val = true;
721    } else if (stalls[tid].rename) {
722        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
723        ret_val = true;
724    } else if (stalls[tid].iew) {
725        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
726        ret_val = true;
727    } else if (stalls[tid].commit) {
728        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
729        ret_val = true;
730    }
731
732    return ret_val;
733}
734
735template<class Impl>
736typename DefaultFetch<Impl>::FetchStatus
737DefaultFetch<Impl>::updateFetchStatus()
738{
739    //Check Running
740    std::list<unsigned>::iterator threads = (*activeThreads).begin();
741
742    while (threads != (*activeThreads).end()) {
743
744        unsigned tid = *threads++;
745
746        if (fetchStatus[tid] == Running ||
747            fetchStatus[tid] == Squashing ||
748            fetchStatus[tid] == IcacheAccessComplete) {
749
750            if (_status == Inactive) {
751                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
752
753                if (fetchStatus[tid] == IcacheAccessComplete) {
754                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
755                            "completion\n",tid);
756                }
757
758                cpu->activateStage(O3CPU::FetchIdx);
759            }
760
761            return Active;
762        }
763    }
764
765    // Stage is switching from active to inactive, notify CPU of it.
766    if (_status == Active) {
767        DPRINTF(Activity, "Deactivating stage.\n");
768
769        cpu->deactivateStage(O3CPU::FetchIdx);
770    }
771
772    return Inactive;
773}
774
775template <class Impl>
776void
777DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
778                           bool squash_delay_slot, unsigned tid)
779{
780    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
781
782    doSquash(new_PC, tid);
783
784#if ISA_HAS_DELAY_SLOT
785    if (seq_num <=  delaySlotInfo[tid].branchSeqNum) {
786        delaySlotInfo[tid].numInsts = 0;
787        delaySlotInfo[tid].targetAddr = 0;
788        delaySlotInfo[tid].targetReady = false;
789    }
790
791    // Tell the CPU to remove any instructions that are not in the ROB.
792    cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
793#else
794    // Tell the CPU to remove any instructions that are not in the ROB.
795    cpu->removeInstsNotInROB(tid, true, 0);
796#endif
797}
798
799template <class Impl>
800void
801DefaultFetch<Impl>::tick()
802{
803    std::list<unsigned>::iterator threads = (*activeThreads).begin();
804    bool status_change = false;
805
806    wroteToTimeBuffer = false;
807
808    while (threads != (*activeThreads).end()) {
809        unsigned tid = *threads++;
810
811        // Check the signals for each thread to determine the proper status
812        // for each thread.
813        bool updated_status = checkSignalsAndUpdate(tid);
814        status_change =  status_change || updated_status;
815    }
816
817    DPRINTF(Fetch, "Running stage.\n");
818
819    // Reset the number of the instruction we're fetching.
820    numInst = 0;
821
822#if FULL_SYSTEM
823    if (fromCommit->commitInfo[0].interruptPending) {
824        interruptPending = true;
825    }
826
827    if (fromCommit->commitInfo[0].clearInterrupt) {
828        interruptPending = false;
829    }
830#endif
831
832    for (threadFetched = 0; threadFetched < numFetchingThreads;
833         threadFetched++) {
834        // Fetch each of the actively fetching threads.
835        fetch(status_change);
836    }
837
838    // Record number of instructions fetched this cycle for distribution.
839    fetchNisnDist.sample(numInst);
840
841    if (status_change) {
842        // Change the fetch stage status if there was a status change.
843        _status = updateFetchStatus();
844    }
845
846    // If there was activity this cycle, inform the CPU of it.
847    if (wroteToTimeBuffer || cpu->contextSwitch) {
848        DPRINTF(Activity, "Activity this cycle.\n");
849
850        cpu->activityThisCycle();
851    }
852}
853
854template <class Impl>
855bool
856DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
857{
858    // Update the per thread stall statuses.
859    if (fromDecode->decodeBlock[tid]) {
860        stalls[tid].decode = true;
861    }
862
863    if (fromDecode->decodeUnblock[tid]) {
864        assert(stalls[tid].decode);
865        assert(!fromDecode->decodeBlock[tid]);
866        stalls[tid].decode = false;
867    }
868
869    if (fromRename->renameBlock[tid]) {
870        stalls[tid].rename = true;
871    }
872
873    if (fromRename->renameUnblock[tid]) {
874        assert(stalls[tid].rename);
875        assert(!fromRename->renameBlock[tid]);
876        stalls[tid].rename = false;
877    }
878
879    if (fromIEW->iewBlock[tid]) {
880        stalls[tid].iew = true;
881    }
882
883    if (fromIEW->iewUnblock[tid]) {
884        assert(stalls[tid].iew);
885        assert(!fromIEW->iewBlock[tid]);
886        stalls[tid].iew = false;
887    }
888
889    if (fromCommit->commitBlock[tid]) {
890        stalls[tid].commit = true;
891    }
892
893    if (fromCommit->commitUnblock[tid]) {
894        assert(stalls[tid].commit);
895        assert(!fromCommit->commitBlock[tid]);
896        stalls[tid].commit = false;
897    }
898
899    // Check squash signals from commit.
900    if (fromCommit->commitInfo[tid].squash) {
901
902        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
903                "from commit.\n",tid);
904
905#if ISA_HAS_DELAY_SLOT
906    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
907#else
908    InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
909#endif
910        // In any case, squash.
911        squash(fromCommit->commitInfo[tid].nextPC,
912               doneSeqNum,
913               fromCommit->commitInfo[tid].squashDelaySlot,
914               tid);
915
916        // Also check if there's a mispredict that happened.
917        if (fromCommit->commitInfo[tid].branchMispredict) {
918            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
919                              fromCommit->commitInfo[tid].nextPC,
920                              fromCommit->commitInfo[tid].branchTaken,
921                              tid);
922        } else {
923            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
924                              tid);
925        }
926
927        return true;
928    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
929        // Update the branch predictor if it wasn't a squashed instruction
930        // that was broadcasted.
931        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
932    }
933
934    // Check ROB squash signals from commit.
935    if (fromCommit->commitInfo[tid].robSquashing) {
936        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
937
938        // Continue to squash.
939        fetchStatus[tid] = Squashing;
940
941        return true;
942    }
943
944    // Check squash signals from decode.
945    if (fromDecode->decodeInfo[tid].squash) {
946        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
947                "from decode.\n",tid);
948
949        // Update the branch predictor.
950        if (fromDecode->decodeInfo[tid].branchMispredict) {
951            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
952                              fromDecode->decodeInfo[tid].nextPC,
953                              fromDecode->decodeInfo[tid].branchTaken,
954                              tid);
955        } else {
956            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
957                              tid);
958        }
959
960        if (fetchStatus[tid] != Squashing) {
961
962#if ISA_HAS_DELAY_SLOT
963            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
964#else
965            InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
966#endif
967            // Squash unless we're already squashing
968            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
969                             doneSeqNum,
970                             tid);
971
972            return true;
973        }
974    }
975
976    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
977        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
978
979        fetchStatus[tid] = Blocked;
980
981        return true;
982    }
983
984    if (fetchStatus[tid] == Blocked ||
985        fetchStatus[tid] == Squashing) {
986        // Switch status to running if fetch isn't being told to block or
987        // squash this cycle.
988        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
989                tid);
990
991        fetchStatus[tid] = Running;
992
993        return true;
994    }
995
996    // If we've reached this point, we have not gotten any signals that
997    // cause fetch to change its status.  Fetch remains the same as before.
998    return false;
999}
1000
1001template<class Impl>
1002void
1003DefaultFetch<Impl>::fetch(bool &status_change)
1004{
1005    //////////////////////////////////////////
1006    // Start actual fetch
1007    //////////////////////////////////////////
1008    int tid = getFetchingThread(fetchPolicy);
1009
1010    if (tid == -1 || drainPending) {
1011        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1012
1013        // Breaks looping condition in tick()
1014        threadFetched = numFetchingThreads;
1015        return;
1016    }
1017
1018    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1019
1020    // The current PC.
1021    Addr &fetch_PC = PC[tid];
1022
1023    // Fault code for memory access.
1024    Fault fault = NoFault;
1025
1026    // If returning from the delay of a cache miss, then update the status
1027    // to running, otherwise do the cache access.  Possibly move this up
1028    // to tick() function.
1029    if (fetchStatus[tid] == IcacheAccessComplete) {
1030        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
1031                tid);
1032
1033        fetchStatus[tid] = Running;
1034        status_change = true;
1035    } else if (fetchStatus[tid] == Running) {
1036        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
1037                "instruction, starting at PC %08p.\n",
1038                tid, fetch_PC);
1039
1040        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
1041        if (!fetch_success) {
1042            if (cacheBlocked) {
1043                ++icacheStallCycles;
1044            } else {
1045                ++fetchMiscStallCycles;
1046            }
1047            return;
1048        }
1049    } else {
1050        if (fetchStatus[tid] == Idle) {
1051            ++fetchIdleCycles;
1052        } else if (fetchStatus[tid] == Blocked) {
1053            ++fetchBlockedCycles;
1054        } else if (fetchStatus[tid] == Squashing) {
1055            ++fetchSquashCycles;
1056        } else if (fetchStatus[tid] == IcacheWaitResponse) {
1057            ++icacheStallCycles;
1058        }
1059
1060        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
1061        // fetch should do nothing.
1062        return;
1063    }
1064
1065    ++fetchCycles;
1066
1067    // If we had a stall due to an icache miss, then return.
1068    if (fetchStatus[tid] == IcacheWaitResponse) {
1069        ++icacheStallCycles;
1070        status_change = true;
1071        return;
1072    }
1073
1074    Addr next_PC = fetch_PC;
1075    Addr next_NPC = next_PC + instSize;
1076    InstSeqNum inst_seq;
1077    MachInst inst;
1078    ExtMachInst ext_inst;
1079    // @todo: Fix this hack.
1080    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
1081
1082    if (fault == NoFault) {
1083        // If the read of the first instruction was successful, then grab the
1084        // instructions from the rest of the cache line and put them into the
1085        // queue heading to decode.
1086
1087        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
1088                "decode.\n",tid);
1089
1090        // Need to keep track of whether or not a predicted branch
1091        // ended this fetch block.
1092        bool predicted_branch = false;
1093
1094        // Need to keep track of whether or not a delay slot
1095        // instruction has been fetched
1096
1097        for (;
1098             offset < cacheBlkSize &&
1099                 numInst < fetchWidth &&
1100                 (!predicted_branch || delaySlotInfo[tid].numInsts > 0);
1101             ++numInst) {
1102
1103            // Get a sequence number.
1104            inst_seq = cpu->getAndIncrementInstSeq();
1105
1106            // Make sure this is a valid index.
1107            assert(offset <= cacheBlkSize - instSize);
1108
1109            // Get the instruction from the array of the cache line.
1110            inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
1111                        (&cacheData[tid][offset]));
1112
1113            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1114
1115            // Create a new DynInst from the instruction fetched.
1116            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1117                                                 next_PC,
1118                                                 inst_seq, cpu);
1119            instruction->setTid(tid);
1120
1121            instruction->setASID(tid);
1122
1123            instruction->setThreadState(cpu->thread[tid]);
1124
1125            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1126                    "[sn:%lli]\n",
1127                    tid, instruction->readPC(), inst_seq);
1128
1129            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1130                    tid, instruction->staticInst->disassemble(fetch_PC));
1131
1132            instruction->traceData =
1133                Trace::getInstRecord(curTick, cpu->tcBase(tid),
1134                                     instruction->staticInst,
1135                                     instruction->readPC());
1136
1137            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
1138                                                     next_NPC);
1139
1140            // Add instruction to the CPU's list of instructions.
1141            instruction->setInstListIt(cpu->addInst(instruction));
1142
1143            // Write the instruction to the first slot in the queue
1144            // that heads to decode.
1145            toDecode->insts[numInst] = instruction;
1146
1147            toDecode->size++;
1148
1149            // Increment stat of fetched instructions.
1150            ++fetchedInsts;
1151
1152            // Move to the next instruction, unless we have a branch.
1153            fetch_PC = next_PC;
1154
1155            if (instruction->isQuiesce()) {
1156//                warn("%lli: Quiesce instruction encountered, halting fetch!",
1157//                     curTick);
1158                fetchStatus[tid] = QuiescePending;
1159                ++numInst;
1160                status_change = true;
1161                break;
1162            }
1163
1164            offset += instSize;
1165
1166#if ISA_HAS_DELAY_SLOT
1167            if (predicted_branch) {
1168                delaySlotInfo[tid].branchSeqNum = inst_seq;
1169
1170                DPRINTF(Fetch, "[tid:%i]: Delay slot branch set to [sn:%i]\n",
1171                        tid, inst_seq);
1172                continue;
1173            } else if (delaySlotInfo[tid].numInsts > 0) {
1174                --delaySlotInfo[tid].numInsts;
1175
1176                // It's OK to set PC to target of branch
1177                if (delaySlotInfo[tid].numInsts == 0) {
1178                    delaySlotInfo[tid].targetReady = true;
1179
1180                    // Break the looping condition
1181                    predicted_branch = true;
1182                }
1183
1184                DPRINTF(Fetch, "[tid:%i]: %i delay slot inst(s) left to"
1185                        " process.\n", tid, delaySlotInfo[tid].numInsts);
1186            }
1187#endif
1188        }
1189
1190        if (offset >= cacheBlkSize) {
1191            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
1192                    "block.\n", tid);
1193        } else if (numInst >= fetchWidth) {
1194            DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
1195                    "for this cycle.\n", tid);
1196        } else if (predicted_branch && delaySlotInfo[tid].numInsts <= 0) {
1197            DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
1198                    "instruction encountered.\n", tid);
1199        }
1200    }
1201
1202    if (numInst > 0) {
1203        wroteToTimeBuffer = true;
1204    }
1205
1206    // Now that fetching is completed, update the PC to signify what the next
1207    // cycle will be.
1208    if (fault == NoFault) {
1209#if ISA_HAS_DELAY_SLOT
1210        if (delaySlotInfo[tid].targetReady &&
1211            delaySlotInfo[tid].numInsts == 0) {
1212            // Set PC to target
1213            PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
1214            nextPC[tid] = next_PC + instSize;        //next_NPC
1215            nextNPC[tid] = next_PC + (2 * instSize);
1216
1217            delaySlotInfo[tid].targetReady = false;
1218        } else {
1219            PC[tid] = next_PC;
1220            nextPC[tid] = next_NPC;
1221            nextNPC[tid] = next_NPC + instSize;
1222        }
1223
1224        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
1225#else
1226        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1227        PC[tid] = next_PC;
1228        nextPC[tid] = next_PC + instSize;
1229#endif
1230    } else {
1231        // We shouldn't be in an icache miss and also have a fault (an ITB
1232        // miss)
1233        if (fetchStatus[tid] == IcacheWaitResponse) {
1234            panic("Fetch should have exited prior to this!");
1235        }
1236
1237        // Send the fault to commit.  This thread will not do anything
1238        // until commit handles the fault.  The only other way it can
1239        // wake up is if a squash comes along and changes the PC.
1240#if FULL_SYSTEM
1241        assert(numInst != fetchWidth);
1242        // Get a sequence number.
1243        inst_seq = cpu->getAndIncrementInstSeq();
1244        // We will use a nop in order to carry the fault.
1245        ext_inst = TheISA::NoopMachInst;
1246
1247        // Create a new DynInst from the dummy nop.
1248        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1249                                             next_PC,
1250                                             inst_seq, cpu);
1251        instruction->setPredTarg(next_PC + instSize);
1252        instruction->setTid(tid);
1253
1254        instruction->setASID(tid);
1255
1256        instruction->setThreadState(cpu->thread[tid]);
1257
1258        instruction->traceData = NULL;
1259
1260        instruction->setInstListIt(cpu->addInst(instruction));
1261
1262        instruction->fault = fault;
1263
1264        toDecode->insts[numInst] = instruction;
1265        toDecode->size++;
1266
1267        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1268
1269        fetchStatus[tid] = TrapPending;
1270        status_change = true;
1271
1272//        warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1273#else // !FULL_SYSTEM
1274        warn("cycle %lli: fault (%s) detected @ PC %08p", curTick, fault->name(), PC[tid]);
1275#endif // FULL_SYSTEM
1276    }
1277}
1278
1279template<class Impl>
1280void
1281DefaultFetch<Impl>::recvRetry()
1282{
1283    assert(cacheBlocked);
1284    if (retryPkt != NULL) {
1285        assert(retryTid != -1);
1286        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1287
1288        if (icachePort->sendTiming(retryPkt)) {
1289            fetchStatus[retryTid] = IcacheWaitResponse;
1290            retryPkt = NULL;
1291            retryTid = -1;
1292            cacheBlocked = false;
1293        }
1294    } else {
1295        assert(retryTid == -1);
1296        // Access has been squashed since it was sent out.  Just clear
1297        // the cache being blocked.
1298        cacheBlocked = false;
1299    }
1300}
1301
1302///////////////////////////////////////
1303//                                   //
1304//  SMT FETCH POLICY MAINTAINED HERE //
1305//                                   //
1306///////////////////////////////////////
1307template<class Impl>
1308int
1309DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1310{
1311    if (numThreads > 1) {
1312        switch (fetch_priority) {
1313
1314          case SingleThread:
1315            return 0;
1316
1317          case RoundRobin:
1318            return roundRobin();
1319
1320          case IQ:
1321            return iqCount();
1322
1323          case LSQ:
1324            return lsqCount();
1325
1326          case Branch:
1327            return branchCount();
1328
1329          default:
1330            return -1;
1331        }
1332    } else {
1333        int tid = *((*activeThreads).begin());
1334
1335        if (fetchStatus[tid] == Running ||
1336            fetchStatus[tid] == IcacheAccessComplete ||
1337            fetchStatus[tid] == Idle) {
1338            return tid;
1339        } else {
1340            return -1;
1341        }
1342    }
1343
1344}
1345
1346
1347template<class Impl>
1348int
1349DefaultFetch<Impl>::roundRobin()
1350{
1351    std::list<unsigned>::iterator pri_iter = priorityList.begin();
1352    std::list<unsigned>::iterator end      = priorityList.end();
1353
1354    int high_pri;
1355
1356    while (pri_iter != end) {
1357        high_pri = *pri_iter;
1358
1359        assert(high_pri <= numThreads);
1360
1361        if (fetchStatus[high_pri] == Running ||
1362            fetchStatus[high_pri] == IcacheAccessComplete ||
1363            fetchStatus[high_pri] == Idle) {
1364
1365            priorityList.erase(pri_iter);
1366            priorityList.push_back(high_pri);
1367
1368            return high_pri;
1369        }
1370
1371        pri_iter++;
1372    }
1373
1374    return -1;
1375}
1376
1377template<class Impl>
1378int
1379DefaultFetch<Impl>::iqCount()
1380{
1381    std::priority_queue<unsigned> PQ;
1382
1383    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1384
1385    while (threads != (*activeThreads).end()) {
1386        unsigned tid = *threads++;
1387
1388        PQ.push(fromIEW->iewInfo[tid].iqCount);
1389    }
1390
1391    while (!PQ.empty()) {
1392
1393        unsigned high_pri = PQ.top();
1394
1395        if (fetchStatus[high_pri] == Running ||
1396            fetchStatus[high_pri] == IcacheAccessComplete ||
1397            fetchStatus[high_pri] == Idle)
1398            return high_pri;
1399        else
1400            PQ.pop();
1401
1402    }
1403
1404    return -1;
1405}
1406
1407template<class Impl>
1408int
1409DefaultFetch<Impl>::lsqCount()
1410{
1411    std::priority_queue<unsigned> PQ;
1412
1413
1414    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1415
1416    while (threads != (*activeThreads).end()) {
1417        unsigned tid = *threads++;
1418
1419        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1420    }
1421
1422    while (!PQ.empty()) {
1423
1424        unsigned high_pri = PQ.top();
1425
1426        if (fetchStatus[high_pri] == Running ||
1427            fetchStatus[high_pri] == IcacheAccessComplete ||
1428            fetchStatus[high_pri] == Idle)
1429            return high_pri;
1430        else
1431            PQ.pop();
1432
1433    }
1434
1435    return -1;
1436}
1437
1438template<class Impl>
1439int
1440DefaultFetch<Impl>::branchCount()
1441{
1442    std::list<unsigned>::iterator threads = (*activeThreads).begin();
1443    panic("Branch Count Fetch policy unimplemented\n");
1444    return *threads;
1445}
1446