fetch_impl.hh revision 2894:a83675362809 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61    panic("DefaultFetch doesn't expect recvAtomic callback!");
62    return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69    panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76    if (status == RangeChange)
77        return;
78
79    panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86    fetch->processCacheCompletion(pkt);
87    return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94    fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99    : mem(params->mem),
100      branchPred(params),
101      decodeToFetchDelay(params->decodeToFetchDelay),
102      renameToFetchDelay(params->renameToFetchDelay),
103      iewToFetchDelay(params->iewToFetchDelay),
104      commitToFetchDelay(params->commitToFetchDelay),
105      fetchWidth(params->fetchWidth),
106      cacheBlocked(false),
107      retryPkt(NULL),
108      retryTid(-1),
109      numThreads(params->numberOfThreads),
110      numFetchingThreads(params->smtNumFetchingThreads),
111      interruptPending(false),
112      drainPending(false),
113      switchedOut(false)
114{
115    if (numThreads > Impl::MaxThreads)
116        fatal("numThreads is not a valid value\n");
117
118    // Set fetch stage's status to inactive.
119    _status = Inactive;
120
121    string policy = params->smtFetchPolicy;
122
123    // Convert string to lowercase
124    std::transform(policy.begin(), policy.end(), policy.begin(),
125                   (int(*)(int)) tolower);
126
127    // Figure out fetch policy
128    if (policy == "singlethread") {
129        fetchPolicy = SingleThread;
130        if (numThreads > 1)
131            panic("Invalid Fetch Policy for a SMT workload.");
132    } else if (policy == "roundrobin") {
133        fetchPolicy = RoundRobin;
134        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135    } else if (policy == "branch") {
136        fetchPolicy = Branch;
137        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138    } else if (policy == "iqcount") {
139        fetchPolicy = IQ;
140        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141    } else if (policy == "lsqcount") {
142        fetchPolicy = LSQ;
143        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144    } else {
145        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146              " RoundRobin,LSQcount,IQcount}\n");
147    }
148
149    // Size of cache block.
150    cacheBlkSize = 64;
151
152    // Create mask to get rid of offset bits.
153    cacheBlkMask = (cacheBlkSize - 1);
154
155    for (int tid=0; tid < numThreads; tid++) {
156
157        fetchStatus[tid] = Running;
158
159        priorityList.push_back(tid);
160
161        memReq[tid] = NULL;
162
163        // Create space to store a cache line.
164        cacheData[tid] = new uint8_t[cacheBlkSize];
165
166        stalls[tid].decode = 0;
167        stalls[tid].rename = 0;
168        stalls[tid].iew = 0;
169        stalls[tid].commit = 0;
170    }
171
172    // Get the size of an instruction.
173    instSize = sizeof(MachInst);
174}
175
176template <class Impl>
177std::string
178DefaultFetch<Impl>::name() const
179{
180    return cpu->name() + ".fetch";
181}
182
183template <class Impl>
184void
185DefaultFetch<Impl>::regStats()
186{
187    icacheStallCycles
188        .name(name() + ".icacheStallCycles")
189        .desc("Number of cycles fetch is stalled on an Icache miss")
190        .prereq(icacheStallCycles);
191
192    fetchedInsts
193        .name(name() + ".Insts")
194        .desc("Number of instructions fetch has processed")
195        .prereq(fetchedInsts);
196
197    fetchedBranches
198        .name(name() + ".Branches")
199        .desc("Number of branches that fetch encountered")
200        .prereq(fetchedBranches);
201
202    predictedBranches
203        .name(name() + ".predictedBranches")
204        .desc("Number of branches that fetch has predicted taken")
205        .prereq(predictedBranches);
206
207    fetchCycles
208        .name(name() + ".Cycles")
209        .desc("Number of cycles fetch has run and was not squashing or"
210              " blocked")
211        .prereq(fetchCycles);
212
213    fetchSquashCycles
214        .name(name() + ".SquashCycles")
215        .desc("Number of cycles fetch has spent squashing")
216        .prereq(fetchSquashCycles);
217
218    fetchIdleCycles
219        .name(name() + ".IdleCycles")
220        .desc("Number of cycles fetch was idle")
221        .prereq(fetchIdleCycles);
222
223    fetchBlockedCycles
224        .name(name() + ".BlockedCycles")
225        .desc("Number of cycles fetch has spent blocked")
226        .prereq(fetchBlockedCycles);
227
228    fetchedCacheLines
229        .name(name() + ".CacheLines")
230        .desc("Number of cache lines fetched")
231        .prereq(fetchedCacheLines);
232
233    fetchMiscStallCycles
234        .name(name() + ".MiscStallCycles")
235        .desc("Number of cycles fetch has spent waiting on interrupts, or "
236              "bad addresses, or out of MSHRs")
237        .prereq(fetchMiscStallCycles);
238
239    fetchIcacheSquashes
240        .name(name() + ".IcacheSquashes")
241        .desc("Number of outstanding Icache misses that were squashed")
242        .prereq(fetchIcacheSquashes);
243
244    fetchNisnDist
245        .init(/* base value */ 0,
246              /* last value */ fetchWidth,
247              /* bucket size */ 1)
248        .name(name() + ".rateDist")
249        .desc("Number of instructions fetched each cycle (Total)")
250        .flags(Stats::pdf);
251
252    idleRate
253        .name(name() + ".idleRate")
254        .desc("Percent of cycles fetch was idle")
255        .prereq(idleRate);
256    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
257
258    branchRate
259        .name(name() + ".branchRate")
260        .desc("Number of branch fetches per cycle")
261        .flags(Stats::total);
262    branchRate = fetchedBranches / cpu->numCycles;
263
264    fetchRate
265        .name(name() + ".rate")
266        .desc("Number of inst fetches per cycle")
267        .flags(Stats::total);
268    fetchRate = fetchedInsts / cpu->numCycles;
269
270    branchPred.regStats();
271}
272
273template<class Impl>
274void
275DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
276{
277    DPRINTF(Fetch, "Setting the CPU pointer.\n");
278    cpu = cpu_ptr;
279
280    // Name is finally available, so create the port.
281    icachePort = new IcachePort(this);
282
283#if USE_CHECKER
284    if (cpu->checker) {
285        cpu->checker->setIcachePort(icachePort);
286    }
287#endif
288
289    // Fetch needs to start fetching instructions at the very beginning,
290    // so it must start up in active state.
291    switchToActive();
292}
293
294template<class Impl>
295void
296DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
297{
298    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
299    timeBuffer = time_buffer;
300
301    // Create wires to get information from proper places in time buffer.
302    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
303    fromRename = timeBuffer->getWire(-renameToFetchDelay);
304    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
305    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
306}
307
308template<class Impl>
309void
310DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
311{
312    DPRINTF(Fetch, "Setting active threads list pointer.\n");
313    activeThreads = at_ptr;
314}
315
316template<class Impl>
317void
318DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
319{
320    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
321    fetchQueue = fq_ptr;
322
323    // Create wire to write information to proper place in fetch queue.
324    toDecode = fetchQueue->getWire(0);
325}
326
327template<class Impl>
328void
329DefaultFetch<Impl>::initStage()
330{
331    // Setup PC and nextPC with initial state.
332    for (int tid = 0; tid < numThreads; tid++) {
333        PC[tid] = cpu->readPC(tid);
334        nextPC[tid] = cpu->readNextPC(tid);
335#if THE_ISA != ALPHA_ISA
336        nextNPC[tid] = cpu->readNextNPC(tid);
337#endif
338    }
339}
340
341template<class Impl>
342void
343DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
344{
345    unsigned tid = pkt->req->getThreadNum();
346
347    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
348
349    // Only change the status if it's still waiting on the icache access
350    // to return.
351    if (fetchStatus[tid] != IcacheWaitResponse ||
352        pkt->req != memReq[tid] ||
353        isSwitchedOut()) {
354        ++fetchIcacheSquashes;
355        delete pkt->req;
356        delete pkt;
357        return;
358    }
359
360    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
361
362    if (!drainPending) {
363        // Wake up the CPU (if it went to sleep and was waiting on
364        // this completion event).
365        cpu->wakeCPU();
366
367        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
368                tid);
369
370        switchToActive();
371    }
372
373    // Only switch to IcacheAccessComplete if we're not stalled as well.
374    if (checkStall(tid)) {
375        fetchStatus[tid] = Blocked;
376    } else {
377        fetchStatus[tid] = IcacheAccessComplete;
378    }
379
380    // Reset the mem req to NULL.
381    delete pkt->req;
382    delete pkt;
383    memReq[tid] = NULL;
384}
385
386template <class Impl>
387bool
388DefaultFetch<Impl>::drain()
389{
390    // Fetch is ready to drain at any time.
391    cpu->signalDrained();
392    drainPending = true;
393    return true;
394}
395
396template <class Impl>
397void
398DefaultFetch<Impl>::resume()
399{
400    drainPending = false;
401}
402
403template <class Impl>
404void
405DefaultFetch<Impl>::switchOut()
406{
407    switchedOut = true;
408    // Branch predictor needs to have its state cleared.
409    branchPred.switchOut();
410}
411
412template <class Impl>
413void
414DefaultFetch<Impl>::takeOverFrom()
415{
416    // Reset all state
417    for (int i = 0; i < Impl::MaxThreads; ++i) {
418        stalls[i].decode = 0;
419        stalls[i].rename = 0;
420        stalls[i].iew = 0;
421        stalls[i].commit = 0;
422        PC[i] = cpu->readPC(i);
423        nextPC[i] = cpu->readNextPC(i);
424#if THE_ISA != ALPHA_ISA
425        nextNPC[i] = cpu->readNextNPC(i);
426#endif
427        fetchStatus[i] = Running;
428    }
429    numInst = 0;
430    wroteToTimeBuffer = false;
431    _status = Inactive;
432    switchedOut = false;
433    branchPred.takeOverFrom();
434}
435
436template <class Impl>
437void
438DefaultFetch<Impl>::wakeFromQuiesce()
439{
440    DPRINTF(Fetch, "Waking up from quiesce\n");
441    // Hopefully this is safe
442    // @todo: Allow other threads to wake from quiesce.
443    fetchStatus[0] = Running;
444}
445
446template <class Impl>
447inline void
448DefaultFetch<Impl>::switchToActive()
449{
450    if (_status == Inactive) {
451        DPRINTF(Activity, "Activating stage.\n");
452
453        cpu->activateStage(O3CPU::FetchIdx);
454
455        _status = Active;
456    }
457}
458
459template <class Impl>
460inline void
461DefaultFetch<Impl>::switchToInactive()
462{
463    if (_status == Active) {
464        DPRINTF(Activity, "Deactivating stage.\n");
465
466        cpu->deactivateStage(O3CPU::FetchIdx);
467
468        _status = Inactive;
469    }
470}
471
472template <class Impl>
473bool
474DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
475{
476    // Do branch prediction check here.
477    // A bit of a misnomer...next_PC is actually the current PC until
478    // this function updates it.
479    bool predict_taken;
480
481    if (!inst->isControl()) {
482        next_PC = next_PC + instSize;
483        inst->setPredTarg(next_PC);
484        return false;
485    }
486
487    predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
488
489    ++fetchedBranches;
490
491    if (predict_taken) {
492        ++predictedBranches;
493    }
494
495    return predict_taken;
496}
497
498template <class Impl>
499bool
500DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
501{
502    Fault fault = NoFault;
503
504#if FULL_SYSTEM
505    // Flag to say whether or not address is physical addr.
506    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
507#else
508    unsigned flags = 0;
509#endif // FULL_SYSTEM
510
511    if (cacheBlocked || (interruptPending && flags == 0)) {
512        // Hold off fetch from getting new instructions when:
513        // Cache is blocked, or
514        // while an interrupt is pending and we're not in PAL mode, or
515        // fetch is switched out.
516        return false;
517    }
518
519    // Align the fetch PC so it's at the start of a cache block.
520    fetch_PC = icacheBlockAlignPC(fetch_PC);
521
522    // Setup the memReq to do a read of the first instruction's address.
523    // Set the appropriate read size and flags as well.
524    // Build request here.
525    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
526                                     fetch_PC, cpu->readCpuId(), tid);
527
528    memReq[tid] = mem_req;
529
530    // Translate the instruction request.
531    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
532
533    // In the case of faults, the fetch stage may need to stall and wait
534    // for the ITB miss to be handled.
535
536    // If translation was successful, attempt to read the first
537    // instruction.
538    if (fault == NoFault) {
539#if 0
540        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
541            memReq[tid]->flags & UNCACHEABLE) {
542            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
543                    "misspeculating path)!",
544                    memReq[tid]->paddr);
545            ret_fault = TheISA::genMachineCheckFault();
546            return false;
547        }
548#endif
549
550        // Build packet here.
551        PacketPtr data_pkt = new Packet(mem_req,
552                                        Packet::ReadReq, Packet::Broadcast);
553        data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
554
555        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
556
557        fetchedCacheLines++;
558
559        // Now do the timing access to see whether or not the instruction
560        // exists within the cache.
561        if (!icachePort->sendTiming(data_pkt)) {
562            assert(retryPkt == NULL);
563            assert(retryTid == -1);
564            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
565            fetchStatus[tid] = IcacheWaitRetry;
566            retryPkt = data_pkt;
567            retryTid = tid;
568            cacheBlocked = true;
569            return false;
570        }
571
572        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
573
574        lastIcacheStall[tid] = curTick;
575
576        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
577                "response.\n", tid);
578
579        fetchStatus[tid] = IcacheWaitResponse;
580    } else {
581        delete mem_req;
582        memReq[tid] = NULL;
583    }
584
585    ret_fault = fault;
586    return true;
587}
588
589template <class Impl>
590inline void
591DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
592{
593    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
594            tid, new_PC);
595
596    PC[tid] = new_PC;
597    nextPC[tid] = new_PC + instSize;
598
599    // Clear the icache miss if it's outstanding.
600    if (fetchStatus[tid] == IcacheWaitResponse) {
601        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
602                tid);
603        memReq[tid] = NULL;
604    }
605
606    // Get rid of the retrying packet if it was from this thread.
607    if (retryTid == tid) {
608        assert(cacheBlocked);
609        cacheBlocked = false;
610        retryTid = -1;
611        retryPkt = NULL;
612        delete retryPkt->req;
613        delete retryPkt;
614    }
615
616    fetchStatus[tid] = Squashing;
617
618    ++fetchSquashCycles;
619}
620
621template<class Impl>
622void
623DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
624                                     const InstSeqNum &seq_num,
625                                     unsigned tid)
626{
627    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
628
629    doSquash(new_PC, tid);
630
631    // Tell the CPU to remove any instructions that are in flight between
632    // fetch and decode.
633    cpu->removeInstsUntil(seq_num, tid);
634}
635
636template<class Impl>
637bool
638DefaultFetch<Impl>::checkStall(unsigned tid) const
639{
640    bool ret_val = false;
641
642    if (cpu->contextSwitch) {
643        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
644        ret_val = true;
645    } else if (stalls[tid].decode) {
646        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
647        ret_val = true;
648    } else if (stalls[tid].rename) {
649        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
650        ret_val = true;
651    } else if (stalls[tid].iew) {
652        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
653        ret_val = true;
654    } else if (stalls[tid].commit) {
655        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
656        ret_val = true;
657    }
658
659    return ret_val;
660}
661
662template<class Impl>
663typename DefaultFetch<Impl>::FetchStatus
664DefaultFetch<Impl>::updateFetchStatus()
665{
666    //Check Running
667    list<unsigned>::iterator threads = (*activeThreads).begin();
668
669    while (threads != (*activeThreads).end()) {
670
671        unsigned tid = *threads++;
672
673        if (fetchStatus[tid] == Running ||
674            fetchStatus[tid] == Squashing ||
675            fetchStatus[tid] == IcacheAccessComplete) {
676
677            if (_status == Inactive) {
678                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
679
680                if (fetchStatus[tid] == IcacheAccessComplete) {
681                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
682                            "completion\n",tid);
683                }
684
685                cpu->activateStage(O3CPU::FetchIdx);
686            }
687
688            return Active;
689        }
690    }
691
692    // Stage is switching from active to inactive, notify CPU of it.
693    if (_status == Active) {
694        DPRINTF(Activity, "Deactivating stage.\n");
695
696        cpu->deactivateStage(O3CPU::FetchIdx);
697    }
698
699    return Inactive;
700}
701
702template <class Impl>
703void
704DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
705{
706    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
707
708    doSquash(new_PC, tid);
709
710    // Tell the CPU to remove any instructions that are not in the ROB.
711    cpu->removeInstsNotInROB(tid);
712}
713
714template <class Impl>
715void
716DefaultFetch<Impl>::tick()
717{
718    list<unsigned>::iterator threads = (*activeThreads).begin();
719    bool status_change = false;
720
721    wroteToTimeBuffer = false;
722
723    while (threads != (*activeThreads).end()) {
724        unsigned tid = *threads++;
725
726        // Check the signals for each thread to determine the proper status
727        // for each thread.
728        bool updated_status = checkSignalsAndUpdate(tid);
729        status_change =  status_change || updated_status;
730    }
731
732    DPRINTF(Fetch, "Running stage.\n");
733
734    // Reset the number of the instruction we're fetching.
735    numInst = 0;
736
737#if FULL_SYSTEM
738    if (fromCommit->commitInfo[0].interruptPending) {
739        interruptPending = true;
740    }
741
742    if (fromCommit->commitInfo[0].clearInterrupt) {
743        interruptPending = false;
744    }
745#endif
746
747    for (threadFetched = 0; threadFetched < numFetchingThreads;
748         threadFetched++) {
749        // Fetch each of the actively fetching threads.
750        fetch(status_change);
751    }
752
753    // Record number of instructions fetched this cycle for distribution.
754    fetchNisnDist.sample(numInst);
755
756    if (status_change) {
757        // Change the fetch stage status if there was a status change.
758        _status = updateFetchStatus();
759    }
760
761    // If there was activity this cycle, inform the CPU of it.
762    if (wroteToTimeBuffer || cpu->contextSwitch) {
763        DPRINTF(Activity, "Activity this cycle.\n");
764
765        cpu->activityThisCycle();
766    }
767}
768
769template <class Impl>
770bool
771DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
772{
773    // Update the per thread stall statuses.
774    if (fromDecode->decodeBlock[tid]) {
775        stalls[tid].decode = true;
776    }
777
778    if (fromDecode->decodeUnblock[tid]) {
779        assert(stalls[tid].decode);
780        assert(!fromDecode->decodeBlock[tid]);
781        stalls[tid].decode = false;
782    }
783
784    if (fromRename->renameBlock[tid]) {
785        stalls[tid].rename = true;
786    }
787
788    if (fromRename->renameUnblock[tid]) {
789        assert(stalls[tid].rename);
790        assert(!fromRename->renameBlock[tid]);
791        stalls[tid].rename = false;
792    }
793
794    if (fromIEW->iewBlock[tid]) {
795        stalls[tid].iew = true;
796    }
797
798    if (fromIEW->iewUnblock[tid]) {
799        assert(stalls[tid].iew);
800        assert(!fromIEW->iewBlock[tid]);
801        stalls[tid].iew = false;
802    }
803
804    if (fromCommit->commitBlock[tid]) {
805        stalls[tid].commit = true;
806    }
807
808    if (fromCommit->commitUnblock[tid]) {
809        assert(stalls[tid].commit);
810        assert(!fromCommit->commitBlock[tid]);
811        stalls[tid].commit = false;
812    }
813
814    // Check squash signals from commit.
815    if (fromCommit->commitInfo[tid].squash) {
816
817        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
818                "from commit.\n",tid);
819
820        // In any case, squash.
821        squash(fromCommit->commitInfo[tid].nextPC,tid);
822
823        // Also check if there's a mispredict that happened.
824        if (fromCommit->commitInfo[tid].branchMispredict) {
825            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
826                              fromCommit->commitInfo[tid].nextPC,
827                              fromCommit->commitInfo[tid].branchTaken,
828                              tid);
829        } else {
830            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
831                              tid);
832        }
833
834        return true;
835    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
836        // Update the branch predictor if it wasn't a squashed instruction
837        // that was broadcasted.
838        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
839    }
840
841    // Check ROB squash signals from commit.
842    if (fromCommit->commitInfo[tid].robSquashing) {
843        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
844
845        // Continue to squash.
846        fetchStatus[tid] = Squashing;
847
848        return true;
849    }
850
851    // Check squash signals from decode.
852    if (fromDecode->decodeInfo[tid].squash) {
853        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
854                "from decode.\n",tid);
855
856        // Update the branch predictor.
857        if (fromDecode->decodeInfo[tid].branchMispredict) {
858            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
859                              fromDecode->decodeInfo[tid].nextPC,
860                              fromDecode->decodeInfo[tid].branchTaken,
861                              tid);
862        } else {
863            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
864                              tid);
865        }
866
867        if (fetchStatus[tid] != Squashing) {
868            // Squash unless we're already squashing
869            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
870                             fromDecode->decodeInfo[tid].doneSeqNum,
871                             tid);
872
873            return true;
874        }
875    }
876
877    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
878        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
879
880        fetchStatus[tid] = Blocked;
881
882        return true;
883    }
884
885    if (fetchStatus[tid] == Blocked ||
886        fetchStatus[tid] == Squashing) {
887        // Switch status to running if fetch isn't being told to block or
888        // squash this cycle.
889        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
890                tid);
891
892        fetchStatus[tid] = Running;
893
894        return true;
895    }
896
897    // If we've reached this point, we have not gotten any signals that
898    // cause fetch to change its status.  Fetch remains the same as before.
899    return false;
900}
901
902template<class Impl>
903void
904DefaultFetch<Impl>::fetch(bool &status_change)
905{
906    //////////////////////////////////////////
907    // Start actual fetch
908    //////////////////////////////////////////
909    int tid = getFetchingThread(fetchPolicy);
910
911    if (tid == -1 || drainPending) {
912        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
913
914        // Breaks looping condition in tick()
915        threadFetched = numFetchingThreads;
916        return;
917    }
918
919    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
920
921    // The current PC.
922    Addr &fetch_PC = PC[tid];
923
924    // Fault code for memory access.
925    Fault fault = NoFault;
926
927    // If returning from the delay of a cache miss, then update the status
928    // to running, otherwise do the cache access.  Possibly move this up
929    // to tick() function.
930    if (fetchStatus[tid] == IcacheAccessComplete) {
931        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
932                tid);
933
934        fetchStatus[tid] = Running;
935        status_change = true;
936    } else if (fetchStatus[tid] == Running) {
937        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
938                "instruction, starting at PC %08p.\n",
939                tid, fetch_PC);
940
941        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
942        if (!fetch_success) {
943            if (cacheBlocked) {
944                ++icacheStallCycles;
945            } else {
946                ++fetchMiscStallCycles;
947            }
948            return;
949        }
950    } else {
951        if (fetchStatus[tid] == Idle) {
952            ++fetchIdleCycles;
953        } else if (fetchStatus[tid] == Blocked) {
954            ++fetchBlockedCycles;
955        } else if (fetchStatus[tid] == Squashing) {
956            ++fetchSquashCycles;
957        } else if (fetchStatus[tid] == IcacheWaitResponse) {
958            ++icacheStallCycles;
959        }
960
961        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
962        // fetch should do nothing.
963        return;
964    }
965
966    ++fetchCycles;
967
968    // If we had a stall due to an icache miss, then return.
969    if (fetchStatus[tid] == IcacheWaitResponse) {
970        ++icacheStallCycles;
971        status_change = true;
972        return;
973    }
974
975    Addr next_PC = fetch_PC;
976    InstSeqNum inst_seq;
977    MachInst inst;
978    ExtMachInst ext_inst;
979    // @todo: Fix this hack.
980    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
981
982    if (fault == NoFault) {
983        // If the read of the first instruction was successful, then grab the
984        // instructions from the rest of the cache line and put them into the
985        // queue heading to decode.
986
987        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
988                "decode.\n",tid);
989
990        // Need to keep track of whether or not a predicted branch
991        // ended this fetch block.
992        bool predicted_branch = false;
993
994        for (;
995             offset < cacheBlkSize &&
996                 numInst < fetchWidth &&
997                 !predicted_branch;
998             ++numInst) {
999
1000            // Get a sequence number.
1001            inst_seq = cpu->getAndIncrementInstSeq();
1002
1003            // Make sure this is a valid index.
1004            assert(offset <= cacheBlkSize - instSize);
1005
1006            // Get the instruction from the array of the cache line.
1007            inst = gtoh(*reinterpret_cast<MachInst *>
1008                        (&cacheData[tid][offset]));
1009
1010            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1011
1012            // Create a new DynInst from the instruction fetched.
1013            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1014                                                 next_PC,
1015                                                 inst_seq, cpu);
1016            instruction->setTid(tid);
1017
1018            instruction->setASID(tid);
1019
1020            instruction->setThreadState(cpu->thread[tid]);
1021
1022            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1023                    "[sn:%lli]\n",
1024                    tid, instruction->readPC(), inst_seq);
1025
1026            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1027                    tid, instruction->staticInst->disassemble(fetch_PC));
1028
1029            instruction->traceData =
1030                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1031                                     instruction->staticInst,
1032                                     instruction->readPC(),tid);
1033
1034            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1035
1036            // Add instruction to the CPU's list of instructions.
1037            instruction->setInstListIt(cpu->addInst(instruction));
1038
1039            // Write the instruction to the first slot in the queue
1040            // that heads to decode.
1041            toDecode->insts[numInst] = instruction;
1042
1043            toDecode->size++;
1044
1045            // Increment stat of fetched instructions.
1046            ++fetchedInsts;
1047
1048            // Move to the next instruction, unless we have a branch.
1049            fetch_PC = next_PC;
1050
1051            if (instruction->isQuiesce()) {
1052                warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1053                     curTick);
1054                fetchStatus[tid] = QuiescePending;
1055                ++numInst;
1056                status_change = true;
1057                break;
1058            }
1059
1060            offset+= instSize;
1061        }
1062    }
1063
1064    if (numInst > 0) {
1065        wroteToTimeBuffer = true;
1066    }
1067
1068    // Now that fetching is completed, update the PC to signify what the next
1069    // cycle will be.
1070    if (fault == NoFault) {
1071        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1072
1073#if THE_ISA == ALPHA_ISA
1074        PC[tid] = next_PC;
1075        nextPC[tid] = next_PC + instSize;
1076#else
1077        PC[tid] = next_PC;
1078        nextPC[tid] = next_PC + instSize;
1079        nextPC[tid] = next_PC + instSize;
1080
1081        thread->setNextPC(thread->readNextNPC());
1082        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1083#endif
1084    } else {
1085        // We shouldn't be in an icache miss and also have a fault (an ITB
1086        // miss)
1087        if (fetchStatus[tid] == IcacheWaitResponse) {
1088            panic("Fetch should have exited prior to this!");
1089        }
1090
1091        // Send the fault to commit.  This thread will not do anything
1092        // until commit handles the fault.  The only other way it can
1093        // wake up is if a squash comes along and changes the PC.
1094#if FULL_SYSTEM
1095        assert(numInst != fetchWidth);
1096        // Get a sequence number.
1097        inst_seq = cpu->getAndIncrementInstSeq();
1098        // We will use a nop in order to carry the fault.
1099        ext_inst = TheISA::NoopMachInst;
1100
1101        // Create a new DynInst from the dummy nop.
1102        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1103                                             next_PC,
1104                                             inst_seq, cpu);
1105        instruction->setPredTarg(next_PC + instSize);
1106        instruction->setTid(tid);
1107
1108        instruction->setASID(tid);
1109
1110        instruction->setThreadState(cpu->thread[tid]);
1111
1112        instruction->traceData = NULL;
1113
1114        instruction->setInstListIt(cpu->addInst(instruction));
1115
1116        instruction->fault = fault;
1117
1118        toDecode->insts[numInst] = instruction;
1119        toDecode->size++;
1120
1121        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1122
1123        fetchStatus[tid] = TrapPending;
1124        status_change = true;
1125
1126        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1127#else // !FULL_SYSTEM
1128        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1129#endif // FULL_SYSTEM
1130    }
1131}
1132
1133template<class Impl>
1134void
1135DefaultFetch<Impl>::recvRetry()
1136{
1137    assert(cacheBlocked);
1138    if (retryPkt != NULL) {
1139        assert(retryTid != -1);
1140        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1141
1142        if (icachePort->sendTiming(retryPkt)) {
1143            fetchStatus[retryTid] = IcacheWaitResponse;
1144            retryPkt = NULL;
1145            retryTid = -1;
1146            cacheBlocked = false;
1147        }
1148    } else {
1149        assert(retryTid == -1);
1150        // Access has been squashed since it was sent out.  Just clear
1151        // the cache being blocked.
1152        cacheBlocked = false;
1153    }
1154}
1155
1156///////////////////////////////////////
1157//                                   //
1158//  SMT FETCH POLICY MAINTAINED HERE //
1159//                                   //
1160///////////////////////////////////////
1161template<class Impl>
1162int
1163DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1164{
1165    if (numThreads > 1) {
1166        switch (fetch_priority) {
1167
1168          case SingleThread:
1169            return 0;
1170
1171          case RoundRobin:
1172            return roundRobin();
1173
1174          case IQ:
1175            return iqCount();
1176
1177          case LSQ:
1178            return lsqCount();
1179
1180          case Branch:
1181            return branchCount();
1182
1183          default:
1184            return -1;
1185        }
1186    } else {
1187        int tid = *((*activeThreads).begin());
1188
1189        if (fetchStatus[tid] == Running ||
1190            fetchStatus[tid] == IcacheAccessComplete ||
1191            fetchStatus[tid] == Idle) {
1192            return tid;
1193        } else {
1194            return -1;
1195        }
1196    }
1197
1198}
1199
1200
1201template<class Impl>
1202int
1203DefaultFetch<Impl>::roundRobin()
1204{
1205    list<unsigned>::iterator pri_iter = priorityList.begin();
1206    list<unsigned>::iterator end      = priorityList.end();
1207
1208    int high_pri;
1209
1210    while (pri_iter != end) {
1211        high_pri = *pri_iter;
1212
1213        assert(high_pri <= numThreads);
1214
1215        if (fetchStatus[high_pri] == Running ||
1216            fetchStatus[high_pri] == IcacheAccessComplete ||
1217            fetchStatus[high_pri] == Idle) {
1218
1219            priorityList.erase(pri_iter);
1220            priorityList.push_back(high_pri);
1221
1222            return high_pri;
1223        }
1224
1225        pri_iter++;
1226    }
1227
1228    return -1;
1229}
1230
1231template<class Impl>
1232int
1233DefaultFetch<Impl>::iqCount()
1234{
1235    priority_queue<unsigned> PQ;
1236
1237    list<unsigned>::iterator threads = (*activeThreads).begin();
1238
1239    while (threads != (*activeThreads).end()) {
1240        unsigned tid = *threads++;
1241
1242        PQ.push(fromIEW->iewInfo[tid].iqCount);
1243    }
1244
1245    while (!PQ.empty()) {
1246
1247        unsigned high_pri = PQ.top();
1248
1249        if (fetchStatus[high_pri] == Running ||
1250            fetchStatus[high_pri] == IcacheAccessComplete ||
1251            fetchStatus[high_pri] == Idle)
1252            return high_pri;
1253        else
1254            PQ.pop();
1255
1256    }
1257
1258    return -1;
1259}
1260
1261template<class Impl>
1262int
1263DefaultFetch<Impl>::lsqCount()
1264{
1265    priority_queue<unsigned> PQ;
1266
1267
1268    list<unsigned>::iterator threads = (*activeThreads).begin();
1269
1270    while (threads != (*activeThreads).end()) {
1271        unsigned tid = *threads++;
1272
1273        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1274    }
1275
1276    while (!PQ.empty()) {
1277
1278        unsigned high_pri = PQ.top();
1279
1280        if (fetchStatus[high_pri] == Running ||
1281            fetchStatus[high_pri] == IcacheAccessComplete ||
1282            fetchStatus[high_pri] == Idle)
1283            return high_pri;
1284        else
1285            PQ.pop();
1286
1287    }
1288
1289    return -1;
1290}
1291
1292template<class Impl>
1293int
1294DefaultFetch<Impl>::branchCount()
1295{
1296    list<unsigned>::iterator threads = (*activeThreads).begin();
1297    panic("Branch Count Fetch policy unimplemented\n");
1298    return *threads;
1299}
1300