fetch_impl.hh revision 2893:58c423134221 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "arch/isa_traits.hh"
35#include "arch/utility.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/fetch.hh"
39#include "mem/packet.hh"
40#include "mem/request.hh"
41#include "sim/byteswap.hh"
42#include "sim/host.hh"
43#include "sim/root.hh"
44
45#if FULL_SYSTEM
46#include "arch/tlb.hh"
47#include "arch/vtophys.hh"
48#include "base/remote_gdb.hh"
49#include "sim/system.hh"
50#endif // FULL_SYSTEM
51
52#include <algorithm>
53
54using namespace std;
55using namespace TheISA;
56
57template<class Impl>
58Tick
59DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
60{
61    panic("DefaultFetch doesn't expect recvAtomic callback!");
62    return curTick;
63}
64
65template<class Impl>
66void
67DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
68{
69    panic("DefaultFetch doesn't expect recvFunctional callback!");
70}
71
72template<class Impl>
73void
74DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
75{
76    if (status == RangeChange)
77        return;
78
79    panic("DefaultFetch doesn't expect recvStatusChange callback!");
80}
81
82template<class Impl>
83bool
84DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
85{
86    fetch->processCacheCompletion(pkt);
87    return true;
88}
89
90template<class Impl>
91void
92DefaultFetch<Impl>::IcachePort::recvRetry()
93{
94    fetch->recvRetry();
95}
96
97template<class Impl>
98DefaultFetch<Impl>::DefaultFetch(Params *params)
99    : mem(params->mem),
100      branchPred(params),
101      decodeToFetchDelay(params->decodeToFetchDelay),
102      renameToFetchDelay(params->renameToFetchDelay),
103      iewToFetchDelay(params->iewToFetchDelay),
104      commitToFetchDelay(params->commitToFetchDelay),
105      fetchWidth(params->fetchWidth),
106      cacheBlocked(false),
107      retryPkt(NULL),
108      retryTid(-1),
109      numThreads(params->numberOfThreads),
110      numFetchingThreads(params->smtNumFetchingThreads),
111      interruptPending(false),
112      drainPending(false),
113      switchedOut(false)
114{
115    if (numThreads > Impl::MaxThreads)
116        fatal("numThreads is not a valid value\n");
117
118    // Set fetch stage's status to inactive.
119    _status = Inactive;
120
121    string policy = params->smtFetchPolicy;
122
123    // Convert string to lowercase
124    std::transform(policy.begin(), policy.end(), policy.begin(),
125                   (int(*)(int)) tolower);
126
127    // Figure out fetch policy
128    if (policy == "singlethread") {
129        fetchPolicy = SingleThread;
130        if (numThreads > 1)
131            panic("Invalid Fetch Policy for a SMT workload.");
132    } else if (policy == "roundrobin") {
133        fetchPolicy = RoundRobin;
134        DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
135    } else if (policy == "branch") {
136        fetchPolicy = Branch;
137        DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
138    } else if (policy == "iqcount") {
139        fetchPolicy = IQ;
140        DPRINTF(Fetch, "Fetch policy set to IQ count\n");
141    } else if (policy == "lsqcount") {
142        fetchPolicy = LSQ;
143        DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
144    } else {
145        fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
146              " RoundRobin,LSQcount,IQcount}\n");
147    }
148
149    // Size of cache block.
150    cacheBlkSize = 64;
151
152    // Create mask to get rid of offset bits.
153    cacheBlkMask = (cacheBlkSize - 1);
154
155    for (int tid=0; tid < numThreads; tid++) {
156
157        fetchStatus[tid] = Running;
158
159        priorityList.push_back(tid);
160
161        memReq[tid] = NULL;
162
163        // Create space to store a cache line.
164        cacheData[tid] = new uint8_t[cacheBlkSize];
165
166        stalls[tid].decode = 0;
167        stalls[tid].rename = 0;
168        stalls[tid].iew = 0;
169        stalls[tid].commit = 0;
170    }
171
172    // Get the size of an instruction.
173    instSize = sizeof(MachInst);
174}
175
176template <class Impl>
177std::string
178DefaultFetch<Impl>::name() const
179{
180    return cpu->name() + ".fetch";
181}
182
183template <class Impl>
184void
185DefaultFetch<Impl>::regStats()
186{
187    icacheStallCycles
188        .name(name() + ".icacheStallCycles")
189        .desc("Number of cycles fetch is stalled on an Icache miss")
190        .prereq(icacheStallCycles);
191
192    fetchedInsts
193        .name(name() + ".Insts")
194        .desc("Number of instructions fetch has processed")
195        .prereq(fetchedInsts);
196
197    fetchedBranches
198        .name(name() + ".Branches")
199        .desc("Number of branches that fetch encountered")
200        .prereq(fetchedBranches);
201
202    predictedBranches
203        .name(name() + ".predictedBranches")
204        .desc("Number of branches that fetch has predicted taken")
205        .prereq(predictedBranches);
206
207    fetchCycles
208        .name(name() + ".Cycles")
209        .desc("Number of cycles fetch has run and was not squashing or"
210              " blocked")
211        .prereq(fetchCycles);
212
213    fetchSquashCycles
214        .name(name() + ".SquashCycles")
215        .desc("Number of cycles fetch has spent squashing")
216        .prereq(fetchSquashCycles);
217
218    fetchIdleCycles
219        .name(name() + ".IdleCycles")
220        .desc("Number of cycles fetch was idle")
221        .prereq(fetchIdleCycles);
222
223    fetchBlockedCycles
224        .name(name() + ".BlockedCycles")
225        .desc("Number of cycles fetch has spent blocked")
226        .prereq(fetchBlockedCycles);
227
228    fetchedCacheLines
229        .name(name() + ".CacheLines")
230        .desc("Number of cache lines fetched")
231        .prereq(fetchedCacheLines);
232
233    fetchMiscStallCycles
234        .name(name() + ".MiscStallCycles")
235        .desc("Number of cycles fetch has spent waiting on interrupts, or "
236              "bad addresses, or out of MSHRs")
237        .prereq(fetchMiscStallCycles);
238
239    fetchIcacheSquashes
240        .name(name() + ".IcacheSquashes")
241        .desc("Number of outstanding Icache misses that were squashed")
242        .prereq(fetchIcacheSquashes);
243
244    fetchNisnDist
245        .init(/* base value */ 0,
246              /* last value */ fetchWidth,
247              /* bucket size */ 1)
248        .name(name() + ".rateDist")
249        .desc("Number of instructions fetched each cycle (Total)")
250        .flags(Stats::pdf);
251
252    idleRate
253        .name(name() + ".idleRate")
254        .desc("Percent of cycles fetch was idle")
255        .prereq(idleRate);
256    idleRate = fetchIdleCycles * 100 / cpu->numCycles;
257
258    branchRate
259        .name(name() + ".branchRate")
260        .desc("Number of branch fetches per cycle")
261        .flags(Stats::total);
262    branchRate = fetchedBranches / cpu->numCycles;
263
264    fetchRate
265        .name(name() + ".rate")
266        .desc("Number of inst fetches per cycle")
267        .flags(Stats::total);
268    fetchRate = fetchedInsts / cpu->numCycles;
269
270    branchPred.regStats();
271}
272
273template<class Impl>
274void
275DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
276{
277    DPRINTF(Fetch, "Setting the CPU pointer.\n");
278    cpu = cpu_ptr;
279
280    // Name is finally available, so create the port.
281    icachePort = new IcachePort(this);
282
283#if USE_CHECKER
284    if (cpu->checker) {
285        cpu->checker->setIcachePort(icachePort);
286    }
287#endif
288
289    // Fetch needs to start fetching instructions at the very beginning,
290    // so it must start up in active state.
291    switchToActive();
292}
293
294template<class Impl>
295void
296DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
297{
298    DPRINTF(Fetch, "Setting the time buffer pointer.\n");
299    timeBuffer = time_buffer;
300
301    // Create wires to get information from proper places in time buffer.
302    fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
303    fromRename = timeBuffer->getWire(-renameToFetchDelay);
304    fromIEW = timeBuffer->getWire(-iewToFetchDelay);
305    fromCommit = timeBuffer->getWire(-commitToFetchDelay);
306}
307
308template<class Impl>
309void
310DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
311{
312    DPRINTF(Fetch, "Setting active threads list pointer.\n");
313    activeThreads = at_ptr;
314}
315
316template<class Impl>
317void
318DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
319{
320    DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
321    fetchQueue = fq_ptr;
322
323    // Create wire to write information to proper place in fetch queue.
324    toDecode = fetchQueue->getWire(0);
325}
326
327template<class Impl>
328void
329DefaultFetch<Impl>::initStage()
330{
331    // Setup PC and nextPC with initial state.
332    for (int tid = 0; tid < numThreads; tid++) {
333        PC[tid] = cpu->readPC(tid);
334        nextPC[tid] = cpu->readNextPC(tid);
335#if THE_ISA != ALPHA_ISA
336        nextNPC[tid] = cpu->readNextNPC(tid);
337#endif
338    }
339}
340
341template<class Impl>
342void
343DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
344{
345    unsigned tid = pkt->req->getThreadNum();
346
347    DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
348
349    // Only change the status if it's still waiting on the icache access
350    // to return.
351    if (fetchStatus[tid] != IcacheWaitResponse ||
352        pkt->req != memReq[tid] ||
353        isSwitchedOut()) {
354        ++fetchIcacheSquashes;
355        delete pkt->req;
356        delete pkt;
357        return;
358    }
359
360    if (!drainPending) {
361        // Wake up the CPU (if it went to sleep and was waiting on
362        // this completion event).
363        cpu->wakeCPU();
364
365        DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
366                tid);
367
368        switchToActive();
369    }
370
371    // Only switch to IcacheAccessComplete if we're not stalled as well.
372    if (checkStall(tid)) {
373        fetchStatus[tid] = Blocked;
374    } else {
375        fetchStatus[tid] = IcacheAccessComplete;
376    }
377
378    // Reset the mem req to NULL.
379    delete pkt->req;
380    delete pkt;
381    memReq[tid] = NULL;
382}
383
384template <class Impl>
385bool
386DefaultFetch<Impl>::drain()
387{
388    // Fetch is ready to drain at any time.
389    cpu->signalDrained();
390    drainPending = true;
391    return true;
392}
393
394template <class Impl>
395void
396DefaultFetch<Impl>::resume()
397{
398    drainPending = false;
399}
400
401template <class Impl>
402void
403DefaultFetch<Impl>::switchOut()
404{
405    switchedOut = true;
406    // Branch predictor needs to have its state cleared.
407    branchPred.switchOut();
408}
409
410template <class Impl>
411void
412DefaultFetch<Impl>::takeOverFrom()
413{
414    // Reset all state
415    for (int i = 0; i < Impl::MaxThreads; ++i) {
416        stalls[i].decode = 0;
417        stalls[i].rename = 0;
418        stalls[i].iew = 0;
419        stalls[i].commit = 0;
420        PC[i] = cpu->readPC(i);
421        nextPC[i] = cpu->readNextPC(i);
422#if THE_ISA != ALPHA_ISA
423        nextNPC[i] = cpu->readNextNPC(i);
424#endif
425        fetchStatus[i] = Running;
426    }
427    numInst = 0;
428    wroteToTimeBuffer = false;
429    _status = Inactive;
430    switchedOut = false;
431    branchPred.takeOverFrom();
432}
433
434template <class Impl>
435void
436DefaultFetch<Impl>::wakeFromQuiesce()
437{
438    DPRINTF(Fetch, "Waking up from quiesce\n");
439    // Hopefully this is safe
440    // @todo: Allow other threads to wake from quiesce.
441    fetchStatus[0] = Running;
442}
443
444template <class Impl>
445inline void
446DefaultFetch<Impl>::switchToActive()
447{
448    if (_status == Inactive) {
449        DPRINTF(Activity, "Activating stage.\n");
450
451        cpu->activateStage(O3CPU::FetchIdx);
452
453        _status = Active;
454    }
455}
456
457template <class Impl>
458inline void
459DefaultFetch<Impl>::switchToInactive()
460{
461    if (_status == Active) {
462        DPRINTF(Activity, "Deactivating stage.\n");
463
464        cpu->deactivateStage(O3CPU::FetchIdx);
465
466        _status = Inactive;
467    }
468}
469
470template <class Impl>
471bool
472DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
473{
474    // Do branch prediction check here.
475    // A bit of a misnomer...next_PC is actually the current PC until
476    // this function updates it.
477    bool predict_taken;
478
479    if (!inst->isControl()) {
480        next_PC = next_PC + instSize;
481        inst->setPredTarg(next_PC);
482        return false;
483    }
484
485    predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
486
487    ++fetchedBranches;
488
489    if (predict_taken) {
490        ++predictedBranches;
491    }
492
493    return predict_taken;
494}
495
496template <class Impl>
497bool
498DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
499{
500    Fault fault = NoFault;
501
502#if FULL_SYSTEM
503    // Flag to say whether or not address is physical addr.
504    unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
505#else
506    unsigned flags = 0;
507#endif // FULL_SYSTEM
508
509    if (cacheBlocked || (interruptPending && flags == 0)) {
510        // Hold off fetch from getting new instructions when:
511        // Cache is blocked, or
512        // while an interrupt is pending and we're not in PAL mode, or
513        // fetch is switched out.
514        return false;
515    }
516
517    // Align the fetch PC so it's at the start of a cache block.
518    fetch_PC = icacheBlockAlignPC(fetch_PC);
519
520    // If we've already got the block, no need to try to fetch it again.
521    if (fetch_PC == cacheDataPC[tid]) {
522        return true;
523    }
524
525    // Setup the memReq to do a read of the first instruction's address.
526    // Set the appropriate read size and flags as well.
527    // Build request here.
528    RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
529                                     fetch_PC, cpu->readCpuId(), tid);
530
531    memReq[tid] = mem_req;
532
533    // Translate the instruction request.
534    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
535
536    // In the case of faults, the fetch stage may need to stall and wait
537    // for the ITB miss to be handled.
538
539    // If translation was successful, attempt to read the first
540    // instruction.
541    if (fault == NoFault) {
542#if 0
543        if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
544            memReq[tid]->flags & UNCACHEABLE) {
545            DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
546                    "misspeculating path)!",
547                    memReq[tid]->paddr);
548            ret_fault = TheISA::genMachineCheckFault();
549            return false;
550        }
551#endif
552
553        // Build packet here.
554        PacketPtr data_pkt = new Packet(mem_req,
555                                        Packet::ReadReq, Packet::Broadcast);
556        data_pkt->dataStatic(cacheData[tid]);
557
558        cacheDataPC[tid] = fetch_PC;
559
560        DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
561
562        fetchedCacheLines++;
563
564        // Now do the timing access to see whether or not the instruction
565        // exists within the cache.
566        if (!icachePort->sendTiming(data_pkt)) {
567            assert(retryPkt == NULL);
568            assert(retryTid == -1);
569            DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
570            fetchStatus[tid] = IcacheWaitRetry;
571            retryPkt = data_pkt;
572            retryTid = tid;
573            cacheBlocked = true;
574            return false;
575        }
576
577        DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
578
579        lastIcacheStall[tid] = curTick;
580
581        DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
582                "response.\n", tid);
583
584        fetchStatus[tid] = IcacheWaitResponse;
585    } else {
586        delete mem_req;
587        memReq[tid] = NULL;
588    }
589
590    ret_fault = fault;
591    return true;
592}
593
594template <class Impl>
595inline void
596DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
597{
598    DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
599            tid, new_PC);
600
601    PC[tid] = new_PC;
602    nextPC[tid] = new_PC + instSize;
603
604    // Clear the icache miss if it's outstanding.
605    if (fetchStatus[tid] == IcacheWaitResponse) {
606        DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
607                tid);
608        memReq[tid] = NULL;
609    }
610
611    // Get rid of the retrying packet if it was from this thread.
612    if (retryTid == tid) {
613        assert(cacheBlocked);
614        cacheBlocked = false;
615        retryTid = -1;
616        retryPkt = NULL;
617        delete retryPkt->req;
618        delete retryPkt;
619    }
620
621    fetchStatus[tid] = Squashing;
622
623    ++fetchSquashCycles;
624}
625
626template<class Impl>
627void
628DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
629                                     const InstSeqNum &seq_num,
630                                     unsigned tid)
631{
632    DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
633
634    doSquash(new_PC, tid);
635
636    // Tell the CPU to remove any instructions that are in flight between
637    // fetch and decode.
638    cpu->removeInstsUntil(seq_num, tid);
639}
640
641template<class Impl>
642bool
643DefaultFetch<Impl>::checkStall(unsigned tid) const
644{
645    bool ret_val = false;
646
647    if (cpu->contextSwitch) {
648        DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
649        ret_val = true;
650    } else if (stalls[tid].decode) {
651        DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
652        ret_val = true;
653    } else if (stalls[tid].rename) {
654        DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
655        ret_val = true;
656    } else if (stalls[tid].iew) {
657        DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
658        ret_val = true;
659    } else if (stalls[tid].commit) {
660        DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
661        ret_val = true;
662    }
663
664    return ret_val;
665}
666
667template<class Impl>
668typename DefaultFetch<Impl>::FetchStatus
669DefaultFetch<Impl>::updateFetchStatus()
670{
671    //Check Running
672    list<unsigned>::iterator threads = (*activeThreads).begin();
673
674    while (threads != (*activeThreads).end()) {
675
676        unsigned tid = *threads++;
677
678        if (fetchStatus[tid] == Running ||
679            fetchStatus[tid] == Squashing ||
680            fetchStatus[tid] == IcacheAccessComplete) {
681
682            if (_status == Inactive) {
683                DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
684
685                if (fetchStatus[tid] == IcacheAccessComplete) {
686                    DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
687                            "completion\n",tid);
688                }
689
690                cpu->activateStage(O3CPU::FetchIdx);
691            }
692
693            return Active;
694        }
695    }
696
697    // Stage is switching from active to inactive, notify CPU of it.
698    if (_status == Active) {
699        DPRINTF(Activity, "Deactivating stage.\n");
700
701        cpu->deactivateStage(O3CPU::FetchIdx);
702    }
703
704    return Inactive;
705}
706
707template <class Impl>
708void
709DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
710{
711    DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
712
713    doSquash(new_PC, tid);
714
715    // Tell the CPU to remove any instructions that are not in the ROB.
716    cpu->removeInstsNotInROB(tid);
717}
718
719template <class Impl>
720void
721DefaultFetch<Impl>::tick()
722{
723    list<unsigned>::iterator threads = (*activeThreads).begin();
724    bool status_change = false;
725
726    wroteToTimeBuffer = false;
727
728    while (threads != (*activeThreads).end()) {
729        unsigned tid = *threads++;
730
731        // Check the signals for each thread to determine the proper status
732        // for each thread.
733        bool updated_status = checkSignalsAndUpdate(tid);
734        status_change =  status_change || updated_status;
735    }
736
737    DPRINTF(Fetch, "Running stage.\n");
738
739    // Reset the number of the instruction we're fetching.
740    numInst = 0;
741
742#if FULL_SYSTEM
743    if (fromCommit->commitInfo[0].interruptPending) {
744        interruptPending = true;
745    }
746
747    if (fromCommit->commitInfo[0].clearInterrupt) {
748        interruptPending = false;
749    }
750#endif
751
752    for (threadFetched = 0; threadFetched < numFetchingThreads;
753         threadFetched++) {
754        // Fetch each of the actively fetching threads.
755        fetch(status_change);
756    }
757
758    // Record number of instructions fetched this cycle for distribution.
759    fetchNisnDist.sample(numInst);
760
761    if (status_change) {
762        // Change the fetch stage status if there was a status change.
763        _status = updateFetchStatus();
764    }
765
766    // If there was activity this cycle, inform the CPU of it.
767    if (wroteToTimeBuffer || cpu->contextSwitch) {
768        DPRINTF(Activity, "Activity this cycle.\n");
769
770        cpu->activityThisCycle();
771    }
772}
773
774template <class Impl>
775bool
776DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
777{
778    // Update the per thread stall statuses.
779    if (fromDecode->decodeBlock[tid]) {
780        stalls[tid].decode = true;
781    }
782
783    if (fromDecode->decodeUnblock[tid]) {
784        assert(stalls[tid].decode);
785        assert(!fromDecode->decodeBlock[tid]);
786        stalls[tid].decode = false;
787    }
788
789    if (fromRename->renameBlock[tid]) {
790        stalls[tid].rename = true;
791    }
792
793    if (fromRename->renameUnblock[tid]) {
794        assert(stalls[tid].rename);
795        assert(!fromRename->renameBlock[tid]);
796        stalls[tid].rename = false;
797    }
798
799    if (fromIEW->iewBlock[tid]) {
800        stalls[tid].iew = true;
801    }
802
803    if (fromIEW->iewUnblock[tid]) {
804        assert(stalls[tid].iew);
805        assert(!fromIEW->iewBlock[tid]);
806        stalls[tid].iew = false;
807    }
808
809    if (fromCommit->commitBlock[tid]) {
810        stalls[tid].commit = true;
811    }
812
813    if (fromCommit->commitUnblock[tid]) {
814        assert(stalls[tid].commit);
815        assert(!fromCommit->commitBlock[tid]);
816        stalls[tid].commit = false;
817    }
818
819    // Check squash signals from commit.
820    if (fromCommit->commitInfo[tid].squash) {
821
822        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
823                "from commit.\n",tid);
824
825        // In any case, squash.
826        squash(fromCommit->commitInfo[tid].nextPC,tid);
827
828        // Also check if there's a mispredict that happened.
829        if (fromCommit->commitInfo[tid].branchMispredict) {
830            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
831                              fromCommit->commitInfo[tid].nextPC,
832                              fromCommit->commitInfo[tid].branchTaken,
833                              tid);
834        } else {
835            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
836                              tid);
837        }
838
839        return true;
840    } else if (fromCommit->commitInfo[tid].doneSeqNum) {
841        // Update the branch predictor if it wasn't a squashed instruction
842        // that was broadcasted.
843        branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
844    }
845
846    // Check ROB squash signals from commit.
847    if (fromCommit->commitInfo[tid].robSquashing) {
848        DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
849
850        // Continue to squash.
851        fetchStatus[tid] = Squashing;
852
853        return true;
854    }
855
856    // Check squash signals from decode.
857    if (fromDecode->decodeInfo[tid].squash) {
858        DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
859                "from decode.\n",tid);
860
861        // Update the branch predictor.
862        if (fromDecode->decodeInfo[tid].branchMispredict) {
863            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
864                              fromDecode->decodeInfo[tid].nextPC,
865                              fromDecode->decodeInfo[tid].branchTaken,
866                              tid);
867        } else {
868            branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
869                              tid);
870        }
871
872        if (fetchStatus[tid] != Squashing) {
873            // Squash unless we're already squashing
874            squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
875                             fromDecode->decodeInfo[tid].doneSeqNum,
876                             tid);
877
878            return true;
879        }
880    }
881
882    if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) {
883        DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
884
885        fetchStatus[tid] = Blocked;
886
887        return true;
888    }
889
890    if (fetchStatus[tid] == Blocked ||
891        fetchStatus[tid] == Squashing) {
892        // Switch status to running if fetch isn't being told to block or
893        // squash this cycle.
894        DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
895                tid);
896
897        fetchStatus[tid] = Running;
898
899        return true;
900    }
901
902    // If we've reached this point, we have not gotten any signals that
903    // cause fetch to change its status.  Fetch remains the same as before.
904    return false;
905}
906
907template<class Impl>
908void
909DefaultFetch<Impl>::fetch(bool &status_change)
910{
911    //////////////////////////////////////////
912    // Start actual fetch
913    //////////////////////////////////////////
914    int tid = getFetchingThread(fetchPolicy);
915
916    if (tid == -1 || drainPending) {
917        DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
918
919        // Breaks looping condition in tick()
920        threadFetched = numFetchingThreads;
921        return;
922    }
923
924    DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
925
926    // The current PC.
927    Addr &fetch_PC = PC[tid];
928
929    // Fault code for memory access.
930    Fault fault = NoFault;
931
932    // If returning from the delay of a cache miss, then update the status
933    // to running, otherwise do the cache access.  Possibly move this up
934    // to tick() function.
935    if (fetchStatus[tid] == IcacheAccessComplete) {
936        DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
937                tid);
938
939        fetchStatus[tid] = Running;
940        status_change = true;
941    } else if (fetchStatus[tid] == Running) {
942        DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
943                "instruction, starting at PC %08p.\n",
944                tid, fetch_PC);
945
946        bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
947        if (!fetch_success) {
948            if (cacheBlocked) {
949                ++icacheStallCycles;
950            } else {
951                ++fetchMiscStallCycles;
952            }
953            return;
954        }
955    } else {
956        if (fetchStatus[tid] == Idle) {
957            ++fetchIdleCycles;
958        } else if (fetchStatus[tid] == Blocked) {
959            ++fetchBlockedCycles;
960        } else if (fetchStatus[tid] == Squashing) {
961            ++fetchSquashCycles;
962        } else if (fetchStatus[tid] == IcacheWaitResponse) {
963            ++icacheStallCycles;
964        }
965
966        // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so
967        // fetch should do nothing.
968        return;
969    }
970
971    ++fetchCycles;
972
973    // If we had a stall due to an icache miss, then return.
974    if (fetchStatus[tid] == IcacheWaitResponse) {
975        ++icacheStallCycles;
976        status_change = true;
977        return;
978    }
979
980    Addr next_PC = fetch_PC;
981    InstSeqNum inst_seq;
982    MachInst inst;
983    ExtMachInst ext_inst;
984    // @todo: Fix this hack.
985    unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
986
987    if (fault == NoFault) {
988        // If the read of the first instruction was successful, then grab the
989        // instructions from the rest of the cache line and put them into the
990        // queue heading to decode.
991
992        DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
993                "decode.\n",tid);
994
995        // Need to keep track of whether or not a predicted branch
996        // ended this fetch block.
997        bool predicted_branch = false;
998
999        for (;
1000             offset < cacheBlkSize &&
1001                 numInst < fetchWidth &&
1002                 !predicted_branch;
1003             ++numInst) {
1004
1005            // Get a sequence number.
1006            inst_seq = cpu->getAndIncrementInstSeq();
1007
1008            // Make sure this is a valid index.
1009            assert(offset <= cacheBlkSize - instSize);
1010
1011            // Get the instruction from the array of the cache line.
1012            inst = gtoh(*reinterpret_cast<MachInst *>
1013                        (&cacheData[tid][offset]));
1014
1015            ext_inst = TheISA::makeExtMI(inst, fetch_PC);
1016
1017            // Create a new DynInst from the instruction fetched.
1018            DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1019                                                 next_PC,
1020                                                 inst_seq, cpu);
1021            instruction->setTid(tid);
1022
1023            instruction->setASID(tid);
1024
1025            instruction->setThreadState(cpu->thread[tid]);
1026
1027            DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
1028                    "[sn:%lli]\n",
1029                    tid, instruction->readPC(), inst_seq);
1030
1031            DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
1032                    tid, instruction->staticInst->disassemble(fetch_PC));
1033
1034            instruction->traceData =
1035                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
1036                                     instruction->staticInst,
1037                                     instruction->readPC(),tid);
1038
1039            predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
1040
1041            // Add instruction to the CPU's list of instructions.
1042            instruction->setInstListIt(cpu->addInst(instruction));
1043
1044            // Write the instruction to the first slot in the queue
1045            // that heads to decode.
1046            toDecode->insts[numInst] = instruction;
1047
1048            toDecode->size++;
1049
1050            // Increment stat of fetched instructions.
1051            ++fetchedInsts;
1052
1053            // Move to the next instruction, unless we have a branch.
1054            fetch_PC = next_PC;
1055
1056            if (instruction->isQuiesce()) {
1057                warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
1058                     curTick);
1059                fetchStatus[tid] = QuiescePending;
1060                ++numInst;
1061                status_change = true;
1062                break;
1063            }
1064
1065            offset+= instSize;
1066        }
1067    }
1068
1069    if (numInst > 0) {
1070        wroteToTimeBuffer = true;
1071    }
1072
1073    // Now that fetching is completed, update the PC to signify what the next
1074    // cycle will be.
1075    if (fault == NoFault) {
1076        DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
1077
1078#if THE_ISA == ALPHA_ISA
1079        PC[tid] = next_PC;
1080        nextPC[tid] = next_PC + instSize;
1081#else
1082        PC[tid] = next_PC;
1083        nextPC[tid] = next_PC + instSize;
1084        nextPC[tid] = next_PC + instSize;
1085
1086        thread->setNextPC(thread->readNextNPC());
1087        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
1088#endif
1089    } else {
1090        // We shouldn't be in an icache miss and also have a fault (an ITB
1091        // miss)
1092        if (fetchStatus[tid] == IcacheWaitResponse) {
1093            panic("Fetch should have exited prior to this!");
1094        }
1095
1096        // Send the fault to commit.  This thread will not do anything
1097        // until commit handles the fault.  The only other way it can
1098        // wake up is if a squash comes along and changes the PC.
1099#if FULL_SYSTEM
1100        assert(numInst != fetchWidth);
1101        // Get a sequence number.
1102        inst_seq = cpu->getAndIncrementInstSeq();
1103        // We will use a nop in order to carry the fault.
1104        ext_inst = TheISA::NoopMachInst;
1105
1106        // Create a new DynInst from the dummy nop.
1107        DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
1108                                             next_PC,
1109                                             inst_seq, cpu);
1110        instruction->setPredTarg(next_PC + instSize);
1111        instruction->setTid(tid);
1112
1113        instruction->setASID(tid);
1114
1115        instruction->setThreadState(cpu->thread[tid]);
1116
1117        instruction->traceData = NULL;
1118
1119        instruction->setInstListIt(cpu->addInst(instruction));
1120
1121        instruction->fault = fault;
1122
1123        toDecode->insts[numInst] = instruction;
1124        toDecode->size++;
1125
1126        DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
1127
1128        fetchStatus[tid] = TrapPending;
1129        status_change = true;
1130
1131        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1132#else // !FULL_SYSTEM
1133        warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
1134#endif // FULL_SYSTEM
1135    }
1136}
1137
1138template<class Impl>
1139void
1140DefaultFetch<Impl>::recvRetry()
1141{
1142    assert(cacheBlocked);
1143    if (retryPkt != NULL) {
1144        assert(retryTid != -1);
1145        assert(fetchStatus[retryTid] == IcacheWaitRetry);
1146
1147        if (icachePort->sendTiming(retryPkt)) {
1148            fetchStatus[retryTid] = IcacheWaitResponse;
1149            retryPkt = NULL;
1150            retryTid = -1;
1151            cacheBlocked = false;
1152        }
1153    } else {
1154        assert(retryTid == -1);
1155        // Access has been squashed since it was sent out.  Just clear
1156        // the cache being blocked.
1157        cacheBlocked = false;
1158    }
1159}
1160
1161///////////////////////////////////////
1162//                                   //
1163//  SMT FETCH POLICY MAINTAINED HERE //
1164//                                   //
1165///////////////////////////////////////
1166template<class Impl>
1167int
1168DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
1169{
1170    if (numThreads > 1) {
1171        switch (fetch_priority) {
1172
1173          case SingleThread:
1174            return 0;
1175
1176          case RoundRobin:
1177            return roundRobin();
1178
1179          case IQ:
1180            return iqCount();
1181
1182          case LSQ:
1183            return lsqCount();
1184
1185          case Branch:
1186            return branchCount();
1187
1188          default:
1189            return -1;
1190        }
1191    } else {
1192        int tid = *((*activeThreads).begin());
1193
1194        if (fetchStatus[tid] == Running ||
1195            fetchStatus[tid] == IcacheAccessComplete ||
1196            fetchStatus[tid] == Idle) {
1197            return tid;
1198        } else {
1199            return -1;
1200        }
1201    }
1202
1203}
1204
1205
1206template<class Impl>
1207int
1208DefaultFetch<Impl>::roundRobin()
1209{
1210    list<unsigned>::iterator pri_iter = priorityList.begin();
1211    list<unsigned>::iterator end      = priorityList.end();
1212
1213    int high_pri;
1214
1215    while (pri_iter != end) {
1216        high_pri = *pri_iter;
1217
1218        assert(high_pri <= numThreads);
1219
1220        if (fetchStatus[high_pri] == Running ||
1221            fetchStatus[high_pri] == IcacheAccessComplete ||
1222            fetchStatus[high_pri] == Idle) {
1223
1224            priorityList.erase(pri_iter);
1225            priorityList.push_back(high_pri);
1226
1227            return high_pri;
1228        }
1229
1230        pri_iter++;
1231    }
1232
1233    return -1;
1234}
1235
1236template<class Impl>
1237int
1238DefaultFetch<Impl>::iqCount()
1239{
1240    priority_queue<unsigned> PQ;
1241
1242    list<unsigned>::iterator threads = (*activeThreads).begin();
1243
1244    while (threads != (*activeThreads).end()) {
1245        unsigned tid = *threads++;
1246
1247        PQ.push(fromIEW->iewInfo[tid].iqCount);
1248    }
1249
1250    while (!PQ.empty()) {
1251
1252        unsigned high_pri = PQ.top();
1253
1254        if (fetchStatus[high_pri] == Running ||
1255            fetchStatus[high_pri] == IcacheAccessComplete ||
1256            fetchStatus[high_pri] == Idle)
1257            return high_pri;
1258        else
1259            PQ.pop();
1260
1261    }
1262
1263    return -1;
1264}
1265
1266template<class Impl>
1267int
1268DefaultFetch<Impl>::lsqCount()
1269{
1270    priority_queue<unsigned> PQ;
1271
1272
1273    list<unsigned>::iterator threads = (*activeThreads).begin();
1274
1275    while (threads != (*activeThreads).end()) {
1276        unsigned tid = *threads++;
1277
1278        PQ.push(fromIEW->iewInfo[tid].ldstqCount);
1279    }
1280
1281    while (!PQ.empty()) {
1282
1283        unsigned high_pri = PQ.top();
1284
1285        if (fetchStatus[high_pri] == Running ||
1286            fetchStatus[high_pri] == IcacheAccessComplete ||
1287            fetchStatus[high_pri] == Idle)
1288            return high_pri;
1289        else
1290            PQ.pop();
1291
1292    }
1293
1294    return -1;
1295}
1296
1297template<class Impl>
1298int
1299DefaultFetch<Impl>::branchCount()
1300{
1301    list<unsigned>::iterator threads = (*activeThreads).begin();
1302    panic("Branch Count Fetch policy unimplemented\n");
1303    return *threads;
1304}
1305