fetch.hh revision 8541
11689SN/A/* 27849SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 478229Snate@binkert.org#include "arch/predecoder.hh" 482669Sktlim@umich.edu#include "arch/utility.hh" 491461SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 518541Sgblack@eecs.umich.edu#include "cpu/decode.hh" 521060SN/A#include "cpu/pc_event.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 547849SAli.Saidi@ARM.com#include "cpu/translation.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 562669Sktlim@umich.edu#include "mem/port.hh" 571461SN/A#include "sim/eventq.hh" 581060SN/A 595529Snate@binkert.orgclass DerivO3CPUParams; 605529Snate@binkert.org 611060SN/A/** 622329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 632329SN/A * width is specified by the parameters; each cycle it tries to fetch 642329SN/A * that many instructions. It supports using a branch predictor to 652329SN/A * predict direction and targets. 662348SN/A * It supports the idling functionality of the CPU by indicating to 672329SN/A * the CPU when it is active and inactive. 681060SN/A */ 691060SN/Atemplate <class Impl> 702292SN/Aclass DefaultFetch 711060SN/A{ 721060SN/A public: 731060SN/A /** Typedefs from Impl. */ 741061SN/A typedef typename Impl::CPUPol CPUPol; 751060SN/A typedef typename Impl::DynInst DynInst; 761061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 772733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 781060SN/A 792292SN/A /** Typedefs from the CPU policy. */ 801061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 811061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 821061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 831060SN/A 841060SN/A /** Typedefs from ISA. */ 852107SN/A typedef TheISA::MachInst MachInst; 862292SN/A typedef TheISA::ExtMachInst ExtMachInst; 872632Sstever@eecs.umich.edu 882698Sktlim@umich.edu /** IcachePort class for DefaultFetch. Handles doing the 892698Sktlim@umich.edu * communication with the cache/memory. 902698Sktlim@umich.edu */ 912669Sktlim@umich.edu class IcachePort : public Port 922669Sktlim@umich.edu { 932669Sktlim@umich.edu protected: 942698Sktlim@umich.edu /** Pointer to fetch. */ 952669Sktlim@umich.edu DefaultFetch<Impl> *fetch; 962669Sktlim@umich.edu 972669Sktlim@umich.edu public: 982698Sktlim@umich.edu /** Default constructor. */ 995494Sstever@gmail.com IcachePort(DefaultFetch<Impl> *_fetch) 1005606Snate@binkert.org : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) 1012669Sktlim@umich.edu { } 1022669Sktlim@umich.edu 1033647Srdreslin@umich.edu bool snoopRangeSent; 1043647Srdreslin@umich.edu 1054302Sktlim@umich.edu virtual void setPeer(Port *port); 1064302Sktlim@umich.edu 1072669Sktlim@umich.edu protected: 1082698Sktlim@umich.edu /** Atomic version of receive. Panics. */ 1092669Sktlim@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1102669Sktlim@umich.edu 1112698Sktlim@umich.edu /** Functional version of receive. Panics. */ 1122669Sktlim@umich.edu virtual void recvFunctional(PacketPtr pkt); 1132669Sktlim@umich.edu 1142698Sktlim@umich.edu /** Receives status change. Other than range changing, panics. */ 1152669Sktlim@umich.edu virtual void recvStatusChange(Status status); 1162669Sktlim@umich.edu 1172698Sktlim@umich.edu /** Returns the address ranges of this device. */ 1182669Sktlim@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1194475Sstever@eecs.umich.edu bool &snoop) 1204475Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 1212669Sktlim@umich.edu 1222698Sktlim@umich.edu /** Timing version of receive. Handles setting fetch to the 1232698Sktlim@umich.edu * proper status to start fetching. */ 1242669Sktlim@umich.edu virtual bool recvTiming(PacketPtr pkt); 1252669Sktlim@umich.edu 1262698Sktlim@umich.edu /** Handles doing a retry of a failed fetch. */ 1272669Sktlim@umich.edu virtual void recvRetry(); 1282669Sktlim@umich.edu }; 1291060SN/A 1307849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 1317849SAli.Saidi@ARM.com { 1327849SAli.Saidi@ARM.com protected: 1337849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 1347849SAli.Saidi@ARM.com 1357849SAli.Saidi@ARM.com public: 1367849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 1377849SAli.Saidi@ARM.com : fetch(_fetch) 1387849SAli.Saidi@ARM.com {} 1397849SAli.Saidi@ARM.com 1407849SAli.Saidi@ARM.com void 1417944SGiacomo.Gabrielli@arm.com markDelayed() 1427944SGiacomo.Gabrielli@arm.com {} 1437944SGiacomo.Gabrielli@arm.com 1447944SGiacomo.Gabrielli@arm.com void 1457849SAli.Saidi@ARM.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 1467849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1477849SAli.Saidi@ARM.com { 1487849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1497849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1507849SAli.Saidi@ARM.com delete this; 1517849SAli.Saidi@ARM.com } 1527849SAli.Saidi@ARM.com }; 1532935Sksewell@umich.edu 1548462Sgeoffrey.blake@arm.com private: 1558462Sgeoffrey.blake@arm.com /* Event to delay delivery of a fetch translation result in case of 1568462Sgeoffrey.blake@arm.com * a fault and the nop to carry the fault cannot be generated 1578462Sgeoffrey.blake@arm.com * immediately */ 1588462Sgeoffrey.blake@arm.com class FinishTranslationEvent : public Event 1598462Sgeoffrey.blake@arm.com { 1608462Sgeoffrey.blake@arm.com private: 1618462Sgeoffrey.blake@arm.com DefaultFetch<Impl> *fetch; 1628462Sgeoffrey.blake@arm.com Fault fault; 1638462Sgeoffrey.blake@arm.com RequestPtr req; 1648462Sgeoffrey.blake@arm.com 1658462Sgeoffrey.blake@arm.com public: 1668462Sgeoffrey.blake@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1678462Sgeoffrey.blake@arm.com : fetch(_fetch) 1688462Sgeoffrey.blake@arm.com {} 1698462Sgeoffrey.blake@arm.com 1708462Sgeoffrey.blake@arm.com void setFault(Fault _fault) 1718462Sgeoffrey.blake@arm.com { 1728462Sgeoffrey.blake@arm.com fault = _fault; 1738462Sgeoffrey.blake@arm.com } 1748462Sgeoffrey.blake@arm.com 1758462Sgeoffrey.blake@arm.com void setReq(RequestPtr _req) 1768462Sgeoffrey.blake@arm.com { 1778462Sgeoffrey.blake@arm.com req = _req; 1788462Sgeoffrey.blake@arm.com } 1798462Sgeoffrey.blake@arm.com 1808462Sgeoffrey.blake@arm.com /** Process the delayed finish translation */ 1818462Sgeoffrey.blake@arm.com void process() 1828462Sgeoffrey.blake@arm.com { 1838462Sgeoffrey.blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1848462Sgeoffrey.blake@arm.com fetch->finishTranslation(fault, req); 1858462Sgeoffrey.blake@arm.com } 1868462Sgeoffrey.blake@arm.com 1878462Sgeoffrey.blake@arm.com const char *description() const 1888462Sgeoffrey.blake@arm.com { 1898462Sgeoffrey.blake@arm.com return "FullO3CPU FetchFinishTranslation"; 1908462Sgeoffrey.blake@arm.com } 1918462Sgeoffrey.blake@arm.com }; 1928462Sgeoffrey.blake@arm.com 1931060SN/A public: 1942329SN/A /** Overall fetch status. Used to determine if the CPU can 1952329SN/A * deschedule itsef due to a lack of activity. 1962292SN/A */ 1972292SN/A enum FetchStatus { 1982292SN/A Active, 1992292SN/A Inactive 2002292SN/A }; 2012292SN/A 2022292SN/A /** Individual thread status. */ 2032292SN/A enum ThreadStatus { 2041060SN/A Running, 2051060SN/A Idle, 2061060SN/A Squashing, 2071060SN/A Blocked, 2082292SN/A Fetching, 2092292SN/A TrapPending, 2102292SN/A QuiescePending, 2112307SN/A SwitchOut, 2127849SAli.Saidi@ARM.com ItlbWait, 2132669Sktlim@umich.edu IcacheWaitResponse, 2142696Sktlim@umich.edu IcacheWaitRetry, 2158460SAli.Saidi@ARM.com IcacheAccessComplete, 2168460SAli.Saidi@ARM.com NoGoodAddr 2171060SN/A }; 2181060SN/A 2192292SN/A /** Fetching Policy, Add new policies here.*/ 2202292SN/A enum FetchPriority { 2212292SN/A SingleThread, 2222292SN/A RoundRobin, 2232292SN/A Branch, 2242292SN/A IQ, 2252292SN/A LSQ 2262292SN/A }; 2271060SN/A 2282292SN/A private: 2292292SN/A /** Fetch status. */ 2302292SN/A FetchStatus _status; 2312292SN/A 2322292SN/A /** Per-thread status. */ 2332292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 2342292SN/A 2352292SN/A /** Fetch policy. */ 2362292SN/A FetchPriority fetchPolicy; 2372292SN/A 2382292SN/A /** List that has the threads organized by priority. */ 2396221Snate@binkert.org std::list<ThreadID> priorityList; 2401060SN/A 2411060SN/A public: 2422292SN/A /** DefaultFetch constructor. */ 2435529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2441684SN/A 2452292SN/A /** Returns the name of fetch. */ 2462292SN/A std::string name() const; 2471684SN/A 2482292SN/A /** Registers statistics. */ 2491062SN/A void regStats(); 2501062SN/A 2512871Sktlim@umich.edu /** Returns the icache port. */ 2522871Sktlim@umich.edu Port *getIcachePort() { return icachePort; } 2532871Sktlim@umich.edu 2542292SN/A /** Sets the main backwards communication time buffer pointer. */ 2551060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2561060SN/A 2572292SN/A /** Sets pointer to list of active threads. */ 2586221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2592292SN/A 2602292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2611060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2621060SN/A 2632292SN/A /** Initialize stage. */ 2642292SN/A void initStage(); 2652292SN/A 2664302Sktlim@umich.edu /** Tells the fetch stage that the Icache is set. */ 2674302Sktlim@umich.edu void setIcache(); 2684302Sktlim@umich.edu 2692292SN/A /** Processes cache completion event. */ 2702669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2712292SN/A 2722843Sktlim@umich.edu /** Begins the drain of the fetch stage. */ 2732863Sktlim@umich.edu bool drain(); 2742843Sktlim@umich.edu 2752843Sktlim@umich.edu /** Resumes execution after a drain. */ 2762843Sktlim@umich.edu void resume(); 2772843Sktlim@umich.edu 2782843Sktlim@umich.edu /** Tells fetch stage to prepare to be switched out. */ 2792307SN/A void switchOut(); 2802307SN/A 2812348SN/A /** Takes over from another CPU's thread. */ 2822307SN/A void takeOverFrom(); 2832307SN/A 2842348SN/A /** Checks if the fetch stage is switched out. */ 2852307SN/A bool isSwitchedOut() { return switchedOut; } 2862307SN/A 2872348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2882292SN/A void wakeFromQuiesce(); 2891060SN/A 2901061SN/A private: 2912329SN/A /** Changes the status of this stage to active, and indicates this 2922329SN/A * to the CPU. 2932292SN/A */ 2942292SN/A inline void switchToActive(); 2952292SN/A 2962329SN/A /** Changes the status of this stage to inactive, and indicates 2972329SN/A * this to the CPU. 2982292SN/A */ 2992292SN/A inline void switchToInactive(); 3002292SN/A 3011061SN/A /** 3021061SN/A * Looks up in the branch predictor to see if the next PC should be 3031061SN/A * either next PC+=MachInst or a branch target. 3041763SN/A * @param next_PC Next PC variable passed in by reference. It is 3051061SN/A * expected to be set to the current PC; it will be updated with what 3061061SN/A * the next PC will be. 3072935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 3081061SN/A * @return Whether or not a branch was predicted as taken. 3091061SN/A */ 3107720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 3111062SN/A 3121062SN/A /** 3131062SN/A * Fetches the cache line that contains fetch_PC. Returns any 3141062SN/A * fault that happened. Puts the data into the class variable 3151062SN/A * cacheData. 3167764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 3172292SN/A * @param ret_fault The fault reference that will be set to the result of 3182292SN/A * the icache access. 3192292SN/A * @param tid Thread id. 3207764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 3211062SN/A * @return Any fault that occured. 3221062SN/A */ 3237849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 3247849SAli.Saidi@ARM.com void finishTranslation(Fault fault, RequestPtr mem_req); 3251062SN/A 3267847Sminkyu.jeong@arm.com 3277847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 3287847Sminkyu.jeong@arm.com */ 3297847Sminkyu.jeong@arm.com bool 3307847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 3317847Sminkyu.jeong@arm.com { 3327847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 3337847Sminkyu.jeong@arm.com } 3347847Sminkyu.jeong@arm.com 3352292SN/A /** Squashes a specific thread and resets the PC. */ 3368503Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, 3378503Sgblack@eecs.umich.edu const DynInstPtr squashInst, ThreadID tid); 3381684SN/A 3392292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3402292SN/A * remove any instructions between fetch and decode that should be sqaushed. 3412292SN/A */ 3427720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3438503Sgblack@eecs.umich.edu const DynInstPtr squashInst, 3448503Sgblack@eecs.umich.edu const InstSeqNum seq_num, ThreadID tid); 3452292SN/A 3462292SN/A /** Checks if a thread is stalled. */ 3476221Snate@binkert.org bool checkStall(ThreadID tid) const; 3482292SN/A 3492292SN/A /** Updates overall fetch stage status; to be called at the end of each 3502292SN/A * cycle. */ 3512292SN/A FetchStatus updateFetchStatus(); 3521684SN/A 3531684SN/A public: 3542292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3552292SN/A * remove any instructions that are not in the ROB. The source of this 3562292SN/A * squash should be the commit stage. 3572292SN/A */ 3588503Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3598503Sgblack@eecs.umich.edu DynInstPtr squashInst, ThreadID tid); 3601684SN/A 3612292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3622292SN/A * as many instructions as possible. 3632292SN/A */ 3641684SN/A void tick(); 3651684SN/A 3662292SN/A /** Checks all input signals and updates the status as necessary. 3672292SN/A * @return: Returns if the status has changed due to input signals. 3682292SN/A */ 3696221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3701684SN/A 3712292SN/A /** Does the actual fetching of instructions and passing them on to the 3722292SN/A * next stage. 3732292SN/A * @param status_change fetch() sets this variable if there was a status 3742292SN/A * change (ie switching to IcacheMissStall). 3752292SN/A */ 3762292SN/A void fetch(bool &status_change); 3772292SN/A 3782292SN/A /** Align a PC to the start of an I-cache block. */ 3791062SN/A Addr icacheBlockAlignPC(Addr addr) 3801062SN/A { 3811062SN/A return (addr & ~(cacheBlkMask)); 3821062SN/A } 3831061SN/A 3848541Sgblack@eecs.umich.edu /** The decoder. */ 3858541Sgblack@eecs.umich.edu Decoder decoder; 3868541Sgblack@eecs.umich.edu 3871060SN/A private: 3887764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3897764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3907764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3917764Sgblack@eecs.umich.edu 3922698Sktlim@umich.edu /** Handles retrying the fetch access. */ 3932696Sktlim@umich.edu void recvRetry(); 3942696Sktlim@umich.edu 3952292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3966221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3972292SN/A 3982292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3996221Snate@binkert.org ThreadID roundRobin(); 4002292SN/A 4012292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 4026221Snate@binkert.org ThreadID iqCount(); 4032292SN/A 4042292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 4056221Snate@binkert.org ThreadID lsqCount(); 4062292SN/A 4076221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 4086221Snate@binkert.org * policy. */ 4096221Snate@binkert.org ThreadID branchCount(); 4102292SN/A 4118462Sgeoffrey.blake@arm.com /** Pipeline the next I-cache access to the current one. */ 4128462Sgeoffrey.blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 4138462Sgeoffrey.blake@arm.com 4148462Sgeoffrey.blake@arm.com /** Profile the reasons of fetch stall. */ 4158462Sgeoffrey.blake@arm.com void profileStall(ThreadID tid); 4168462Sgeoffrey.blake@arm.com 4172292SN/A private: 4182733Sktlim@umich.edu /** Pointer to the O3CPU. */ 4192733Sktlim@umich.edu O3CPU *cpu; 4201060SN/A 4211060SN/A /** Time buffer interface. */ 4221060SN/A TimeBuffer<TimeStruct> *timeBuffer; 4231060SN/A 4241060SN/A /** Wire to get decode's information from backwards time buffer. */ 4251060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 4261060SN/A 4271060SN/A /** Wire to get rename's information from backwards time buffer. */ 4281060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 4291060SN/A 4301060SN/A /** Wire to get iew's information from backwards time buffer. */ 4311060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 4321060SN/A 4331060SN/A /** Wire to get commit's information from backwards time buffer. */ 4341060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 4351060SN/A 4361060SN/A /** Internal fetch instruction queue. */ 4371060SN/A TimeBuffer<FetchStruct> *fetchQueue; 4381060SN/A 4391060SN/A //Might be annoying how this name is different than the queue. 4401060SN/A /** Wire used to write any information heading to decode. */ 4411060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 4421060SN/A 4431060SN/A /** Icache interface. */ 4442669Sktlim@umich.edu IcachePort *icachePort; 4451060SN/A 4461061SN/A /** BPredUnit. */ 4471061SN/A BPredUnit branchPred; 4481061SN/A 4494182Sgblack@eecs.umich.edu /** Predecoder. */ 4504182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 4514182Sgblack@eecs.umich.edu 4527720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4532292SN/A 4547764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4557764Sgblack@eecs.umich.edu 4567764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4577764Sgblack@eecs.umich.edu 4588314Sgeoffrey.blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4598314Sgeoffrey.blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4608314Sgeoffrey.blake@arm.com 4612678Sktlim@umich.edu /** Memory request used to access cache. */ 4622678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4632292SN/A 4642292SN/A /** Variable that tracks if fetch has written to the time buffer this 4652292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4662292SN/A */ 4672292SN/A bool wroteToTimeBuffer; 4682292SN/A 4692292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4702292SN/A int numInst; 4712292SN/A 4722292SN/A /** Source of possible stalls. */ 4732292SN/A struct Stalls { 4742292SN/A bool decode; 4752292SN/A bool rename; 4762292SN/A bool iew; 4772292SN/A bool commit; 4782292SN/A }; 4792292SN/A 4802292SN/A /** Tracks which stages are telling fetch to stall. */ 4812292SN/A Stalls stalls[Impl::MaxThreads]; 4821060SN/A 4831060SN/A /** Decode to fetch delay, in ticks. */ 4841060SN/A unsigned decodeToFetchDelay; 4851060SN/A 4861060SN/A /** Rename to fetch delay, in ticks. */ 4871060SN/A unsigned renameToFetchDelay; 4881060SN/A 4891060SN/A /** IEW to fetch delay, in ticks. */ 4901060SN/A unsigned iewToFetchDelay; 4911060SN/A 4921060SN/A /** Commit to fetch delay, in ticks. */ 4931060SN/A unsigned commitToFetchDelay; 4941060SN/A 4951060SN/A /** The width of fetch in instructions. */ 4961060SN/A unsigned fetchWidth; 4971060SN/A 4982696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4992696Sktlim@umich.edu bool cacheBlocked; 5002696Sktlim@umich.edu 5012696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 5022696Sktlim@umich.edu PacketPtr retryPkt; 5032696Sktlim@umich.edu 5042696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 5056221Snate@binkert.org ThreadID retryTid; 5062696Sktlim@umich.edu 5071060SN/A /** Cache block size. */ 5081062SN/A int cacheBlkSize; 5091060SN/A 5101060SN/A /** Mask to get a cache block's address. */ 5111062SN/A Addr cacheBlkMask; 5121060SN/A 5131062SN/A /** The cache line being fetched. */ 5142292SN/A uint8_t *cacheData[Impl::MaxThreads]; 5151060SN/A 5162893Sktlim@umich.edu /** The PC of the cacheline that has been loaded. */ 5172893Sktlim@umich.edu Addr cacheDataPC[Impl::MaxThreads]; 5182893Sktlim@umich.edu 5192906Sktlim@umich.edu /** Whether or not the cache data is valid. */ 5202906Sktlim@umich.edu bool cacheDataValid[Impl::MaxThreads]; 5212906Sktlim@umich.edu 5221060SN/A /** Size of instructions. */ 5231060SN/A int instSize; 5241060SN/A 5251060SN/A /** Icache stall statistics. */ 5262292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 5271062SN/A 5282292SN/A /** List of Active Threads */ 5296221Snate@binkert.org std::list<ThreadID> *activeThreads; 5302292SN/A 5312292SN/A /** Number of threads. */ 5326221Snate@binkert.org ThreadID numThreads; 5332292SN/A 5342292SN/A /** Number of threads that are actively fetching. */ 5356221Snate@binkert.org ThreadID numFetchingThreads; 5362292SN/A 5372292SN/A /** Thread ID being fetched. */ 5386221Snate@binkert.org ThreadID threadFetched; 5392292SN/A 5402348SN/A /** Checks if there is an interrupt pending. If there is, fetch 5412348SN/A * must stop once it is not fetching PAL instructions. 5422348SN/A */ 5432292SN/A bool interruptPending; 5442292SN/A 5452843Sktlim@umich.edu /** Is there a drain pending. */ 5462843Sktlim@umich.edu bool drainPending; 5472843Sktlim@umich.edu 5482348SN/A /** Records if fetch is switched out. */ 5492307SN/A bool switchedOut; 5502307SN/A 5518462Sgeoffrey.blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5528462Sgeoffrey.blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5538462Sgeoffrey.blake@arm.com 5548462Sgeoffrey.blake@arm.com /** Event used to delay fault generation of translation faults */ 5558462Sgeoffrey.blake@arm.com FinishTranslationEvent finishTranslationEvent; 5568462Sgeoffrey.blake@arm.com 5572292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 5582292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 5595999Snate@binkert.org Stats::Scalar icacheStallCycles; 5602292SN/A /** Stat for total number of fetched instructions. */ 5615999Snate@binkert.org Stats::Scalar fetchedInsts; 5622727Sktlim@umich.edu /** Total number of fetched branches. */ 5635999Snate@binkert.org Stats::Scalar fetchedBranches; 5642292SN/A /** Stat for total number of predicted branches. */ 5655999Snate@binkert.org Stats::Scalar predictedBranches; 5662292SN/A /** Stat for total number of cycles spent fetching. */ 5675999Snate@binkert.org Stats::Scalar fetchCycles; 5682292SN/A /** Stat for total number of cycles spent squashing. */ 5695999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5707849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5717849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5722292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5732292SN/A * the pipeline. 5742292SN/A */ 5755999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5762348SN/A /** Total number of cycles spent blocked. */ 5775999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5782348SN/A /** Total number of cycles spent in any other state. */ 5795999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5808462Sgeoffrey.blake@arm.com /** Total number of cycles spent in waiting for drains. */ 5818462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingDrainCycles; 5828462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by no active threads to run. */ 5838462Sgeoffrey.blake@arm.com Stats::Scalar fetchNoActiveThreadStallCycles; 5848462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending traps. */ 5858462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingTrapStallCycles; 5868462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending quiesce instructions. */ 5878462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingQuiesceStallCycles; 5888462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by I-cache wait retrys. */ 5898462Sgeoffrey.blake@arm.com Stats::Scalar fetchIcacheWaitRetryStallCycles; 5902292SN/A /** Stat for total number of fetched cache lines. */ 5915999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5922348SN/A /** Total number of outstanding icache accesses that were dropped 5932348SN/A * due to a squash. 5942348SN/A */ 5955999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5968064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5978064SAli.Saidi@ARM.com * due to a squash. 5988064SAli.Saidi@ARM.com */ 5998064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 6002292SN/A /** Distribution of number of instructions fetched each cycle. */ 6015999Snate@binkert.org Stats::Distribution fetchNisnDist; 6022348SN/A /** Rate of how often fetch was idle. */ 6032292SN/A Stats::Formula idleRate; 6042348SN/A /** Number of branch fetches per cycle. */ 6052292SN/A Stats::Formula branchRate; 6062348SN/A /** Number of instruction fetched per cycle. */ 6072292SN/A Stats::Formula fetchRate; 6081060SN/A}; 6091060SN/A 6102292SN/A#endif //__CPU_O3_FETCH_HH__ 611