fetch.hh revision 8541 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/predecoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/decode.hh"
52#include "cpu/pc_event.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58
59class DerivO3CPUParams;
60
61/**
62 * DefaultFetch class handles both single threaded and SMT fetch. Its
63 * width is specified by the parameters; each cycle it tries to fetch
64 * that many instructions. It supports using a branch predictor to
65 * predict direction and targets.
66 * It supports the idling functionality of the CPU by indicating to
67 * the CPU when it is active and inactive.
68 */
69template <class Impl>
70class DefaultFetch
71{
72  public:
73    /** Typedefs from Impl. */
74    typedef typename Impl::CPUPol CPUPol;
75    typedef typename Impl::DynInst DynInst;
76    typedef typename Impl::DynInstPtr DynInstPtr;
77    typedef typename Impl::O3CPU O3CPU;
78
79    /** Typedefs from the CPU policy. */
80    typedef typename CPUPol::BPredUnit BPredUnit;
81    typedef typename CPUPol::FetchStruct FetchStruct;
82    typedef typename CPUPol::TimeStruct TimeStruct;
83
84    /** Typedefs from ISA. */
85    typedef TheISA::MachInst MachInst;
86    typedef TheISA::ExtMachInst ExtMachInst;
87
88    /** IcachePort class for DefaultFetch.  Handles doing the
89     * communication with the cache/memory.
90     */
91    class IcachePort : public Port
92    {
93      protected:
94        /** Pointer to fetch. */
95        DefaultFetch<Impl> *fetch;
96
97      public:
98        /** Default constructor. */
99        IcachePort(DefaultFetch<Impl> *_fetch)
100            : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
101        { }
102
103        bool snoopRangeSent;
104
105        virtual void setPeer(Port *port);
106
107      protected:
108        /** Atomic version of receive.  Panics. */
109        virtual Tick recvAtomic(PacketPtr pkt);
110
111        /** Functional version of receive.  Panics. */
112        virtual void recvFunctional(PacketPtr pkt);
113
114        /** Receives status change.  Other than range changing, panics. */
115        virtual void recvStatusChange(Status status);
116
117        /** Returns the address ranges of this device. */
118        virtual void getDeviceAddressRanges(AddrRangeList &resp,
119                                            bool &snoop)
120        { resp.clear(); snoop = true; }
121
122        /** Timing version of receive.  Handles setting fetch to the
123         * proper status to start fetching. */
124        virtual bool recvTiming(PacketPtr pkt);
125
126        /** Handles doing a retry of a failed fetch. */
127        virtual void recvRetry();
128    };
129
130    class FetchTranslation : public BaseTLB::Translation
131    {
132      protected:
133        DefaultFetch<Impl> *fetch;
134
135      public:
136        FetchTranslation(DefaultFetch<Impl> *_fetch)
137            : fetch(_fetch)
138        {}
139
140        void
141        markDelayed()
142        {}
143
144        void
145        finish(Fault fault, RequestPtr req, ThreadContext *tc,
146               BaseTLB::Mode mode)
147        {
148            assert(mode == BaseTLB::Execute);
149            fetch->finishTranslation(fault, req);
150            delete this;
151        }
152    };
153
154  private:
155    /* Event to delay delivery of a fetch translation result in case of
156     * a fault and the nop to carry the fault cannot be generated
157     * immediately */
158    class FinishTranslationEvent : public Event
159    {
160      private:
161        DefaultFetch<Impl> *fetch;
162        Fault fault;
163        RequestPtr req;
164
165      public:
166        FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
167            : fetch(_fetch)
168        {}
169
170        void setFault(Fault _fault)
171        {
172            fault = _fault;
173        }
174
175        void setReq(RequestPtr _req)
176        {
177            req = _req;
178        }
179
180        /** Process the delayed finish translation */
181        void process()
182        {
183            assert(fetch->numInst < fetch->fetchWidth);
184            fetch->finishTranslation(fault, req);
185        }
186
187        const char *description() const
188        {
189            return "FullO3CPU FetchFinishTranslation";
190        }
191      };
192
193  public:
194    /** Overall fetch status. Used to determine if the CPU can
195     * deschedule itsef due to a lack of activity.
196     */
197    enum FetchStatus {
198        Active,
199        Inactive
200    };
201
202    /** Individual thread status. */
203    enum ThreadStatus {
204        Running,
205        Idle,
206        Squashing,
207        Blocked,
208        Fetching,
209        TrapPending,
210        QuiescePending,
211        SwitchOut,
212        ItlbWait,
213        IcacheWaitResponse,
214        IcacheWaitRetry,
215        IcacheAccessComplete,
216        NoGoodAddr
217    };
218
219    /** Fetching Policy, Add new policies here.*/
220    enum FetchPriority {
221        SingleThread,
222        RoundRobin,
223        Branch,
224        IQ,
225        LSQ
226    };
227
228  private:
229    /** Fetch status. */
230    FetchStatus _status;
231
232    /** Per-thread status. */
233    ThreadStatus fetchStatus[Impl::MaxThreads];
234
235    /** Fetch policy. */
236    FetchPriority fetchPolicy;
237
238    /** List that has the threads organized by priority. */
239    std::list<ThreadID> priorityList;
240
241  public:
242    /** DefaultFetch constructor. */
243    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
244
245    /** Returns the name of fetch. */
246    std::string name() const;
247
248    /** Registers statistics. */
249    void regStats();
250
251    /** Returns the icache port. */
252    Port *getIcachePort() { return icachePort; }
253
254    /** Sets the main backwards communication time buffer pointer. */
255    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
256
257    /** Sets pointer to list of active threads. */
258    void setActiveThreads(std::list<ThreadID> *at_ptr);
259
260    /** Sets pointer to time buffer used to communicate to the next stage. */
261    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
262
263    /** Initialize stage. */
264    void initStage();
265
266    /** Tells the fetch stage that the Icache is set. */
267    void setIcache();
268
269    /** Processes cache completion event. */
270    void processCacheCompletion(PacketPtr pkt);
271
272    /** Begins the drain of the fetch stage. */
273    bool drain();
274
275    /** Resumes execution after a drain. */
276    void resume();
277
278    /** Tells fetch stage to prepare to be switched out. */
279    void switchOut();
280
281    /** Takes over from another CPU's thread. */
282    void takeOverFrom();
283
284    /** Checks if the fetch stage is switched out. */
285    bool isSwitchedOut() { return switchedOut; }
286
287    /** Tells fetch to wake up from a quiesce instruction. */
288    void wakeFromQuiesce();
289
290  private:
291    /** Changes the status of this stage to active, and indicates this
292     * to the CPU.
293     */
294    inline void switchToActive();
295
296    /** Changes the status of this stage to inactive, and indicates
297     * this to the CPU.
298     */
299    inline void switchToInactive();
300
301    /**
302     * Looks up in the branch predictor to see if the next PC should be
303     * either next PC+=MachInst or a branch target.
304     * @param next_PC Next PC variable passed in by reference.  It is
305     * expected to be set to the current PC; it will be updated with what
306     * the next PC will be.
307     * @param next_NPC Used for ISAs which use delay slots.
308     * @return Whether or not a branch was predicted as taken.
309     */
310    bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
311
312    /**
313     * Fetches the cache line that contains fetch_PC.  Returns any
314     * fault that happened.  Puts the data into the class variable
315     * cacheData.
316     * @param vaddr The memory address that is being fetched from.
317     * @param ret_fault The fault reference that will be set to the result of
318     * the icache access.
319     * @param tid Thread id.
320     * @param pc The actual PC of the current instruction.
321     * @return Any fault that occured.
322     */
323    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
324    void finishTranslation(Fault fault, RequestPtr mem_req);
325
326
327    /** Check if an interrupt is pending and that we need to handle
328     */
329    bool
330    checkInterrupt(Addr pc)
331    {
332        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
333    }
334
335    /** Squashes a specific thread and resets the PC. */
336    inline void doSquash(const TheISA::PCState &newPC,
337                         const DynInstPtr squashInst, ThreadID tid);
338
339    /** Squashes a specific thread and resets the PC. Also tells the CPU to
340     * remove any instructions between fetch and decode that should be sqaushed.
341     */
342    void squashFromDecode(const TheISA::PCState &newPC,
343                          const DynInstPtr squashInst,
344                          const InstSeqNum seq_num, ThreadID tid);
345
346    /** Checks if a thread is stalled. */
347    bool checkStall(ThreadID tid) const;
348
349    /** Updates overall fetch stage status; to be called at the end of each
350     * cycle. */
351    FetchStatus updateFetchStatus();
352
353  public:
354    /** Squashes a specific thread and resets the PC. Also tells the CPU to
355     * remove any instructions that are not in the ROB. The source of this
356     * squash should be the commit stage.
357     */
358    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
359                DynInstPtr squashInst, ThreadID tid);
360
361    /** Ticks the fetch stage, processing all inputs signals and fetching
362     * as many instructions as possible.
363     */
364    void tick();
365
366    /** Checks all input signals and updates the status as necessary.
367     *  @return: Returns if the status has changed due to input signals.
368     */
369    bool checkSignalsAndUpdate(ThreadID tid);
370
371    /** Does the actual fetching of instructions and passing them on to the
372     * next stage.
373     * @param status_change fetch() sets this variable if there was a status
374     * change (ie switching to IcacheMissStall).
375     */
376    void fetch(bool &status_change);
377
378    /** Align a PC to the start of an I-cache block. */
379    Addr icacheBlockAlignPC(Addr addr)
380    {
381        return (addr & ~(cacheBlkMask));
382    }
383
384    /** The decoder. */
385    Decoder decoder;
386
387  private:
388    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
389                         StaticInstPtr curMacroop, TheISA::PCState thisPC,
390                         TheISA::PCState nextPC, bool trace);
391
392    /** Handles retrying the fetch access. */
393    void recvRetry();
394
395    /** Returns the appropriate thread to fetch, given the fetch policy. */
396    ThreadID getFetchingThread(FetchPriority &fetch_priority);
397
398    /** Returns the appropriate thread to fetch using a round robin policy. */
399    ThreadID roundRobin();
400
401    /** Returns the appropriate thread to fetch using the IQ count policy. */
402    ThreadID iqCount();
403
404    /** Returns the appropriate thread to fetch using the LSQ count policy. */
405    ThreadID lsqCount();
406
407    /** Returns the appropriate thread to fetch using the branch count
408     * policy. */
409    ThreadID branchCount();
410
411    /** Pipeline the next I-cache access to the current one. */
412    void pipelineIcacheAccesses(ThreadID tid);
413
414    /** Profile the reasons of fetch stall. */
415    void profileStall(ThreadID tid);
416
417  private:
418    /** Pointer to the O3CPU. */
419    O3CPU *cpu;
420
421    /** Time buffer interface. */
422    TimeBuffer<TimeStruct> *timeBuffer;
423
424    /** Wire to get decode's information from backwards time buffer. */
425    typename TimeBuffer<TimeStruct>::wire fromDecode;
426
427    /** Wire to get rename's information from backwards time buffer. */
428    typename TimeBuffer<TimeStruct>::wire fromRename;
429
430    /** Wire to get iew's information from backwards time buffer. */
431    typename TimeBuffer<TimeStruct>::wire fromIEW;
432
433    /** Wire to get commit's information from backwards time buffer. */
434    typename TimeBuffer<TimeStruct>::wire fromCommit;
435
436    /** Internal fetch instruction queue. */
437    TimeBuffer<FetchStruct> *fetchQueue;
438
439    //Might be annoying how this name is different than the queue.
440    /** Wire used to write any information heading to decode. */
441    typename TimeBuffer<FetchStruct>::wire toDecode;
442
443    /** Icache interface. */
444    IcachePort *icachePort;
445
446    /** BPredUnit. */
447    BPredUnit branchPred;
448
449    /** Predecoder. */
450    TheISA::Predecoder predecoder;
451
452    TheISA::PCState pc[Impl::MaxThreads];
453
454    Addr fetchOffset[Impl::MaxThreads];
455
456    StaticInstPtr macroop[Impl::MaxThreads];
457
458    /** Can the fetch stage redirect from an interrupt on this instruction? */
459    bool delayedCommit[Impl::MaxThreads];
460
461    /** Memory request used to access cache. */
462    RequestPtr memReq[Impl::MaxThreads];
463
464    /** Variable that tracks if fetch has written to the time buffer this
465     * cycle. Used to tell CPU if there is activity this cycle.
466     */
467    bool wroteToTimeBuffer;
468
469    /** Tracks how many instructions has been fetched this cycle. */
470    int numInst;
471
472    /** Source of possible stalls. */
473    struct Stalls {
474        bool decode;
475        bool rename;
476        bool iew;
477        bool commit;
478    };
479
480    /** Tracks which stages are telling fetch to stall. */
481    Stalls stalls[Impl::MaxThreads];
482
483    /** Decode to fetch delay, in ticks. */
484    unsigned decodeToFetchDelay;
485
486    /** Rename to fetch delay, in ticks. */
487    unsigned renameToFetchDelay;
488
489    /** IEW to fetch delay, in ticks. */
490    unsigned iewToFetchDelay;
491
492    /** Commit to fetch delay, in ticks. */
493    unsigned commitToFetchDelay;
494
495    /** The width of fetch in instructions. */
496    unsigned fetchWidth;
497
498    /** Is the cache blocked?  If so no threads can access it. */
499    bool cacheBlocked;
500
501    /** The packet that is waiting to be retried. */
502    PacketPtr retryPkt;
503
504    /** The thread that is waiting on the cache to tell fetch to retry. */
505    ThreadID retryTid;
506
507    /** Cache block size. */
508    int cacheBlkSize;
509
510    /** Mask to get a cache block's address. */
511    Addr cacheBlkMask;
512
513    /** The cache line being fetched. */
514    uint8_t *cacheData[Impl::MaxThreads];
515
516    /** The PC of the cacheline that has been loaded. */
517    Addr cacheDataPC[Impl::MaxThreads];
518
519    /** Whether or not the cache data is valid. */
520    bool cacheDataValid[Impl::MaxThreads];
521
522    /** Size of instructions. */
523    int instSize;
524
525    /** Icache stall statistics. */
526    Counter lastIcacheStall[Impl::MaxThreads];
527
528    /** List of Active Threads */
529    std::list<ThreadID> *activeThreads;
530
531    /** Number of threads. */
532    ThreadID numThreads;
533
534    /** Number of threads that are actively fetching. */
535    ThreadID numFetchingThreads;
536
537    /** Thread ID being fetched. */
538    ThreadID threadFetched;
539
540    /** Checks if there is an interrupt pending.  If there is, fetch
541     * must stop once it is not fetching PAL instructions.
542     */
543    bool interruptPending;
544
545    /** Is there a drain pending. */
546    bool drainPending;
547
548    /** Records if fetch is switched out. */
549    bool switchedOut;
550
551    /** Set to true if a pipelined I-cache request should be issued. */
552    bool issuePipelinedIfetch[Impl::MaxThreads];
553
554    /** Event used to delay fault generation of translation faults */
555    FinishTranslationEvent finishTranslationEvent;
556
557    // @todo: Consider making these vectors and tracking on a per thread basis.
558    /** Stat for total number of cycles stalled due to an icache miss. */
559    Stats::Scalar icacheStallCycles;
560    /** Stat for total number of fetched instructions. */
561    Stats::Scalar fetchedInsts;
562    /** Total number of fetched branches. */
563    Stats::Scalar fetchedBranches;
564    /** Stat for total number of predicted branches. */
565    Stats::Scalar predictedBranches;
566    /** Stat for total number of cycles spent fetching. */
567    Stats::Scalar fetchCycles;
568    /** Stat for total number of cycles spent squashing. */
569    Stats::Scalar fetchSquashCycles;
570    /** Stat for total number of cycles spent waiting for translation */
571    Stats::Scalar fetchTlbCycles;
572    /** Stat for total number of cycles spent blocked due to other stages in
573     * the pipeline.
574     */
575    Stats::Scalar fetchIdleCycles;
576    /** Total number of cycles spent blocked. */
577    Stats::Scalar fetchBlockedCycles;
578    /** Total number of cycles spent in any other state. */
579    Stats::Scalar fetchMiscStallCycles;
580    /** Total number of cycles spent in waiting for drains. */
581    Stats::Scalar fetchPendingDrainCycles;
582    /** Total number of stall cycles caused by no active threads to run. */
583    Stats::Scalar fetchNoActiveThreadStallCycles;
584    /** Total number of stall cycles caused by pending traps. */
585    Stats::Scalar fetchPendingTrapStallCycles;
586    /** Total number of stall cycles caused by pending quiesce instructions. */
587    Stats::Scalar fetchPendingQuiesceStallCycles;
588    /** Total number of stall cycles caused by I-cache wait retrys. */
589    Stats::Scalar fetchIcacheWaitRetryStallCycles;
590    /** Stat for total number of fetched cache lines. */
591    Stats::Scalar fetchedCacheLines;
592    /** Total number of outstanding icache accesses that were dropped
593     * due to a squash.
594     */
595    Stats::Scalar fetchIcacheSquashes;
596    /** Total number of outstanding tlb accesses that were dropped
597     * due to a squash.
598     */
599    Stats::Scalar fetchTlbSquashes;
600    /** Distribution of number of instructions fetched each cycle. */
601    Stats::Distribution fetchNisnDist;
602    /** Rate of how often fetch was idle. */
603    Stats::Formula idleRate;
604    /** Number of branch fetches per cycle. */
605    Stats::Formula branchRate;
606    /** Number of instruction fetched per cycle. */
607    Stats::Formula fetchRate;
608};
609
610#endif //__CPU_O3_FETCH_HH__
611