fetch.hh revision 1689
110447Snilay@cs.wisc.edu/* 210447Snilay@cs.wisc.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 310447Snilay@cs.wisc.edu * All rights reserved. 410447Snilay@cs.wisc.edu * 510447Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 610447Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 710447Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 810447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 910447Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 1010447Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 1110447Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 1210447Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 1310447Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410447Snilay@cs.wisc.edu * this software without specific prior written permission. 1510447Snilay@cs.wisc.edu * 1610447Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710447Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810447Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910447Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010447Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110447Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210447Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310447Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410447Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510447Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610447Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710447Snilay@cs.wisc.edu */ 2810447Snilay@cs.wisc.edu 2910447Snilay@cs.wisc.edu// Todo: SMT fetch, 3010447Snilay@cs.wisc.edu// Add a way to get a stage's current status. 3110447Snilay@cs.wisc.edu 3210447Snilay@cs.wisc.edu#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__ 3310447Snilay@cs.wisc.edu#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__ 3410447Snilay@cs.wisc.edu 3510447Snilay@cs.wisc.edu#include "base/statistics.hh" 3610447Snilay@cs.wisc.edu#include "base/timebuf.hh" 3710447Snilay@cs.wisc.edu#include "cpu/pc_event.hh" 3810447Snilay@cs.wisc.edu#include "mem/mem_interface.hh" 3910447Snilay@cs.wisc.edu#include "sim/eventq.hh" 4010447Snilay@cs.wisc.edu 4110447Snilay@cs.wisc.edu/** 4210447Snilay@cs.wisc.edu * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch 4310447Snilay@cs.wisc.edu * will stall if there's an Icache miss, but otherwise assumes a one cycle 4410447Snilay@cs.wisc.edu * Icache hit. 4510447Snilay@cs.wisc.edu */ 4610447Snilay@cs.wisc.edu 4710447Snilay@cs.wisc.edutemplate <class Impl> 4810447Snilay@cs.wisc.educlass SimpleFetch 4910447Snilay@cs.wisc.edu{ 50 public: 51 /** Typedefs from Impl. */ 52 typedef typename Impl::ISA ISA; 53 typedef typename Impl::CPUPol CPUPol; 54 typedef typename Impl::DynInst DynInst; 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 typedef typename Impl::FullCPU FullCPU; 57 typedef typename Impl::Params Params; 58 59 typedef typename CPUPol::BPredUnit BPredUnit; 60 typedef typename CPUPol::FetchStruct FetchStruct; 61 typedef typename CPUPol::TimeStruct TimeStruct; 62 63 /** Typedefs from ISA. */ 64 typedef typename ISA::MachInst MachInst; 65 66 public: 67 enum Status { 68 Running, 69 Idle, 70 Squashing, 71 Blocked, 72 IcacheMissStall, 73 IcacheMissComplete 74 }; 75 76 // May eventually need statuses on a per thread basis. 77 Status _status; 78 79 bool stalled; 80 81 public: 82 class CacheCompletionEvent : public Event 83 { 84 private: 85 SimpleFetch *fetch; 86 87 public: 88 CacheCompletionEvent(SimpleFetch *_fetch); 89 90 virtual void process(); 91 virtual const char *description(); 92 }; 93 94 public: 95 /** SimpleFetch constructor. */ 96 SimpleFetch(Params ¶ms); 97 98 void regStats(); 99 100 void setCPU(FullCPU *cpu_ptr); 101 102 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 103 104 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 105 106 void processCacheCompletion(); 107 108 private: 109 /** 110 * Looks up in the branch predictor to see if the next PC should be 111 * either next PC+=MachInst or a branch target. 112 * @params next_PC Next PC variable passed in by reference. It is 113 * expected to be set to the current PC; it will be updated with what 114 * the next PC will be. 115 * @return Whether or not a branch was predicted as taken. 116 */ 117 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); 118 119 /** 120 * Fetches the cache line that contains fetch_PC. Returns any 121 * fault that happened. Puts the data into the class variable 122 * cacheData. 123 * @params fetch_PC The PC address that is being fetched from. 124 * @return Any fault that occured. 125 */ 126 Fault fetchCacheLine(Addr fetch_PC); 127 128 inline void doSquash(const Addr &new_PC); 129 130 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num); 131 132 public: 133 // Figure out PC vs next PC and how it should be updated 134 void squash(const Addr &new_PC); 135 136 void tick(); 137 138 void fetch(); 139 140 // Align an address (typically a PC) to the start of an I-cache block. 141 // We fold in the PISA 64- to 32-bit conversion here as well. 142 Addr icacheBlockAlignPC(Addr addr) 143 { 144 addr = ISA::realPCToFetchPC(addr); 145 return (addr & ~(cacheBlkMask)); 146 } 147 148 private: 149 /** Pointer to the FullCPU. */ 150 FullCPU *cpu; 151 152 /** Time buffer interface. */ 153 TimeBuffer<TimeStruct> *timeBuffer; 154 155 /** Wire to get decode's information from backwards time buffer. */ 156 typename TimeBuffer<TimeStruct>::wire fromDecode; 157 158 /** Wire to get rename's information from backwards time buffer. */ 159 typename TimeBuffer<TimeStruct>::wire fromRename; 160 161 /** Wire to get iew's information from backwards time buffer. */ 162 typename TimeBuffer<TimeStruct>::wire fromIEW; 163 164 /** Wire to get commit's information from backwards time buffer. */ 165 typename TimeBuffer<TimeStruct>::wire fromCommit; 166 167 /** Internal fetch instruction queue. */ 168 TimeBuffer<FetchStruct> *fetchQueue; 169 170 //Might be annoying how this name is different than the queue. 171 /** Wire used to write any information heading to decode. */ 172 typename TimeBuffer<FetchStruct>::wire toDecode; 173 174 /** Icache interface. */ 175 MemInterface *icacheInterface; 176 177 /** BPredUnit. */ 178 BPredUnit branchPred; 179 180 /** Memory request used to access cache. */ 181 MemReqPtr memReq; 182 183 /** Decode to fetch delay, in ticks. */ 184 unsigned decodeToFetchDelay; 185 186 /** Rename to fetch delay, in ticks. */ 187 unsigned renameToFetchDelay; 188 189 /** IEW to fetch delay, in ticks. */ 190 unsigned iewToFetchDelay; 191 192 /** Commit to fetch delay, in ticks. */ 193 unsigned commitToFetchDelay; 194 195 /** The width of fetch in instructions. */ 196 unsigned fetchWidth; 197 198 /** Cache block size. */ 199 int cacheBlkSize; 200 201 /** Mask to get a cache block's address. */ 202 Addr cacheBlkMask; 203 204 /** The cache line being fetched. */ 205 uint8_t *cacheData; 206 207 /** Size of instructions. */ 208 int instSize; 209 210 /** Icache stall statistics. */ 211 Counter lastIcacheStall; 212 213 Stats::Scalar<> icacheStallCycles; 214 Stats::Scalar<> fetchedInsts; 215 Stats::Scalar<> predictedBranches; 216 Stats::Scalar<> fetchCycles; 217 Stats::Scalar<> fetchSquashCycles; 218 Stats::Scalar<> fetchBlockedCycles; 219 Stats::Scalar<> fetchedCacheLines; 220 221 Stats::Distribution<> fetch_nisn_dist; 222}; 223 224#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__ 225