fetch.hh revision 1689
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144120Sgblack@eecs.umich.edu * this software without specific prior written permission. 154120Sgblack@eecs.umich.edu * 164120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu */ 284120Sgblack@eecs.umich.edu 294120Sgblack@eecs.umich.edu// Todo: SMT fetch, 304120Sgblack@eecs.umich.edu// Add a way to get a stage's current status. 314120Sgblack@eecs.umich.edu 324120Sgblack@eecs.umich.edu#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__ 334120Sgblack@eecs.umich.edu#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__ 344120Sgblack@eecs.umich.edu 354120Sgblack@eecs.umich.edu#include "base/statistics.hh" 364120Sgblack@eecs.umich.edu#include "base/timebuf.hh" 374120Sgblack@eecs.umich.edu#include "cpu/pc_event.hh" 384120Sgblack@eecs.umich.edu#include "mem/mem_interface.hh" 394120Sgblack@eecs.umich.edu#include "sim/eventq.hh" 404120Sgblack@eecs.umich.edu 414120Sgblack@eecs.umich.edu/** 424120Sgblack@eecs.umich.edu * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch 434120Sgblack@eecs.umich.edu * will stall if there's an Icache miss, but otherwise assumes a one cycle 444120Sgblack@eecs.umich.edu * Icache hit. 454120Sgblack@eecs.umich.edu */ 464120Sgblack@eecs.umich.edu 474120Sgblack@eecs.umich.edutemplate <class Impl> 484120Sgblack@eecs.umich.educlass SimpleFetch 494120Sgblack@eecs.umich.edu{ 504120Sgblack@eecs.umich.edu public: 514120Sgblack@eecs.umich.edu /** Typedefs from Impl. */ 524120Sgblack@eecs.umich.edu typedef typename Impl::ISA ISA; 534120Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 544120Sgblack@eecs.umich.edu typedef typename Impl::DynInst DynInst; 554120Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 564120Sgblack@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 574120Sgblack@eecs.umich.edu typedef typename Impl::Params Params; 584120Sgblack@eecs.umich.edu 594120Sgblack@eecs.umich.edu typedef typename CPUPol::BPredUnit BPredUnit; 604120Sgblack@eecs.umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 614166Sgblack@eecs.umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 625228Sgblack@eecs.umich.edu 634141Sgblack@eecs.umich.edu /** Typedefs from ISA. */ 644136Sgblack@eecs.umich.edu typedef typename ISA::MachInst MachInst; 655086Sgblack@eecs.umich.edu 664136Sgblack@eecs.umich.edu public: 674141Sgblack@eecs.umich.edu enum Status { 684141Sgblack@eecs.umich.edu Running, 694121Sgblack@eecs.umich.edu Idle, 704120Sgblack@eecs.umich.edu Squashing, 714120Sgblack@eecs.umich.edu Blocked, 724120Sgblack@eecs.umich.edu IcacheMissStall, 734121Sgblack@eecs.umich.edu IcacheMissComplete 744121Sgblack@eecs.umich.edu }; 754121Sgblack@eecs.umich.edu 765228Sgblack@eecs.umich.edu // May eventually need statuses on a per thread basis. 775228Sgblack@eecs.umich.edu Status _status; 784121Sgblack@eecs.umich.edu 794121Sgblack@eecs.umich.edu bool stalled; 804121Sgblack@eecs.umich.edu 814121Sgblack@eecs.umich.edu public: 824121Sgblack@eecs.umich.edu class CacheCompletionEvent : public Event 834121Sgblack@eecs.umich.edu { 844121Sgblack@eecs.umich.edu private: 854121Sgblack@eecs.umich.edu SimpleFetch *fetch; 864121Sgblack@eecs.umich.edu 874121Sgblack@eecs.umich.edu public: 885063Sgblack@eecs.umich.edu CacheCompletionEvent(SimpleFetch *_fetch); 895063Sgblack@eecs.umich.edu 905063Sgblack@eecs.umich.edu virtual void process(); 914121Sgblack@eecs.umich.edu virtual const char *description(); 924121Sgblack@eecs.umich.edu }; 934121Sgblack@eecs.umich.edu 944121Sgblack@eecs.umich.edu public: 954121Sgblack@eecs.umich.edu /** SimpleFetch constructor. */ 965121Sgblack@eecs.umich.edu SimpleFetch(Params ¶ms); 975121Sgblack@eecs.umich.edu 985121Sgblack@eecs.umich.edu void regStats(); 995082Sgblack@eecs.umich.edu 1005082Sgblack@eecs.umich.edu void setCPU(FullCPU *cpu_ptr); 1014121Sgblack@eecs.umich.edu 1024121Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1034121Sgblack@eecs.umich.edu 1044121Sgblack@eecs.umich.edu void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1054587Sgblack@eecs.umich.edu 1064166Sgblack@eecs.umich.edu void processCacheCompletion(); 1074121Sgblack@eecs.umich.edu 1084121Sgblack@eecs.umich.edu private: 1094166Sgblack@eecs.umich.edu /** 1104166Sgblack@eecs.umich.edu * Looks up in the branch predictor to see if the next PC should be 1114772Sgblack@eecs.umich.edu * either next PC+=MachInst or a branch target. 1124772Sgblack@eecs.umich.edu * @params next_PC Next PC variable passed in by reference. It is 1134772Sgblack@eecs.umich.edu * expected to be set to the current PC; it will be updated with what 1144772Sgblack@eecs.umich.edu * the next PC will be. 1154772Sgblack@eecs.umich.edu * @return Whether or not a branch was predicted as taken. 1164772Sgblack@eecs.umich.edu */ 1174772Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); 1184772Sgblack@eecs.umich.edu 1194772Sgblack@eecs.umich.edu /** 1204772Sgblack@eecs.umich.edu * Fetches the cache line that contains fetch_PC. Returns any 1214772Sgblack@eecs.umich.edu * fault that happened. Puts the data into the class variable 1224121Sgblack@eecs.umich.edu * cacheData. 1234121Sgblack@eecs.umich.edu * @params fetch_PC The PC address that is being fetched from. 1244121Sgblack@eecs.umich.edu * @return Any fault that occured. 1254166Sgblack@eecs.umich.edu */ 1264121Sgblack@eecs.umich.edu Fault fetchCacheLine(Addr fetch_PC); 1274121Sgblack@eecs.umich.edu 1284141Sgblack@eecs.umich.edu inline void doSquash(const Addr &new_PC); 1294141Sgblack@eecs.umich.edu 1304141Sgblack@eecs.umich.edu void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num); 1315127Sgblack@eecs.umich.edu 1324141Sgblack@eecs.umich.edu public: 1334121Sgblack@eecs.umich.edu // Figure out PC vs next PC and how it should be updated 1344121Sgblack@eecs.umich.edu void squash(const Addr &new_PC); 1354141Sgblack@eecs.umich.edu 1364141Sgblack@eecs.umich.edu void tick(); 1375086Sgblack@eecs.umich.edu 1385152Sgblack@eecs.umich.edu void fetch(); 1394120Sgblack@eecs.umich.edu 1404120Sgblack@eecs.umich.edu // Align an address (typically a PC) to the start of an I-cache block. 1414120Sgblack@eecs.umich.edu // We fold in the PISA 64- to 32-bit conversion here as well. 142 Addr icacheBlockAlignPC(Addr addr) 143 { 144 addr = ISA::realPCToFetchPC(addr); 145 return (addr & ~(cacheBlkMask)); 146 } 147 148 private: 149 /** Pointer to the FullCPU. */ 150 FullCPU *cpu; 151 152 /** Time buffer interface. */ 153 TimeBuffer<TimeStruct> *timeBuffer; 154 155 /** Wire to get decode's information from backwards time buffer. */ 156 typename TimeBuffer<TimeStruct>::wire fromDecode; 157 158 /** Wire to get rename's information from backwards time buffer. */ 159 typename TimeBuffer<TimeStruct>::wire fromRename; 160 161 /** Wire to get iew's information from backwards time buffer. */ 162 typename TimeBuffer<TimeStruct>::wire fromIEW; 163 164 /** Wire to get commit's information from backwards time buffer. */ 165 typename TimeBuffer<TimeStruct>::wire fromCommit; 166 167 /** Internal fetch instruction queue. */ 168 TimeBuffer<FetchStruct> *fetchQueue; 169 170 //Might be annoying how this name is different than the queue. 171 /** Wire used to write any information heading to decode. */ 172 typename TimeBuffer<FetchStruct>::wire toDecode; 173 174 /** Icache interface. */ 175 MemInterface *icacheInterface; 176 177 /** BPredUnit. */ 178 BPredUnit branchPred; 179 180 /** Memory request used to access cache. */ 181 MemReqPtr memReq; 182 183 /** Decode to fetch delay, in ticks. */ 184 unsigned decodeToFetchDelay; 185 186 /** Rename to fetch delay, in ticks. */ 187 unsigned renameToFetchDelay; 188 189 /** IEW to fetch delay, in ticks. */ 190 unsigned iewToFetchDelay; 191 192 /** Commit to fetch delay, in ticks. */ 193 unsigned commitToFetchDelay; 194 195 /** The width of fetch in instructions. */ 196 unsigned fetchWidth; 197 198 /** Cache block size. */ 199 int cacheBlkSize; 200 201 /** Mask to get a cache block's address. */ 202 Addr cacheBlkMask; 203 204 /** The cache line being fetched. */ 205 uint8_t *cacheData; 206 207 /** Size of instructions. */ 208 int instSize; 209 210 /** Icache stall statistics. */ 211 Counter lastIcacheStall; 212 213 Stats::Scalar<> icacheStallCycles; 214 Stats::Scalar<> fetchedInsts; 215 Stats::Scalar<> predictedBranches; 216 Stats::Scalar<> fetchCycles; 217 Stats::Scalar<> fetchSquashCycles; 218 Stats::Scalar<> fetchBlockedCycles; 219 Stats::Scalar<> fetchedCacheLines; 220 221 Stats::Distribution<> fetch_nisn_dist; 222}; 223 224#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__ 225