dyn_inst_impl.hh revision 8887
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2010-2011 ARM Limited 311986Sandreas.sandberg@arm.com * All rights reserved 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 611986Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 711986Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 811986Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 911986Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1011986Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1111986Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1211986Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1311986Sandreas.sandberg@arm.com * 1411986Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1511986Sandreas.sandberg@arm.com * All rights reserved. 1611986Sandreas.sandberg@arm.com * 1711986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1811986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1912391Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 2012391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 2112391Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 2211986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2312391Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 2411986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2511986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2611986Sandreas.sandberg@arm.com * this software without specific prior written permission. 2711986Sandreas.sandberg@arm.com * 2811986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111986Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512391Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612391Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712391Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912391Sjason@lowepower.com * 4012391Sjason@lowepower.com * Authors: Kevin Lim 4111986Sandreas.sandberg@arm.com */ 4211986Sandreas.sandberg@arm.com 4311986Sandreas.sandberg@arm.com#include "base/cp_annotate.hh" 4412037Sandreas.sandberg@arm.com#include "cpu/o3/dyn_inst.hh" 4512037Sandreas.sandberg@arm.com#include "sim/full_system.hh" 4612391Sjason@lowepower.com 4712391Sjason@lowepower.comtemplate <class Impl> 4812391Sjason@lowepower.comBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 4912391Sjason@lowepower.com StaticInstPtr macroop, 5012391Sjason@lowepower.com TheISA::PCState pc, TheISA::PCState predPC, 5112391Sjason@lowepower.com InstSeqNum seq_num, O3CPU *cpu) 5212391Sjason@lowepower.com : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 5312391Sjason@lowepower.com{ 5412391Sjason@lowepower.com initVars(); 5512391Sjason@lowepower.com} 5612391Sjason@lowepower.com 5712391Sjason@lowepower.comtemplate <class Impl> 5812391Sjason@lowepower.comBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst, 5912391Sjason@lowepower.com StaticInstPtr _macroop) 6012391Sjason@lowepower.com : BaseDynInst<Impl>(_staticInst, _macroop) 6112391Sjason@lowepower.com{ 6212391Sjason@lowepower.com initVars(); 6312391Sjason@lowepower.com} 6412391Sjason@lowepower.com 6512391Sjason@lowepower.comtemplate <class Impl> 6612391Sjason@lowepower.comvoid 6712391Sjason@lowepower.comBaseO3DynInst<Impl>::initVars() 6812391Sjason@lowepower.com{ 6912391Sjason@lowepower.com // Make sure to have the renamed register entries set to the same 7012391Sjason@lowepower.com // as the normal register entries. It will allow the IQ to work 7112391Sjason@lowepower.com // without any modifications. 7212391Sjason@lowepower.com for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 7312391Sjason@lowepower.com this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 7412037Sandreas.sandberg@arm.com } 7512037Sandreas.sandberg@arm.com 7612037Sandreas.sandberg@arm.com for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 7712037Sandreas.sandberg@arm.com this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 7812037Sandreas.sandberg@arm.com this->_readySrcRegIdx[i] = 0; 7912037Sandreas.sandberg@arm.com } 8012037Sandreas.sandberg@arm.com 8112037Sandreas.sandberg@arm.com _numDestMiscRegs = 0; 8212037Sandreas.sandberg@arm.com 8312037Sandreas.sandberg@arm.com#if TRACING_ON 8412391Sjason@lowepower.com fetchTick = 0; 8512391Sjason@lowepower.com decodeTick = 0; 8612037Sandreas.sandberg@arm.com renameTick = 0; 8712037Sandreas.sandberg@arm.com dispatchTick = 0; 8812037Sandreas.sandberg@arm.com issueTick = 0; 8912391Sjason@lowepower.com completeTick = 0; 90#endif 91} 92 93template <class Impl> 94Fault 95BaseO3DynInst<Impl>::execute() 96{ 97 // @todo: Pretty convoluted way to avoid squashing from happening 98 // when using the TC during an instruction's execution 99 // (specifically for instructions that have side-effects that use 100 // the TC). Fix this. 101 bool in_syscall = this->thread->inSyscall; 102 this->thread->inSyscall = true; 103 104 this->fault = this->staticInst->execute(this, this->traceData); 105 106 this->thread->inSyscall = in_syscall; 107 108 return this->fault; 109} 110 111template <class Impl> 112Fault 113BaseO3DynInst<Impl>::initiateAcc() 114{ 115 // @todo: Pretty convoluted way to avoid squashing from happening 116 // when using the TC during an instruction's execution 117 // (specifically for instructions that have side-effects that use 118 // the TC). Fix this. 119 bool in_syscall = this->thread->inSyscall; 120 this->thread->inSyscall = true; 121 122 this->fault = this->staticInst->initiateAcc(this, this->traceData); 123 124 this->thread->inSyscall = in_syscall; 125 126 return this->fault; 127} 128 129template <class Impl> 130Fault 131BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 132{ 133 // @todo: Pretty convoluted way to avoid squashing from happening 134 // when using the TC during an instruction's execution 135 // (specifically for instructions that have side-effects that use 136 // the TC). Fix this. 137 bool in_syscall = this->thread->inSyscall; 138 this->thread->inSyscall = true; 139 140 if (this->cpu->checker) { 141 if (this->isStoreConditional()) { 142 this->reqToVerify->setExtraData(pkt->req->getExtraData()); 143 } 144 } 145 146 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 147 148 this->thread->inSyscall = in_syscall; 149 150 return this->fault; 151} 152 153template <class Impl> 154Fault 155BaseO3DynInst<Impl>::hwrei() 156{ 157#if THE_ISA == ALPHA_ISA 158 // Can only do a hwrei when in pal mode. 159 if (!(this->instAddr() & 0x3)) 160 return new AlphaISA::UnimplementedOpcodeFault; 161 162 // Set the next PC based on the value of the EXC_ADDR IPR. 163 AlphaISA::PCState pc = this->pcState(); 164 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 165 this->threadNumber)); 166 this->pcState(pc); 167 if (CPA::available()) { 168 ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 169 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 170 } 171 172 // Tell CPU to clear any state it needs to if a hwrei is taken. 173 this->cpu->hwrei(this->threadNumber); 174#else 175 176#endif 177 // FIXME: XXX check for interrupts? XXX 178 return NoFault; 179} 180 181template <class Impl> 182void 183BaseO3DynInst<Impl>::trap(Fault fault) 184{ 185 this->cpu->trap(fault, this->threadNumber, this->staticInst); 186} 187 188template <class Impl> 189bool 190BaseO3DynInst<Impl>::simPalCheck(int palFunc) 191{ 192#if THE_ISA != ALPHA_ISA 193 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 194#endif 195 return this->cpu->simPalCheck(palFunc, this->threadNumber); 196} 197 198template <class Impl> 199void 200BaseO3DynInst<Impl>::syscall(int64_t callnum) 201{ 202 if (FullSystem) 203 panic("Syscall emulation isn't available in FS mode.\n"); 204 205 // HACK: check CPU's nextPC before and after syscall. If it 206 // changes, update this instruction's nextPC because the syscall 207 // must have changed the nextPC. 208 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 209 this->cpu->syscall(callnum, this->threadNumber); 210 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 211 if (!(curPC == newPC)) { 212 this->pcState(newPC); 213 } 214} 215 216