dyn_inst_impl.hh revision 8887 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/full_system.hh"
46
47template <class Impl>
48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
49                                   StaticInstPtr macroop,
50                                   TheISA::PCState pc, TheISA::PCState predPC,
51                                   InstSeqNum seq_num, O3CPU *cpu)
52    : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
53{
54    initVars();
55}
56
57template <class Impl>
58BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
59                                   StaticInstPtr _macroop)
60    : BaseDynInst<Impl>(_staticInst, _macroop)
61{
62    initVars();
63}
64
65template <class Impl>
66void
67BaseO3DynInst<Impl>::initVars()
68{
69    // Make sure to have the renamed register entries set to the same
70    // as the normal register entries.  It will allow the IQ to work
71    // without any modifications.
72    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
73        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
74    }
75
76    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
77        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
78        this->_readySrcRegIdx[i] = 0;
79    }
80
81    _numDestMiscRegs = 0;
82
83#if TRACING_ON
84    fetchTick = 0;
85    decodeTick = 0;
86    renameTick = 0;
87    dispatchTick = 0;
88    issueTick = 0;
89    completeTick = 0;
90#endif
91}
92
93template <class Impl>
94Fault
95BaseO3DynInst<Impl>::execute()
96{
97    // @todo: Pretty convoluted way to avoid squashing from happening
98    // when using the TC during an instruction's execution
99    // (specifically for instructions that have side-effects that use
100    // the TC).  Fix this.
101    bool in_syscall = this->thread->inSyscall;
102    this->thread->inSyscall = true;
103
104    this->fault = this->staticInst->execute(this, this->traceData);
105
106    this->thread->inSyscall = in_syscall;
107
108    return this->fault;
109}
110
111template <class Impl>
112Fault
113BaseO3DynInst<Impl>::initiateAcc()
114{
115    // @todo: Pretty convoluted way to avoid squashing from happening
116    // when using the TC during an instruction's execution
117    // (specifically for instructions that have side-effects that use
118    // the TC).  Fix this.
119    bool in_syscall = this->thread->inSyscall;
120    this->thread->inSyscall = true;
121
122    this->fault = this->staticInst->initiateAcc(this, this->traceData);
123
124    this->thread->inSyscall = in_syscall;
125
126    return this->fault;
127}
128
129template <class Impl>
130Fault
131BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
132{
133    // @todo: Pretty convoluted way to avoid squashing from happening
134    // when using the TC during an instruction's execution
135    // (specifically for instructions that have side-effects that use
136    // the TC).  Fix this.
137    bool in_syscall = this->thread->inSyscall;
138    this->thread->inSyscall = true;
139
140    if (this->cpu->checker) {
141        if (this->isStoreConditional()) {
142            this->reqToVerify->setExtraData(pkt->req->getExtraData());
143        }
144    }
145
146    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
147
148    this->thread->inSyscall = in_syscall;
149
150    return this->fault;
151}
152
153template <class Impl>
154Fault
155BaseO3DynInst<Impl>::hwrei()
156{
157#if THE_ISA == ALPHA_ISA
158    // Can only do a hwrei when in pal mode.
159    if (!(this->instAddr() & 0x3))
160        return new AlphaISA::UnimplementedOpcodeFault;
161
162    // Set the next PC based on the value of the EXC_ADDR IPR.
163    AlphaISA::PCState pc = this->pcState();
164    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
165                                          this->threadNumber));
166    this->pcState(pc);
167    if (CPA::available()) {
168        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
169        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
170    }
171
172    // Tell CPU to clear any state it needs to if a hwrei is taken.
173    this->cpu->hwrei(this->threadNumber);
174#else
175
176#endif
177    // FIXME: XXX check for interrupts? XXX
178    return NoFault;
179}
180
181template <class Impl>
182void
183BaseO3DynInst<Impl>::trap(Fault fault)
184{
185    this->cpu->trap(fault, this->threadNumber, this->staticInst);
186}
187
188template <class Impl>
189bool
190BaseO3DynInst<Impl>::simPalCheck(int palFunc)
191{
192#if THE_ISA != ALPHA_ISA
193    panic("simPalCheck called, but PAL only exists in Alpha!\n");
194#endif
195    return this->cpu->simPalCheck(palFunc, this->threadNumber);
196}
197
198template <class Impl>
199void
200BaseO3DynInst<Impl>::syscall(int64_t callnum)
201{
202    if (FullSystem)
203        panic("Syscall emulation isn't available in FS mode.\n");
204
205    // HACK: check CPU's nextPC before and after syscall. If it
206    // changes, update this instruction's nextPC because the syscall
207    // must have changed the nextPC.
208    TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
209    this->cpu->syscall(callnum, this->threadNumber);
210    TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
211    if (!(curPC == newPC)) {
212        this->pcState(newPC);
213    }
214}
215
216