dyn_inst_impl.hh revision 7720
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 291689SN/A */ 301061SN/A 315953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 325596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh" 331061SN/A 341061SN/Atemplate <class Impl> 355596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 367720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 375596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 387720Sgblack@eecs.umich.edu : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu) 394637SN/A{ 404637SN/A initVars(); 414637SN/A} 424637SN/A 434637SN/Atemplate <class Impl> 445596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 457720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 465596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 477720Sgblack@eecs.umich.edu : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu) 481061SN/A{ 492292SN/A initVars(); 501061SN/A} 511061SN/A 521061SN/Atemplate <class Impl> 535596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 541464SN/A : BaseDynInst<Impl>(_staticInst) 551061SN/A{ 562292SN/A initVars(); 572292SN/A} 582292SN/A 592292SN/Atemplate <class Impl> 602292SN/Avoid 615596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars() 622292SN/A{ 631464SN/A // Make sure to have the renamed register entries set to the same 641464SN/A // as the normal register entries. It will allow the IQ to work 651464SN/A // without any modifications. 662292SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 673782SN/A this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 681464SN/A } 691464SN/A 702292SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 713782SN/A this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 722292SN/A this->_readySrcRegIdx[i] = 0; 731464SN/A } 741061SN/A} 751061SN/A 762292SN/Atemplate <class Impl> 772292SN/AFault 785596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute() 792292SN/A{ 802348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 812680SN/A // when using the TC during an instruction's execution 822348SN/A // (specifically for instructions that have side-effects that use 832680SN/A // the TC). Fix this. 842292SN/A bool in_syscall = this->thread->inSyscall; 852292SN/A this->thread->inSyscall = true; 862292SN/A 872292SN/A this->fault = this->staticInst->execute(this, this->traceData); 882292SN/A 892292SN/A this->thread->inSyscall = in_syscall; 902292SN/A 912292SN/A return this->fault; 922292SN/A} 932292SN/A 942292SN/Atemplate <class Impl> 952292SN/AFault 965596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc() 972292SN/A{ 982348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 992680SN/A // when using the TC during an instruction's execution 1002348SN/A // (specifically for instructions that have side-effects that use 1012680SN/A // the TC). Fix this. 1022292SN/A bool in_syscall = this->thread->inSyscall; 1032292SN/A this->thread->inSyscall = true; 1042292SN/A 1052292SN/A this->fault = this->staticInst->initiateAcc(this, this->traceData); 1062292SN/A 1072292SN/A this->thread->inSyscall = in_syscall; 1082292SN/A 1092292SN/A return this->fault; 1102292SN/A} 1112292SN/A 1122292SN/Atemplate <class Impl> 1132292SN/AFault 1145596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 1152292SN/A{ 1162790SN/A this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 1172292SN/A 1182292SN/A return this->fault; 1192292SN/A} 1202292SN/A 1211858SN/A#if FULL_SYSTEM 1221061SN/Atemplate <class Impl> 1235702Ssaidi@eecs.umich.eduFault 1245702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei() 1255702Ssaidi@eecs.umich.edu{ 1265702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1275702Ssaidi@eecs.umich.edu // Can only do a hwrei when in pal mode. 1287720Sgblack@eecs.umich.edu if (!(this->instAddr() & 0x3)) 1295702Ssaidi@eecs.umich.edu return new AlphaISA::UnimplementedOpcodeFault; 1305702Ssaidi@eecs.umich.edu 1315702Ssaidi@eecs.umich.edu // Set the next PC based on the value of the EXC_ADDR IPR. 1327720Sgblack@eecs.umich.edu AlphaISA::PCState pc = this->pcState(); 1337720Sgblack@eecs.umich.edu pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 1347720Sgblack@eecs.umich.edu this->threadNumber)); 1357720Sgblack@eecs.umich.edu this->pcState(pc); 1365953Ssaidi@eecs.umich.edu if (CPA::available()) { 1375953Ssaidi@eecs.umich.edu ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 1387720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 1395953Ssaidi@eecs.umich.edu } 1405702Ssaidi@eecs.umich.edu 1415702Ssaidi@eecs.umich.edu // Tell CPU to clear any state it needs to if a hwrei is taken. 1425702Ssaidi@eecs.umich.edu this->cpu->hwrei(this->threadNumber); 1435702Ssaidi@eecs.umich.edu#else 1445702Ssaidi@eecs.umich.edu 1455702Ssaidi@eecs.umich.edu#endif 1465702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 1475702Ssaidi@eecs.umich.edu return NoFault; 1485702Ssaidi@eecs.umich.edu} 1495702Ssaidi@eecs.umich.edu 1505702Ssaidi@eecs.umich.edutemplate <class Impl> 1511061SN/Avoid 1525596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault) 1531061SN/A{ 1547684Sgblack@eecs.umich.edu this->cpu->trap(fault, this->threadNumber, this->staticInst); 1551061SN/A} 1565702Ssaidi@eecs.umich.edu 1575702Ssaidi@eecs.umich.edutemplate <class Impl> 1585702Ssaidi@eecs.umich.edubool 1595702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc) 1605702Ssaidi@eecs.umich.edu{ 1615702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA 1625702Ssaidi@eecs.umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 1635702Ssaidi@eecs.umich.edu#endif 1645702Ssaidi@eecs.umich.edu return this->cpu->simPalCheck(palFunc, this->threadNumber); 1655702Ssaidi@eecs.umich.edu} 1661061SN/A#else 1671061SN/Atemplate <class Impl> 1681061SN/Avoid 1695596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum) 1701061SN/A{ 1715556SN/A // HACK: check CPU's nextPC before and after syscall. If it 1725556SN/A // changes, update this instruction's nextPC because the syscall 1735556SN/A // must have changed the nextPC. 1747720Sgblack@eecs.umich.edu TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 1752669SN/A this->cpu->syscall(callnum, this->threadNumber); 1767720Sgblack@eecs.umich.edu TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 1777720Sgblack@eecs.umich.edu if (!(curPC == newPC)) { 1787720Sgblack@eecs.umich.edu this->pcState(newPC); 1795556SN/A } 1801061SN/A} 1811061SN/A#endif 1821061SN/A 183