dyn_inst_impl.hh revision 7720
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "base/cp_annotate.hh" 32#include "cpu/o3/dyn_inst.hh" 33 34template <class Impl> 35BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 36 TheISA::PCState pc, TheISA::PCState predPC, 37 InstSeqNum seq_num, O3CPU *cpu) 38 : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu) 39{ 40 initVars(); 41} 42 43template <class Impl> 44BaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 45 TheISA::PCState pc, TheISA::PCState predPC, 46 InstSeqNum seq_num, O3CPU *cpu) 47 : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu) 48{ 49 initVars(); 50} 51 52template <class Impl> 53BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 54 : BaseDynInst<Impl>(_staticInst) 55{ 56 initVars(); 57} 58 59template <class Impl> 60void 61BaseO3DynInst<Impl>::initVars() 62{ 63 // Make sure to have the renamed register entries set to the same 64 // as the normal register entries. It will allow the IQ to work 65 // without any modifications. 66 for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 67 this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 68 } 69 70 for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 71 this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 72 this->_readySrcRegIdx[i] = 0; 73 } 74} 75 76template <class Impl> 77Fault 78BaseO3DynInst<Impl>::execute() 79{ 80 // @todo: Pretty convoluted way to avoid squashing from happening 81 // when using the TC during an instruction's execution 82 // (specifically for instructions that have side-effects that use 83 // the TC). Fix this. 84 bool in_syscall = this->thread->inSyscall; 85 this->thread->inSyscall = true; 86 87 this->fault = this->staticInst->execute(this, this->traceData); 88 89 this->thread->inSyscall = in_syscall; 90 91 return this->fault; 92} 93 94template <class Impl> 95Fault 96BaseO3DynInst<Impl>::initiateAcc() 97{ 98 // @todo: Pretty convoluted way to avoid squashing from happening 99 // when using the TC during an instruction's execution 100 // (specifically for instructions that have side-effects that use 101 // the TC). Fix this. 102 bool in_syscall = this->thread->inSyscall; 103 this->thread->inSyscall = true; 104 105 this->fault = this->staticInst->initiateAcc(this, this->traceData); 106 107 this->thread->inSyscall = in_syscall; 108 109 return this->fault; 110} 111 112template <class Impl> 113Fault 114BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 115{ 116 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 117 118 return this->fault; 119} 120 121#if FULL_SYSTEM 122template <class Impl> 123Fault 124BaseO3DynInst<Impl>::hwrei() 125{ 126#if THE_ISA == ALPHA_ISA 127 // Can only do a hwrei when in pal mode. 128 if (!(this->instAddr() & 0x3)) 129 return new AlphaISA::UnimplementedOpcodeFault; 130 131 // Set the next PC based on the value of the EXC_ADDR IPR. 132 AlphaISA::PCState pc = this->pcState(); 133 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 134 this->threadNumber)); 135 this->pcState(pc); 136 if (CPA::available()) { 137 ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 138 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 139 } 140 141 // Tell CPU to clear any state it needs to if a hwrei is taken. 142 this->cpu->hwrei(this->threadNumber); 143#else 144 145#endif 146 // FIXME: XXX check for interrupts? XXX 147 return NoFault; 148} 149 150template <class Impl> 151void 152BaseO3DynInst<Impl>::trap(Fault fault) 153{ 154 this->cpu->trap(fault, this->threadNumber, this->staticInst); 155} 156 157template <class Impl> 158bool 159BaseO3DynInst<Impl>::simPalCheck(int palFunc) 160{ 161#if THE_ISA != ALPHA_ISA 162 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 163#endif 164 return this->cpu->simPalCheck(palFunc, this->threadNumber); 165} 166#else 167template <class Impl> 168void 169BaseO3DynInst<Impl>::syscall(int64_t callnum) 170{ 171 // HACK: check CPU's nextPC before and after syscall. If it 172 // changes, update this instruction's nextPC because the syscall 173 // must have changed the nextPC. 174 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 175 this->cpu->syscall(callnum, this->threadNumber); 176 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 177 if (!(curPC == newPC)) { 178 this->pcState(newPC); 179 } 180} 181#endif 182 183