decode.hh revision 9184:a1a8f137b796 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_DECODE_HH__
32#define __CPU_O3_DECODE_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "cpu/timebuf.hh"
38
39struct DerivO3CPUParams;
40
41/**
42 * DefaultDecode class handles both single threaded and SMT
43 * decode. Its width is specified by the parameters; each cycles it
44 * tries to decode that many instructions. Because instructions are
45 * actually decoded when the StaticInst is created, this stage does
46 * not do much other than check any PC-relative branches.
47 */
48template<class Impl>
49class DefaultDecode
50{
51  private:
52    // Typedefs from the Impl.
53    typedef typename Impl::O3CPU O3CPU;
54    typedef typename Impl::DynInstPtr DynInstPtr;
55    typedef typename Impl::CPUPol CPUPol;
56
57    // Typedefs from the CPU policy.
58    typedef typename CPUPol::FetchStruct FetchStruct;
59    typedef typename CPUPol::DecodeStruct DecodeStruct;
60    typedef typename CPUPol::TimeStruct TimeStruct;
61
62  public:
63    /** Overall decode stage status. Used to determine if the CPU can
64     * deschedule itself due to a lack of activity.
65     */
66    enum DecodeStatus {
67        Active,
68        Inactive
69    };
70
71    /** Individual thread status. */
72    enum ThreadStatus {
73        Running,
74        Idle,
75        StartSquash,
76        Squashing,
77        Blocked,
78        Unblocking
79    };
80
81  private:
82    /** Decode status. */
83    DecodeStatus _status;
84
85    /** Per-thread status. */
86    ThreadStatus decodeStatus[Impl::MaxThreads];
87
88  public:
89    /** DefaultDecode constructor. */
90    DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
91
92    /** Returns the name of decode. */
93    std::string name() const;
94
95    /** Registers statistics. */
96    void regStats();
97
98    /** Sets the main backwards communication time buffer pointer. */
99    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
100
101    /** Sets pointer to time buffer used to communicate to the next stage. */
102    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
103
104    /** Sets pointer to time buffer coming from fetch. */
105    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
106
107    /** Sets pointer to list of active threads. */
108    void setActiveThreads(std::list<ThreadID> *at_ptr);
109
110    /** Drains the decode stage. */
111    bool drain();
112
113    /** Resumes execution after a drain. */
114    void resume() { }
115
116    /** Switches out the decode stage. */
117    void switchOut() { }
118
119    /** Takes over from another CPU's thread. */
120    void takeOverFrom();
121
122    /** Ticks decode, processing all input signals and decoding as many
123     * instructions as possible.
124     */
125    void tick();
126
127    /** Determines what to do based on decode's current status.
128     * @param status_change decode() sets this variable if there was a status
129     * change (ie switching from from blocking to unblocking).
130     * @param tid Thread id to decode instructions from.
131     */
132    void decode(bool &status_change, ThreadID tid);
133
134    /** Processes instructions from fetch and passes them on to rename.
135     * Decoding of instructions actually happens when they are created in
136     * fetch, so this function mostly checks if PC-relative branches are
137     * correct.
138     */
139    void decodeInsts(ThreadID tid);
140
141  private:
142    /** Inserts a thread's instructions into the skid buffer, to be decoded
143     * once decode unblocks.
144     */
145    void skidInsert(ThreadID tid);
146
147    /** Returns if all of the skid buffers are empty. */
148    bool skidsEmpty();
149
150    /** Updates overall decode status based on all of the threads' statuses. */
151    void updateStatus();
152
153    /** Separates instructions from fetch into individual lists of instructions
154     * sorted by thread.
155     */
156    void sortInsts();
157
158    /** Reads all stall signals from the backwards communication timebuffer. */
159    void readStallSignals(ThreadID tid);
160
161    /** Checks all input signals and updates decode's status appropriately. */
162    bool checkSignalsAndUpdate(ThreadID tid);
163
164    /** Checks all stall signals, and returns if any are true. */
165    bool checkStall(ThreadID tid) const;
166
167    /** Returns if there any instructions from fetch on this cycle. */
168    inline bool fetchInstsValid();
169
170    /** Switches decode to blocking, and signals back that decode has
171     * become blocked.
172     * @return Returns true if there is a status change.
173     */
174    bool block(ThreadID tid);
175
176    /** Switches decode to unblocking if the skid buffer is empty, and
177     * signals back that decode has unblocked.
178     * @return Returns true if there is a status change.
179     */
180    bool unblock(ThreadID tid);
181
182    /** Squashes if there is a PC-relative branch that was predicted
183     * incorrectly. Sends squash information back to fetch.
184     */
185    void squash(DynInstPtr &inst, ThreadID tid);
186
187  public:
188    /** Squashes due to commit signalling a squash. Changes status to
189     * squashing and clears block/unblock signals as needed.
190     */
191    unsigned squash(ThreadID tid);
192
193  private:
194    // Interfaces to objects outside of decode.
195    /** CPU interface. */
196    O3CPU *cpu;
197
198    /** Time buffer interface. */
199    TimeBuffer<TimeStruct> *timeBuffer;
200
201    /** Wire to get rename's output from backwards time buffer. */
202    typename TimeBuffer<TimeStruct>::wire fromRename;
203
204    /** Wire to get iew's information from backwards time buffer. */
205    typename TimeBuffer<TimeStruct>::wire fromIEW;
206
207    /** Wire to get commit's information from backwards time buffer. */
208    typename TimeBuffer<TimeStruct>::wire fromCommit;
209
210    /** Wire to write information heading to previous stages. */
211    // Might not be the best name as not only fetch will read it.
212    typename TimeBuffer<TimeStruct>::wire toFetch;
213
214    /** Decode instruction queue. */
215    TimeBuffer<DecodeStruct> *decodeQueue;
216
217    /** Wire used to write any information heading to rename. */
218    typename TimeBuffer<DecodeStruct>::wire toRename;
219
220    /** Fetch instruction queue interface. */
221    TimeBuffer<FetchStruct> *fetchQueue;
222
223    /** Wire to get fetch's output from fetch queue. */
224    typename TimeBuffer<FetchStruct>::wire fromFetch;
225
226    /** Queue of all instructions coming from fetch this cycle. */
227    std::queue<DynInstPtr> insts[Impl::MaxThreads];
228
229    /** Skid buffer between fetch and decode. */
230    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
231
232    /** Variable that tracks if decode has written to the time buffer this
233     * cycle. Used to tell CPU if there is activity this cycle.
234     */
235    bool wroteToTimeBuffer;
236
237    /** Source of possible stalls. */
238    struct Stalls {
239        bool rename;
240        bool iew;
241        bool commit;
242    };
243
244    /** Tracks which stages are telling decode to stall. */
245    Stalls stalls[Impl::MaxThreads];
246
247    /** Rename to decode delay. */
248    Cycles renameToDecodeDelay;
249
250    /** IEW to decode delay. */
251    Cycles iewToDecodeDelay;
252
253    /** Commit to decode delay. */
254    Cycles commitToDecodeDelay;
255
256    /** Fetch to decode delay. */
257    Cycles fetchToDecodeDelay;
258
259    /** The width of decode, in instructions. */
260    unsigned decodeWidth;
261
262    /** Index of instructions being sent to rename. */
263    unsigned toRenameIndex;
264
265    /** number of Active Threads*/
266    ThreadID numThreads;
267
268    /** List of active thread ids */
269    std::list<ThreadID> *activeThreads;
270
271    /** Number of branches in flight. */
272    unsigned branchCount[Impl::MaxThreads];
273
274    /** Maximum size of the skid buffer. */
275    unsigned skidBufferMax;
276
277    /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
278    Addr bdelayDoneSeqNum[Impl::MaxThreads];
279
280    /** Instruction used for squashing branch (used for MIPS)*/
281    DynInstPtr squashInst[Impl::MaxThreads];
282
283    /** Tells when their is a pending delay slot inst. to send
284     *  to rename. If there is, then wait squash after the next
285     *  instruction (used for MIPS).
286     */
287    bool squashAfterDelaySlot[Impl::MaxThreads];
288
289
290    /** Stat for total number of idle cycles. */
291    Stats::Scalar decodeIdleCycles;
292    /** Stat for total number of blocked cycles. */
293    Stats::Scalar decodeBlockedCycles;
294    /** Stat for total number of normal running cycles. */
295    Stats::Scalar decodeRunCycles;
296    /** Stat for total number of unblocking cycles. */
297    Stats::Scalar decodeUnblockCycles;
298    /** Stat for total number of squashing cycles. */
299    Stats::Scalar decodeSquashCycles;
300    /** Stat for number of times a branch is resolved at decode. */
301    Stats::Scalar decodeBranchResolved;
302    /** Stat for number of times a branch mispredict is detected. */
303    Stats::Scalar decodeBranchMispred;
304    /** Stat for number of times decode detected a non-control instruction
305     * incorrectly predicted as a branch.
306     */
307    Stats::Scalar decodeControlMispred;
308    /** Stat for total number of decoded instructions. */
309    Stats::Scalar decodeDecodedInsts;
310    /** Stat for total number of squashed instructions. */
311    Stats::Scalar decodeSquashedInsts;
312};
313
314#endif // __CPU_O3_DECODE_HH__
315