decode.hh revision 2935:d1223a6c9156 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_DECODE_HH__
32#define __CPU_O3_DECODE_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38
39/**
40 * DefaultDecode class handles both single threaded and SMT
41 * decode. Its width is specified by the parameters; each cycles it
42 * tries to decode that many instructions. Because instructions are
43 * actually decoded when the StaticInst is created, this stage does
44 * not do much other than check any PC-relative branches.
45 */
46template<class Impl>
47class DefaultDecode
48{
49  private:
50    // Typedefs from the Impl.
51    typedef typename Impl::O3CPU O3CPU;
52    typedef typename Impl::DynInstPtr DynInstPtr;
53    typedef typename Impl::Params Params;
54    typedef typename Impl::CPUPol CPUPol;
55
56    // Typedefs from the CPU policy.
57    typedef typename CPUPol::FetchStruct FetchStruct;
58    typedef typename CPUPol::DecodeStruct DecodeStruct;
59    typedef typename CPUPol::TimeStruct TimeStruct;
60
61  public:
62    /** Overall decode stage status. Used to determine if the CPU can
63     * deschedule itself due to a lack of activity.
64     */
65    enum DecodeStatus {
66        Active,
67        Inactive
68    };
69
70    /** Individual thread status. */
71    enum ThreadStatus {
72        Running,
73        Idle,
74        StartSquash,
75        Squashing,
76        Blocked,
77        Unblocking
78    };
79
80  private:
81    /** Decode status. */
82    DecodeStatus _status;
83
84    /** Per-thread status. */
85    ThreadStatus decodeStatus[Impl::MaxThreads];
86
87  public:
88    /** DefaultDecode constructor. */
89    DefaultDecode(Params *params);
90
91    /** Returns the name of decode. */
92    std::string name() const;
93
94    /** Registers statistics. */
95    void regStats();
96
97    /** Sets CPU pointer. */
98    void setCPU(O3CPU *cpu_ptr);
99
100    /** Sets the main backwards communication time buffer pointer. */
101    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
102
103    /** Sets pointer to time buffer used to communicate to the next stage. */
104    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
105
106    /** Sets pointer to time buffer coming from fetch. */
107    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
108
109    /** Sets pointer to list of active threads. */
110    void setActiveThreads(std::list<unsigned> *at_ptr);
111
112    /** Drains the decode stage. */
113    bool drain();
114
115    /** Resumes execution after a drain. */
116    void resume() { }
117
118    /** Switches out the decode stage. */
119    void switchOut() { }
120
121    /** Takes over from another CPU's thread. */
122    void takeOverFrom();
123
124    /** Ticks decode, processing all input signals and decoding as many
125     * instructions as possible.
126     */
127    void tick();
128
129    /** Determines what to do based on decode's current status.
130     * @param status_change decode() sets this variable if there was a status
131     * change (ie switching from from blocking to unblocking).
132     * @param tid Thread id to decode instructions from.
133     */
134    void decode(bool &status_change, unsigned tid);
135
136    /** Processes instructions from fetch and passes them on to rename.
137     * Decoding of instructions actually happens when they are created in
138     * fetch, so this function mostly checks if PC-relative branches are
139     * correct.
140     */
141    void decodeInsts(unsigned tid);
142
143  private:
144    /** Inserts a thread's instructions into the skid buffer, to be decoded
145     * once decode unblocks.
146     */
147    void skidInsert(unsigned tid);
148
149    /** Returns if all of the skid buffers are empty. */
150    bool skidsEmpty();
151
152    /** Updates overall decode status based on all of the threads' statuses. */
153    void updateStatus();
154
155    /** Separates instructions from fetch into individual lists of instructions
156     * sorted by thread.
157     */
158    void sortInsts();
159
160    /** Reads all stall signals from the backwards communication timebuffer. */
161    void readStallSignals(unsigned tid);
162
163    /** Checks all input signals and updates decode's status appropriately. */
164    bool checkSignalsAndUpdate(unsigned tid);
165
166    /** Checks all stall signals, and returns if any are true. */
167    bool checkStall(unsigned tid) const;
168
169    /** Returns if there any instructions from fetch on this cycle. */
170    inline bool fetchInstsValid();
171
172    /** Switches decode to blocking, and signals back that decode has
173     * become blocked.
174     * @return Returns true if there is a status change.
175     */
176    bool block(unsigned tid);
177
178    /** Switches decode to unblocking if the skid buffer is empty, and
179     * signals back that decode has unblocked.
180     * @return Returns true if there is a status change.
181     */
182    bool unblock(unsigned tid);
183
184    /** Squashes if there is a PC-relative branch that was predicted
185     * incorrectly. Sends squash information back to fetch.
186     */
187    void squash(DynInstPtr &inst, unsigned tid);
188
189  public:
190    /** Squashes due to commit signalling a squash. Changes status to
191     * squashing and clears block/unblock signals as needed.
192     */
193    unsigned squash(unsigned tid);
194
195  private:
196    // Interfaces to objects outside of decode.
197    /** CPU interface. */
198    O3CPU *cpu;
199
200    /** Time buffer interface. */
201    TimeBuffer<TimeStruct> *timeBuffer;
202
203    /** Wire to get rename's output from backwards time buffer. */
204    typename TimeBuffer<TimeStruct>::wire fromRename;
205
206    /** Wire to get iew's information from backwards time buffer. */
207    typename TimeBuffer<TimeStruct>::wire fromIEW;
208
209    /** Wire to get commit's information from backwards time buffer. */
210    typename TimeBuffer<TimeStruct>::wire fromCommit;
211
212    /** Wire to write information heading to previous stages. */
213    // Might not be the best name as not only fetch will read it.
214    typename TimeBuffer<TimeStruct>::wire toFetch;
215
216    /** Decode instruction queue. */
217    TimeBuffer<DecodeStruct> *decodeQueue;
218
219    /** Wire used to write any information heading to rename. */
220    typename TimeBuffer<DecodeStruct>::wire toRename;
221
222    /** Fetch instruction queue interface. */
223    TimeBuffer<FetchStruct> *fetchQueue;
224
225    /** Wire to get fetch's output from fetch queue. */
226    typename TimeBuffer<FetchStruct>::wire fromFetch;
227
228    /** Queue of all instructions coming from fetch this cycle. */
229    std::queue<DynInstPtr> insts[Impl::MaxThreads];
230
231    /** Skid buffer between fetch and decode. */
232    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
233
234    /** Variable that tracks if decode has written to the time buffer this
235     * cycle. Used to tell CPU if there is activity this cycle.
236     */
237    bool wroteToTimeBuffer;
238
239    /** Source of possible stalls. */
240    struct Stalls {
241        bool rename;
242        bool iew;
243        bool commit;
244    };
245
246    /** Tracks which stages are telling decode to stall. */
247    Stalls stalls[Impl::MaxThreads];
248
249    /** Rename to decode delay, in ticks. */
250    unsigned renameToDecodeDelay;
251
252    /** IEW to decode delay, in ticks. */
253    unsigned iewToDecodeDelay;
254
255    /** Commit to decode delay, in ticks. */
256    unsigned commitToDecodeDelay;
257
258    /** Fetch to decode delay, in ticks. */
259    unsigned fetchToDecodeDelay;
260
261    /** The width of decode, in instructions. */
262    unsigned decodeWidth;
263
264    /** Index of instructions being sent to rename. */
265    unsigned toRenameIndex;
266
267    /** number of Active Threads*/
268    unsigned numThreads;
269
270    /** List of active thread ids */
271    std::list<unsigned> *activeThreads;
272
273    /** Number of branches in flight. */
274    unsigned branchCount[Impl::MaxThreads];
275
276    /** Maximum size of the skid buffer. */
277    unsigned skidBufferMax;
278
279    /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
280    Addr bdelayDoneSeqNum[Impl::MaxThreads];
281
282    /** Instruction used for squashing branch (used for MIPS)*/
283    DynInstPtr squashInst[Impl::MaxThreads];
284
285    /** Tells when their is a pending delay slot inst. to send
286     *  to rename. If there is, then wait squash after the next
287     *  instruction (used for MIPS).
288     */
289    bool squashAfterDelaySlot[Impl::MaxThreads];
290
291
292    /** Stat for total number of idle cycles. */
293    Stats::Scalar<> decodeIdleCycles;
294    /** Stat for total number of blocked cycles. */
295    Stats::Scalar<> decodeBlockedCycles;
296    /** Stat for total number of normal running cycles. */
297    Stats::Scalar<> decodeRunCycles;
298    /** Stat for total number of unblocking cycles. */
299    Stats::Scalar<> decodeUnblockCycles;
300    /** Stat for total number of squashing cycles. */
301    Stats::Scalar<> decodeSquashCycles;
302    /** Stat for number of times a branch is resolved at decode. */
303    Stats::Scalar<> decodeBranchResolved;
304    /** Stat for number of times a branch mispredict is detected. */
305    Stats::Scalar<> decodeBranchMispred;
306    /** Stat for number of times decode detected a non-control instruction
307     * incorrectly predicted as a branch.
308     */
309    Stats::Scalar<> decodeControlMispred;
310    /** Stat for total number of decoded instructions. */
311    Stats::Scalar<> decodeDecodedInsts;
312    /** Stat for total number of squashed instructions. */
313    Stats::Scalar<> decodeSquashedInsts;
314};
315
316#endif // __CPU_O3_DECODE_HH__
317