decode.hh revision 2674:6d4afef73a20 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_DECODE_HH__
32#define __CPU_O3_DECODE_HH__
33
34#include <queue>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38
39/**
40 * DefaultDecode class handles both single threaded and SMT
41 * decode. Its width is specified by the parameters; each cycles it
42 * tries to decode that many instructions. Because instructions are
43 * actually decoded when the StaticInst is created, this stage does
44 * not do much other than check any PC-relative branches.
45 */
46template<class Impl>
47class DefaultDecode
48{
49  private:
50    // Typedefs from the Impl.
51    typedef typename Impl::FullCPU FullCPU;
52    typedef typename Impl::DynInstPtr DynInstPtr;
53    typedef typename Impl::Params Params;
54    typedef typename Impl::CPUPol CPUPol;
55
56    // Typedefs from the CPU policy.
57    typedef typename CPUPol::FetchStruct FetchStruct;
58    typedef typename CPUPol::DecodeStruct DecodeStruct;
59    typedef typename CPUPol::TimeStruct TimeStruct;
60
61  public:
62    /** Overall decode stage status. Used to determine if the CPU can
63     * deschedule itself due to a lack of activity.
64     */
65    enum DecodeStatus {
66        Active,
67        Inactive
68    };
69
70    /** Individual thread status. */
71    enum ThreadStatus {
72        Running,
73        Idle,
74        StartSquash,
75        Squashing,
76        Blocked,
77        Unblocking
78    };
79
80  private:
81    /** Decode status. */
82    DecodeStatus _status;
83
84    /** Per-thread status. */
85    ThreadStatus decodeStatus[Impl::MaxThreads];
86
87  public:
88    /** DefaultDecode constructor. */
89    DefaultDecode(Params *params);
90
91    /** Returns the name of decode. */
92    std::string name() const;
93
94    /** Registers statistics. */
95    void regStats();
96
97    /** Sets CPU pointer. */
98    void setCPU(FullCPU *cpu_ptr);
99
100    /** Sets the main backwards communication time buffer pointer. */
101    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
102
103    /** Sets pointer to time buffer used to communicate to the next stage. */
104    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
105
106    /** Sets pointer to time buffer coming from fetch. */
107    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
108
109    /** Sets pointer to list of active threads. */
110    void setActiveThreads(std::list<unsigned> *at_ptr);
111
112    /** Switches out the decode stage. */
113    void switchOut();
114
115    /** Takes over from another CPU's thread. */
116    void takeOverFrom();
117
118    /** Ticks decode, processing all input signals and decoding as many
119     * instructions as possible.
120     */
121    void tick();
122
123    /** Determines what to do based on decode's current status.
124     * @param status_change decode() sets this variable if there was a status
125     * change (ie switching from from blocking to unblocking).
126     * @param tid Thread id to decode instructions from.
127     */
128    void decode(bool &status_change, unsigned tid);
129
130    /** Processes instructions from fetch and passes them on to rename.
131     * Decoding of instructions actually happens when they are created in
132     * fetch, so this function mostly checks if PC-relative branches are
133     * correct.
134     */
135    void decodeInsts(unsigned tid);
136
137  private:
138    /** Inserts a thread's instructions into the skid buffer, to be decoded
139     * once decode unblocks.
140     */
141    void skidInsert(unsigned tid);
142
143    /** Returns if all of the skid buffers are empty. */
144    bool skidsEmpty();
145
146    /** Updates overall decode status based on all of the threads' statuses. */
147    void updateStatus();
148
149    /** Separates instructions from fetch into individual lists of instructions
150     * sorted by thread.
151     */
152    void sortInsts();
153
154    /** Reads all stall signals from the backwards communication timebuffer. */
155    void readStallSignals(unsigned tid);
156
157    /** Checks all input signals and updates decode's status appropriately. */
158    bool checkSignalsAndUpdate(unsigned tid);
159
160    /** Checks all stall signals, and returns if any are true. */
161    bool checkStall(unsigned tid) const;
162
163    /** Returns if there any instructions from fetch on this cycle. */
164    inline bool fetchInstsValid();
165
166    /** Switches decode to blocking, and signals back that decode has
167     * become blocked.
168     * @return Returns true if there is a status change.
169     */
170    bool block(unsigned tid);
171
172    /** Switches decode to unblocking if the skid buffer is empty, and
173     * signals back that decode has unblocked.
174     * @return Returns true if there is a status change.
175     */
176    bool unblock(unsigned tid);
177
178    /** Squashes if there is a PC-relative branch that was predicted
179     * incorrectly. Sends squash information back to fetch.
180     */
181    void squash(DynInstPtr &inst, unsigned tid);
182
183  public:
184    /** Squashes due to commit signalling a squash. Changes status to
185     * squashing and clears block/unblock signals as needed.
186     */
187    unsigned squash(unsigned tid);
188
189  private:
190    // Interfaces to objects outside of decode.
191    /** CPU interface. */
192    FullCPU *cpu;
193
194    /** Time buffer interface. */
195    TimeBuffer<TimeStruct> *timeBuffer;
196
197    /** Wire to get rename's output from backwards time buffer. */
198    typename TimeBuffer<TimeStruct>::wire fromRename;
199
200    /** Wire to get iew's information from backwards time buffer. */
201    typename TimeBuffer<TimeStruct>::wire fromIEW;
202
203    /** Wire to get commit's information from backwards time buffer. */
204    typename TimeBuffer<TimeStruct>::wire fromCommit;
205
206    /** Wire to write information heading to previous stages. */
207    // Might not be the best name as not only fetch will read it.
208    typename TimeBuffer<TimeStruct>::wire toFetch;
209
210    /** Decode instruction queue. */
211    TimeBuffer<DecodeStruct> *decodeQueue;
212
213    /** Wire used to write any information heading to rename. */
214    typename TimeBuffer<DecodeStruct>::wire toRename;
215
216    /** Fetch instruction queue interface. */
217    TimeBuffer<FetchStruct> *fetchQueue;
218
219    /** Wire to get fetch's output from fetch queue. */
220    typename TimeBuffer<FetchStruct>::wire fromFetch;
221
222    /** Queue of all instructions coming from fetch this cycle. */
223    std::queue<DynInstPtr> insts[Impl::MaxThreads];
224
225    /** Skid buffer between fetch and decode. */
226    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
227
228    /** Variable that tracks if decode has written to the time buffer this
229     * cycle. Used to tell CPU if there is activity this cycle.
230     */
231    bool wroteToTimeBuffer;
232
233    /** Source of possible stalls. */
234    struct Stalls {
235        bool rename;
236        bool iew;
237        bool commit;
238    };
239
240    /** Tracks which stages are telling decode to stall. */
241    Stalls stalls[Impl::MaxThreads];
242
243    /** Rename to decode delay, in ticks. */
244    unsigned renameToDecodeDelay;
245
246    /** IEW to decode delay, in ticks. */
247    unsigned iewToDecodeDelay;
248
249    /** Commit to decode delay, in ticks. */
250    unsigned commitToDecodeDelay;
251
252    /** Fetch to decode delay, in ticks. */
253    unsigned fetchToDecodeDelay;
254
255    /** The width of decode, in instructions. */
256    unsigned decodeWidth;
257
258    /** Index of instructions being sent to rename. */
259    unsigned toRenameIndex;
260
261    /** number of Active Threads*/
262    unsigned numThreads;
263
264    /** List of active thread ids */
265    std::list<unsigned> *activeThreads;
266
267    /** Number of branches in flight. */
268    unsigned branchCount[Impl::MaxThreads];
269
270    /** Maximum size of the skid buffer. */
271    unsigned skidBufferMax;
272
273    /** Stat for total number of idle cycles. */
274    Stats::Scalar<> decodeIdleCycles;
275    /** Stat for total number of blocked cycles. */
276    Stats::Scalar<> decodeBlockedCycles;
277    /** Stat for total number of normal running cycles. */
278    Stats::Scalar<> decodeRunCycles;
279    /** Stat for total number of unblocking cycles. */
280    Stats::Scalar<> decodeUnblockCycles;
281    /** Stat for total number of squashing cycles. */
282    Stats::Scalar<> decodeSquashCycles;
283    /** Stat for number of times a branch is resolved at decode. */
284    Stats::Scalar<> decodeBranchResolved;
285    /** Stat for number of times a branch mispredict is detected. */
286    Stats::Scalar<> decodeBranchMispred;
287    /** Stat for number of times decode detected a non-control instruction
288     * incorrectly predicted as a branch.
289     */
290    Stats::Scalar<> decodeControlMispred;
291    /** Stat for total number of decoded instructions. */
292    Stats::Scalar<> decodeDecodedInsts;
293    /** Stat for total number of squashed instructions. */
294    Stats::Scalar<> decodeSquashedInsts;
295};
296
297#endif // __CPU_O3_DECODE_HH__
298