decode.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
30#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
31
32#include <queue>
33
34#include "base/statistics.hh"
35#include "base/timebuf.hh"
36
37template<class Impl>
38class SimpleDecode
39{
40  private:
41    // Typedefs from the Impl.
42    typedef typename Impl::FullCPU FullCPU;
43    typedef typename Impl::DynInstPtr DynInstPtr;
44    typedef typename Impl::Params Params;
45    typedef typename Impl::CPUPol CPUPol;
46
47    // Typedefs from the CPU policy.
48    typedef typename CPUPol::FetchStruct FetchStruct;
49    typedef typename CPUPol::DecodeStruct DecodeStruct;
50    typedef typename CPUPol::TimeStruct TimeStruct;
51
52  public:
53    // The only time decode will become blocked is if dispatch becomes
54    // blocked, which means IQ or ROB is probably full.
55    enum Status {
56        Running,
57        Idle,
58        Squashing,
59        Blocked,
60        Unblocking
61    };
62
63  private:
64    // May eventually need statuses on a per thread basis.
65    Status _status;
66
67  public:
68    SimpleDecode(Params &params);
69
70    void regStats();
71
72    void setCPU(FullCPU *cpu_ptr);
73
74    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
75
76    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
77
78    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
79
80    void tick();
81
82    void decode();
83
84  private:
85    inline bool fetchInstsValid();
86
87    void block();
88
89    inline void unblock();
90
91    void squash(DynInstPtr &inst);
92
93  public:
94    // Might want to make squash a friend function.
95    void squash();
96
97  private:
98    // Interfaces to objects outside of decode.
99    /** CPU interface. */
100    FullCPU *cpu;
101
102    /** Time buffer interface. */
103    TimeBuffer<TimeStruct> *timeBuffer;
104
105    /** Wire to get rename's output from backwards time buffer. */
106    typename TimeBuffer<TimeStruct>::wire fromRename;
107
108    /** Wire to get iew's information from backwards time buffer. */
109    typename TimeBuffer<TimeStruct>::wire fromIEW;
110
111    /** Wire to get commit's information from backwards time buffer. */
112    typename TimeBuffer<TimeStruct>::wire fromCommit;
113
114    /** Wire to write information heading to previous stages. */
115    // Might not be the best name as not only fetch will read it.
116    typename TimeBuffer<TimeStruct>::wire toFetch;
117
118    /** Decode instruction queue. */
119    TimeBuffer<DecodeStruct> *decodeQueue;
120
121    /** Wire used to write any information heading to rename. */
122    typename TimeBuffer<DecodeStruct>::wire toRename;
123
124    /** Fetch instruction queue interface. */
125    TimeBuffer<FetchStruct> *fetchQueue;
126
127    /** Wire to get fetch's output from fetch queue. */
128    typename TimeBuffer<FetchStruct>::wire fromFetch;
129
130    /** Skid buffer between fetch and decode. */
131    std::queue<FetchStruct> skidBuffer;
132
133    //Consider making these unsigned to avoid any confusion.
134    /** Rename to decode delay, in ticks. */
135    unsigned renameToDecodeDelay;
136
137    /** IEW to decode delay, in ticks. */
138    unsigned iewToDecodeDelay;
139
140    /** Commit to decode delay, in ticks. */
141    unsigned commitToDecodeDelay;
142
143    /** Fetch to decode delay, in ticks. */
144    unsigned fetchToDecodeDelay;
145
146    /** The width of decode, in instructions. */
147    unsigned decodeWidth;
148
149    /** The instruction that decode is currently on.  It needs to have
150     *  persistent state so that when a stall occurs in the middle of a
151     *  group of instructions, it can restart at the proper instruction.
152     */
153    unsigned numInst;
154
155    Stats::Scalar<> decodeIdleCycles;
156    Stats::Scalar<> decodeBlockedCycles;
157    Stats::Scalar<> decodeUnblockCycles;
158    Stats::Scalar<> decodeSquashCycles;
159    Stats::Scalar<> decodeBranchMispred;
160    Stats::Scalar<> decodeControlMispred;
161    Stats::Scalar<> decodeDecodedInsts;
162    Stats::Scalar<> decodeSquashedInsts;
163};
164
165#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
166