decode.hh revision 2632:1bb2f91485ea
12SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
292SN/A#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
302SN/A#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
317067Snate@binkert.org
327067Snate@binkert.org#include <queue>
332SN/A
342SN/A#include "base/statistics.hh"
357067Snate@binkert.org#include "base/timebuf.hh"
362SN/A
37147SN/Atemplate<class Impl>
381158SN/Aclass SimpleDecode
39147SN/A{
40147SN/A  private:
41147SN/A    // Typedefs from the Impl.
42147SN/A    typedef typename Impl::FullCPU FullCPU;
437067Snate@binkert.org    typedef typename Impl::DynInstPtr DynInstPtr;
447067Snate@binkert.org    typedef typename Impl::Params Params;
457067Snate@binkert.org    typedef typename Impl::CPUPol CPUPol;
467067Snate@binkert.org
472SN/A    // Typedefs from the CPU policy.
48147SN/A    typedef typename CPUPol::FetchStruct FetchStruct;
49147SN/A    typedef typename CPUPol::DecodeStruct DecodeStruct;
50147SN/A    typedef typename CPUPol::TimeStruct TimeStruct;
51147SN/A
522SN/A  public:
53147SN/A    // The only time decode will become blocked is if dispatch becomes
54147SN/A    // blocked, which means IQ or ROB is probably full.
55147SN/A    enum Status {
56147SN/A        Running,
57147SN/A        Idle,
582SN/A        Squashing,
592SN/A        Blocked,
602SN/A        Unblocking
617067Snate@binkert.org    };
627067Snate@binkert.org
637067Snate@binkert.org  private:
647067Snate@binkert.org    // May eventually need statuses on a per thread basis.
657067Snate@binkert.org    Status _status;
667067Snate@binkert.org
677067Snate@binkert.org  public:
687067Snate@binkert.org    SimpleDecode(Params &params);
697067Snate@binkert.org
707067Snate@binkert.org    void regStats();
717067Snate@binkert.org
727067Snate@binkert.org    void setCPU(FullCPU *cpu_ptr);
737067Snate@binkert.org
747067Snate@binkert.org    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
757067Snate@binkert.org
767067Snate@binkert.org    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
777067Snate@binkert.org
787067Snate@binkert.org    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
797067Snate@binkert.org
807067Snate@binkert.org    void tick();
817067Snate@binkert.org
827067Snate@binkert.org    void decode();
837067Snate@binkert.org
842SN/A  private:
852SN/A    inline bool fetchInstsValid();
862SN/A
87147SN/A    void block();
88147SN/A
89147SN/A    inline void unblock();
90147SN/A
91147SN/A    void squash(DynInstPtr &inst);
92147SN/A
93147SN/A  public:
94147SN/A    // Might want to make squash a friend function.
95147SN/A    void squash();
96147SN/A
972SN/A  private:
982SN/A    // Interfaces to objects outside of decode.
997067Snate@binkert.org    /** CPU interface. */
1007067Snate@binkert.org    FullCPU *cpu;
1017067Snate@binkert.org
102147SN/A    /** Time buffer interface. */
103147SN/A    TimeBuffer<TimeStruct> *timeBuffer;
104147SN/A
105147SN/A    /** Wire to get rename's output from backwards time buffer. */
1067067Snate@binkert.org    typename TimeBuffer<TimeStruct>::wire fromRename;
1077067Snate@binkert.org
108147SN/A    /** Wire to get iew's information from backwards time buffer. */
109147SN/A    typename TimeBuffer<TimeStruct>::wire fromIEW;
110147SN/A
111147SN/A    /** Wire to get commit's information from backwards time buffer. */
1127067Snate@binkert.org    typename TimeBuffer<TimeStruct>::wire fromCommit;
1137067Snate@binkert.org
1147067Snate@binkert.org    /** Wire to write information heading to previous stages. */
1157067Snate@binkert.org    // Might not be the best name as not only fetch will read it.
1167067Snate@binkert.org    typename TimeBuffer<TimeStruct>::wire toFetch;
1177067Snate@binkert.org
1187067Snate@binkert.org    /** Decode instruction queue. */
1197067Snate@binkert.org    TimeBuffer<DecodeStruct> *decodeQueue;
1207067Snate@binkert.org
1217067Snate@binkert.org    /** Wire used to write any information heading to rename. */
1227067Snate@binkert.org    typename TimeBuffer<DecodeStruct>::wire toRename;
1237067Snate@binkert.org
1247067Snate@binkert.org    /** Fetch instruction queue interface. */
1257067Snate@binkert.org    TimeBuffer<FetchStruct> *fetchQueue;
126147SN/A
127147SN/A    /** Wire to get fetch's output from fetch queue. */
128147SN/A    typename TimeBuffer<FetchStruct>::wire fromFetch;
1292SN/A
130147SN/A    /** Skid buffer between fetch and decode. */
131147SN/A    std::queue<FetchStruct> skidBuffer;
132147SN/A
133147SN/A    //Consider making these unsigned to avoid any confusion.
1347067Snate@binkert.org    /** Rename to decode delay, in ticks. */
1357067Snate@binkert.org    unsigned renameToDecodeDelay;
136147SN/A
137147SN/A    /** IEW to decode delay, in ticks. */
138147SN/A    unsigned iewToDecodeDelay;
139147SN/A
140147SN/A    /** Commit to decode delay, in ticks. */
141147SN/A    unsigned commitToDecodeDelay;
142147SN/A
143147SN/A    /** Fetch to decode delay, in ticks. */
1442SN/A    unsigned fetchToDecodeDelay;
145147SN/A
146147SN/A    /** The width of decode, in instructions. */
147147SN/A    unsigned decodeWidth;
148147SN/A
1497067Snate@binkert.org    /** The instruction that decode is currently on.  It needs to have
1507067Snate@binkert.org     *  persistent state so that when a stall occurs in the middle of a
151147SN/A     *  group of instructions, it can restart at the proper instruction.
152147SN/A     */
153147SN/A    unsigned numInst;
1542SN/A
1552SN/A    Stats::Scalar<> decodeIdleCycles;
1567067Snate@binkert.org    Stats::Scalar<> decodeBlockedCycles;
157    Stats::Scalar<> decodeUnblockCycles;
158    Stats::Scalar<> decodeSquashCycles;
159    Stats::Scalar<> decodeBranchMispred;
160    Stats::Scalar<> decodeControlMispred;
161    Stats::Scalar<> decodeDecodedInsts;
162    Stats::Scalar<> decodeSquashedInsts;
163};
164
165#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
166