decode.hh revision 13429:a1e199fd8122 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_HH__
44#define __CPU_O3_DECODE_HH__
45
46#include <queue>
47
48#include "base/statistics.hh"
49#include "cpu/timebuf.hh"
50
51struct DerivO3CPUParams;
52
53/**
54 * DefaultDecode class handles both single threaded and SMT
55 * decode. Its width is specified by the parameters; each cycles it
56 * tries to decode that many instructions. Because instructions are
57 * actually decoded when the StaticInst is created, this stage does
58 * not do much other than check any PC-relative branches.
59 */
60template<class Impl>
61class DefaultDecode
62{
63  private:
64    // Typedefs from the Impl.
65    typedef typename Impl::O3CPU O3CPU;
66    typedef typename Impl::DynInstPtr DynInstPtr;
67    typedef typename Impl::CPUPol CPUPol;
68
69    // Typedefs from the CPU policy.
70    typedef typename CPUPol::FetchStruct FetchStruct;
71    typedef typename CPUPol::DecodeStruct DecodeStruct;
72    typedef typename CPUPol::TimeStruct TimeStruct;
73
74  public:
75    /** Overall decode stage status. Used to determine if the CPU can
76     * deschedule itself due to a lack of activity.
77     */
78    enum DecodeStatus {
79        Active,
80        Inactive
81    };
82
83    /** Individual thread status. */
84    enum ThreadStatus {
85        Running,
86        Idle,
87        StartSquash,
88        Squashing,
89        Blocked,
90        Unblocking
91    };
92
93  private:
94    /** Decode status. */
95    DecodeStatus _status;
96
97    /** Per-thread status. */
98    ThreadStatus decodeStatus[Impl::MaxThreads];
99
100  public:
101    /** DefaultDecode constructor. */
102    DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
103
104    void startupStage();
105    void resetStage();
106
107    /** Returns the name of decode. */
108    std::string name() const;
109
110    /** Registers statistics. */
111    void regStats();
112
113    /** Sets the main backwards communication time buffer pointer. */
114    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
115
116    /** Sets pointer to time buffer used to communicate to the next stage. */
117    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
118
119    /** Sets pointer to time buffer coming from fetch. */
120    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
121
122    /** Sets pointer to list of active threads. */
123    void setActiveThreads(std::list<ThreadID> *at_ptr);
124
125    /** Perform sanity checks after a drain. */
126    void drainSanityCheck() const;
127
128    /** Has the stage drained? */
129    bool isDrained() const;
130
131    /** Takes over from another CPU's thread. */
132    void takeOverFrom() { resetStage(); }
133
134    /** Ticks decode, processing all input signals and decoding as many
135     * instructions as possible.
136     */
137    void tick();
138
139    /** Determines what to do based on decode's current status.
140     * @param status_change decode() sets this variable if there was a status
141     * change (ie switching from from blocking to unblocking).
142     * @param tid Thread id to decode instructions from.
143     */
144    void decode(bool &status_change, ThreadID tid);
145
146    /** Processes instructions from fetch and passes them on to rename.
147     * Decoding of instructions actually happens when they are created in
148     * fetch, so this function mostly checks if PC-relative branches are
149     * correct.
150     */
151    void decodeInsts(ThreadID tid);
152
153  private:
154    /** Inserts a thread's instructions into the skid buffer, to be decoded
155     * once decode unblocks.
156     */
157    void skidInsert(ThreadID tid);
158
159    /** Returns if all of the skid buffers are empty. */
160    bool skidsEmpty();
161
162    /** Updates overall decode status based on all of the threads' statuses. */
163    void updateStatus();
164
165    /** Separates instructions from fetch into individual lists of instructions
166     * sorted by thread.
167     */
168    void sortInsts();
169
170    /** Reads all stall signals from the backwards communication timebuffer. */
171    void readStallSignals(ThreadID tid);
172
173    /** Checks all input signals and updates decode's status appropriately. */
174    bool checkSignalsAndUpdate(ThreadID tid);
175
176    /** Checks all stall signals, and returns if any are true. */
177    bool checkStall(ThreadID tid) const;
178
179    /** Returns if there any instructions from fetch on this cycle. */
180    inline bool fetchInstsValid();
181
182    /** Switches decode to blocking, and signals back that decode has
183     * become blocked.
184     * @return Returns true if there is a status change.
185     */
186    bool block(ThreadID tid);
187
188    /** Switches decode to unblocking if the skid buffer is empty, and
189     * signals back that decode has unblocked.
190     * @return Returns true if there is a status change.
191     */
192    bool unblock(ThreadID tid);
193
194    /** Squashes if there is a PC-relative branch that was predicted
195     * incorrectly. Sends squash information back to fetch.
196     */
197    void squash(const DynInstPtr &inst, ThreadID tid);
198
199  public:
200    /** Squashes due to commit signalling a squash. Changes status to
201     * squashing and clears block/unblock signals as needed.
202     */
203    unsigned squash(ThreadID tid);
204
205  private:
206    // Interfaces to objects outside of decode.
207    /** CPU interface. */
208    O3CPU *cpu;
209
210    /** Time buffer interface. */
211    TimeBuffer<TimeStruct> *timeBuffer;
212
213    /** Wire to get rename's output from backwards time buffer. */
214    typename TimeBuffer<TimeStruct>::wire fromRename;
215
216    /** Wire to get iew's information from backwards time buffer. */
217    typename TimeBuffer<TimeStruct>::wire fromIEW;
218
219    /** Wire to get commit's information from backwards time buffer. */
220    typename TimeBuffer<TimeStruct>::wire fromCommit;
221
222    /** Wire to write information heading to previous stages. */
223    // Might not be the best name as not only fetch will read it.
224    typename TimeBuffer<TimeStruct>::wire toFetch;
225
226    /** Decode instruction queue. */
227    TimeBuffer<DecodeStruct> *decodeQueue;
228
229    /** Wire used to write any information heading to rename. */
230    typename TimeBuffer<DecodeStruct>::wire toRename;
231
232    /** Fetch instruction queue interface. */
233    TimeBuffer<FetchStruct> *fetchQueue;
234
235    /** Wire to get fetch's output from fetch queue. */
236    typename TimeBuffer<FetchStruct>::wire fromFetch;
237
238    /** Queue of all instructions coming from fetch this cycle. */
239    std::queue<DynInstPtr> insts[Impl::MaxThreads];
240
241    /** Skid buffer between fetch and decode. */
242    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
243
244    /** Variable that tracks if decode has written to the time buffer this
245     * cycle. Used to tell CPU if there is activity this cycle.
246     */
247    bool wroteToTimeBuffer;
248
249    /** Source of possible stalls. */
250    struct Stalls {
251        bool rename;
252    };
253
254    /** Tracks which stages are telling decode to stall. */
255    Stalls stalls[Impl::MaxThreads];
256
257    /** Rename to decode delay. */
258    Cycles renameToDecodeDelay;
259
260    /** IEW to decode delay. */
261    Cycles iewToDecodeDelay;
262
263    /** Commit to decode delay. */
264    Cycles commitToDecodeDelay;
265
266    /** Fetch to decode delay. */
267    Cycles fetchToDecodeDelay;
268
269    /** The width of decode, in instructions. */
270    unsigned decodeWidth;
271
272    /** Index of instructions being sent to rename. */
273    unsigned toRenameIndex;
274
275    /** number of Active Threads*/
276    ThreadID numThreads;
277
278    /** List of active thread ids */
279    std::list<ThreadID> *activeThreads;
280
281    /** Maximum size of the skid buffer. */
282    unsigned skidBufferMax;
283
284    /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
285    Addr bdelayDoneSeqNum[Impl::MaxThreads];
286
287    /** Instruction used for squashing branch (used for MIPS)*/
288    DynInstPtr squashInst[Impl::MaxThreads];
289
290    /** Tells when their is a pending delay slot inst. to send
291     *  to rename. If there is, then wait squash after the next
292     *  instruction (used for MIPS).
293     */
294    bool squashAfterDelaySlot[Impl::MaxThreads];
295
296
297    /** Stat for total number of idle cycles. */
298    Stats::Scalar decodeIdleCycles;
299    /** Stat for total number of blocked cycles. */
300    Stats::Scalar decodeBlockedCycles;
301    /** Stat for total number of normal running cycles. */
302    Stats::Scalar decodeRunCycles;
303    /** Stat for total number of unblocking cycles. */
304    Stats::Scalar decodeUnblockCycles;
305    /** Stat for total number of squashing cycles. */
306    Stats::Scalar decodeSquashCycles;
307    /** Stat for number of times a branch is resolved at decode. */
308    Stats::Scalar decodeBranchResolved;
309    /** Stat for number of times a branch mispredict is detected. */
310    Stats::Scalar decodeBranchMispred;
311    /** Stat for number of times decode detected a non-control instruction
312     * incorrectly predicted as a branch.
313     */
314    Stats::Scalar decodeControlMispred;
315    /** Stat for total number of decoded instructions. */
316    Stats::Scalar decodeDecodedInsts;
317    /** Stat for total number of squashed instructions. */
318    Stats::Scalar decodeSquashedInsts;
319};
320
321#endif // __CPU_O3_DECODE_HH__
322