commit_impl.hh revision 7851
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412965Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#include <algorithm> 452329SN/A#include <string> 462292SN/A 473577Sgblack@eecs.umich.edu#include "arch/utility.hh" 485953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 492292SN/A#include "base/loader/symtab.hh" 507813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 516221Snate@binkert.org#include "config/full_system.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 536221Snate@binkert.org#include "config/use_checker.hh" 542292SN/A#include "cpu/exetrace.hh" 551717SN/A#include "cpu/o3/commit.hh" 562292SN/A#include "cpu/o3/thread_state.hh" 576221Snate@binkert.org#include "params/DerivO3CPU.hh" 582292SN/A 592790Sktlim@umich.edu#if USE_CHECKER 602790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 612790Sktlim@umich.edu#endif 622790Sktlim@umich.edu 636221Snate@binkert.orgusing namespace std; 645529Snate@binkert.org 651061SN/Atemplate <class Impl> 662292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 676221Snate@binkert.org ThreadID _tid) 685606Snate@binkert.org : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 691060SN/A{ 705769Snate@binkert.org this->setFlags(AutoDelete); 711060SN/A} 721060SN/A 731061SN/Atemplate <class Impl> 741060SN/Avoid 752292SN/ADefaultCommit<Impl>::TrapEvent::process() 761062SN/A{ 772316SN/A // This will get reset by commit if it was switched out at the 782316SN/A // time of this event processing. 792292SN/A commit->trapSquash[tid] = true; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 832292SN/Aconst char * 845336Shines@cs.fsu.eduDefaultCommit<Impl>::TrapEvent::description() const 852292SN/A{ 864873Sstever@eecs.umich.edu return "Trap"; 872292SN/A} 882292SN/A 892292SN/Atemplate <class Impl> 905529Snate@binkert.orgDefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 914329Sktlim@umich.edu : cpu(_cpu), 924329Sktlim@umich.edu squashCounter(0), 932292SN/A iewToCommitDelay(params->iewToCommitDelay), 942292SN/A commitToIEWDelay(params->commitToIEWDelay), 952292SN/A renameToROBDelay(params->renameToROBDelay), 962292SN/A fetchToCommitDelay(params->commitToFetchDelay), 972292SN/A renameWidth(params->renameWidth), 982292SN/A commitWidth(params->commitWidth), 995529Snate@binkert.org numThreads(params->numThreads), 1002843Sktlim@umich.edu drainPending(false), 1012316SN/A switchedOut(false), 1022874Sktlim@umich.edu trapLatency(params->trapLatency) 1032292SN/A{ 1042292SN/A _status = Active; 1052292SN/A _nextStatus = Inactive; 1062980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 1072292SN/A 1082292SN/A //Convert string to lowercase 1092292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1102292SN/A (int(*)(int)) tolower); 1112292SN/A 1122292SN/A //Assign commit policy 1132292SN/A if (policy == "aggressive"){ 1142292SN/A commitPolicy = Aggressive; 1152292SN/A 1164329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Aggressive."); 1172292SN/A } else if (policy == "roundrobin"){ 1182292SN/A commitPolicy = RoundRobin; 1192292SN/A 1202292SN/A //Set-Up Priority List 1216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1222292SN/A priority_list.push_back(tid); 1232292SN/A } 1242292SN/A 1254329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Round Robin."); 1262292SN/A } else if (policy == "oldestready"){ 1272292SN/A commitPolicy = OldestReady; 1282292SN/A 1294329Sktlim@umich.edu DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1302292SN/A } else { 1312292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1322292SN/A "RoundRobin,OldestReady}"); 1332292SN/A } 1342292SN/A 1356221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1366221Snate@binkert.org commitStatus[tid] = Idle; 1376221Snate@binkert.org changedROBNumEntries[tid] = false; 1386221Snate@binkert.org checkEmptyROB[tid] = false; 1396221Snate@binkert.org trapInFlight[tid] = false; 1406221Snate@binkert.org committedStores[tid] = false; 1416221Snate@binkert.org trapSquash[tid] = false; 1426221Snate@binkert.org tcSquash[tid] = false; 1437720Sgblack@eecs.umich.edu pc[tid].set(0); 1442292SN/A } 1453640Sktlim@umich.edu#if FULL_SYSTEM 1463640Sktlim@umich.edu interrupt = NoFault; 1473640Sktlim@umich.edu#endif 1482292SN/A} 1492292SN/A 1502292SN/Atemplate <class Impl> 1512292SN/Astd::string 1522292SN/ADefaultCommit<Impl>::name() const 1532292SN/A{ 1542292SN/A return cpu->name() + ".commit"; 1552292SN/A} 1562292SN/A 1572292SN/Atemplate <class Impl> 1582292SN/Avoid 1592292SN/ADefaultCommit<Impl>::regStats() 1602132SN/A{ 1612301SN/A using namespace Stats; 1621062SN/A commitCommittedInsts 1631062SN/A .name(name() + ".commitCommittedInsts") 1641062SN/A .desc("The number of committed instructions") 1651062SN/A .prereq(commitCommittedInsts); 1661062SN/A commitSquashedInsts 1671062SN/A .name(name() + ".commitSquashedInsts") 1681062SN/A .desc("The number of squashed insts skipped by commit") 1691062SN/A .prereq(commitSquashedInsts); 1701062SN/A commitSquashEvents 1711062SN/A .name(name() + ".commitSquashEvents") 1721062SN/A .desc("The number of times commit is told to squash") 1731062SN/A .prereq(commitSquashEvents); 1741062SN/A commitNonSpecStalls 1751062SN/A .name(name() + ".commitNonSpecStalls") 1761062SN/A .desc("The number of times commit has been forced to stall to " 1771062SN/A "communicate backwards") 1781062SN/A .prereq(commitNonSpecStalls); 1791062SN/A branchMispredicts 1801062SN/A .name(name() + ".branchMispredicts") 1811062SN/A .desc("The number of times a branch was mispredicted") 1821062SN/A .prereq(branchMispredicts); 1832292SN/A numCommittedDist 1841062SN/A .init(0,commitWidth,1) 1851062SN/A .name(name() + ".COM:committed_per_cycle") 1861062SN/A .desc("Number of insts commited each cycle") 1871062SN/A .flags(Stats::pdf) 1881062SN/A ; 1892301SN/A 1902316SN/A statComInst 1916221Snate@binkert.org .init(cpu->numThreads) 1922301SN/A .name(name() + ".COM:count") 1932301SN/A .desc("Number of instructions committed") 1942301SN/A .flags(total) 1952301SN/A ; 1962301SN/A 1972316SN/A statComSwp 1986221Snate@binkert.org .init(cpu->numThreads) 1992301SN/A .name(name() + ".COM:swp_count") 2002301SN/A .desc("Number of s/w prefetches committed") 2012301SN/A .flags(total) 2022301SN/A ; 2032301SN/A 2042316SN/A statComRefs 2056221Snate@binkert.org .init(cpu->numThreads) 2062301SN/A .name(name() + ".COM:refs") 2072301SN/A .desc("Number of memory references committed") 2082301SN/A .flags(total) 2092301SN/A ; 2102301SN/A 2112316SN/A statComLoads 2126221Snate@binkert.org .init(cpu->numThreads) 2132301SN/A .name(name() + ".COM:loads") 2142301SN/A .desc("Number of loads committed") 2152301SN/A .flags(total) 2162301SN/A ; 2172301SN/A 2182316SN/A statComMembars 2196221Snate@binkert.org .init(cpu->numThreads) 2202301SN/A .name(name() + ".COM:membars") 2212301SN/A .desc("Number of memory barriers committed") 2222301SN/A .flags(total) 2232301SN/A ; 2242301SN/A 2252316SN/A statComBranches 2266221Snate@binkert.org .init(cpu->numThreads) 2272301SN/A .name(name() + ".COM:branches") 2282301SN/A .desc("Number of branches committed") 2292301SN/A .flags(total) 2302301SN/A ; 2312301SN/A 2322316SN/A commitEligible 2336221Snate@binkert.org .init(cpu->numThreads) 2342301SN/A .name(name() + ".COM:bw_limited") 2352301SN/A .desc("number of insts not committed due to BW limits") 2362301SN/A .flags(total) 2372301SN/A ; 2382301SN/A 2392316SN/A commitEligibleSamples 2402301SN/A .name(name() + ".COM:bw_lim_events") 2412301SN/A .desc("number cycles where commit BW limit reached") 2422301SN/A ; 2431062SN/A} 2441062SN/A 2451062SN/Atemplate <class Impl> 2461062SN/Avoid 2472980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2482292SN/A{ 2492292SN/A thread = threads; 2502292SN/A} 2512292SN/A 2522292SN/Atemplate <class Impl> 2532292SN/Avoid 2542292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2551060SN/A{ 2561060SN/A timeBuffer = tb_ptr; 2571060SN/A 2581060SN/A // Setup wire to send information back to IEW. 2591060SN/A toIEW = timeBuffer->getWire(0); 2601060SN/A 2611060SN/A // Setup wire to read data from IEW (for the ROB). 2621060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2631060SN/A} 2641060SN/A 2651061SN/Atemplate <class Impl> 2661060SN/Avoid 2672292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2682292SN/A{ 2692292SN/A fetchQueue = fq_ptr; 2702292SN/A 2712292SN/A // Setup wire to get instructions from rename (for the ROB). 2722292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2732292SN/A} 2742292SN/A 2752292SN/Atemplate <class Impl> 2762292SN/Avoid 2772292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2781060SN/A{ 2791060SN/A renameQueue = rq_ptr; 2801060SN/A 2811060SN/A // Setup wire to get instructions from rename (for the ROB). 2821060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2831060SN/A} 2841060SN/A 2851061SN/Atemplate <class Impl> 2861060SN/Avoid 2872292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2881060SN/A{ 2891060SN/A iewQueue = iq_ptr; 2901060SN/A 2911060SN/A // Setup wire to get instructions from IEW. 2921060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2931060SN/A} 2941060SN/A 2951061SN/Atemplate <class Impl> 2961060SN/Avoid 2972292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2982292SN/A{ 2992292SN/A iewStage = iew_stage; 3002292SN/A} 3012292SN/A 3022292SN/Atemplate<class Impl> 3032292SN/Avoid 3046221Snate@binkert.orgDefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3052292SN/A{ 3062292SN/A activeThreads = at_ptr; 3072292SN/A} 3082292SN/A 3092292SN/Atemplate <class Impl> 3102292SN/Avoid 3112292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3122292SN/A{ 3136221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3146221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3152292SN/A} 3162292SN/A 3172292SN/Atemplate <class Impl> 3182292SN/Avoid 3192292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3201060SN/A{ 3211060SN/A rob = rob_ptr; 3221060SN/A} 3231060SN/A 3241061SN/Atemplate <class Impl> 3251060SN/Avoid 3262292SN/ADefaultCommit<Impl>::initStage() 3271060SN/A{ 3282292SN/A rob->setActiveThreads(activeThreads); 3292292SN/A rob->resetEntries(); 3301060SN/A 3312292SN/A // Broadcast the number of free entries. 3326221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3336221Snate@binkert.org toIEW->commitInfo[tid].usedROB = true; 3346221Snate@binkert.org toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 3356221Snate@binkert.org toIEW->commitInfo[tid].emptyROB = true; 3361060SN/A } 3371060SN/A 3384329Sktlim@umich.edu // Commit must broadcast the number of free entries it has at the 3394329Sktlim@umich.edu // start of the simulation, so it starts as active. 3404329Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 3414329Sktlim@umich.edu 3422292SN/A cpu->activityThisCycle(); 3435100Ssaidi@eecs.umich.edu trapLatency = cpu->ticks(trapLatency); 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3472863Sktlim@umich.edubool 3482843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3491060SN/A{ 3502843Sktlim@umich.edu drainPending = true; 3512863Sktlim@umich.edu 3522863Sktlim@umich.edu return false; 3532316SN/A} 3542316SN/A 3552316SN/Atemplate <class Impl> 3562316SN/Avoid 3572843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3582316SN/A{ 3592316SN/A switchedOut = true; 3602843Sktlim@umich.edu drainPending = false; 3612307SN/A rob->switchOut(); 3622307SN/A} 3632307SN/A 3642307SN/Atemplate <class Impl> 3652307SN/Avoid 3662843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3672843Sktlim@umich.edu{ 3682864Sktlim@umich.edu drainPending = false; 3692843Sktlim@umich.edu} 3702843Sktlim@umich.edu 3712843Sktlim@umich.edutemplate <class Impl> 3722843Sktlim@umich.eduvoid 3732307SN/ADefaultCommit<Impl>::takeOverFrom() 3742307SN/A{ 3752316SN/A switchedOut = false; 3762307SN/A _status = Active; 3772307SN/A _nextStatus = Inactive; 3786221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3796221Snate@binkert.org commitStatus[tid] = Idle; 3806221Snate@binkert.org changedROBNumEntries[tid] = false; 3816221Snate@binkert.org trapSquash[tid] = false; 3826221Snate@binkert.org tcSquash[tid] = false; 3832307SN/A } 3842307SN/A squashCounter = 0; 3852307SN/A rob->takeOverFrom(); 3862307SN/A} 3872307SN/A 3882307SN/Atemplate <class Impl> 3892307SN/Avoid 3902292SN/ADefaultCommit<Impl>::updateStatus() 3912132SN/A{ 3922316SN/A // reset ROB changed variable 3936221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3946221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3953867Sbinkertn@umich.edu 3963867Sbinkertn@umich.edu while (threads != end) { 3976221Snate@binkert.org ThreadID tid = *threads++; 3983867Sbinkertn@umich.edu 3992316SN/A changedROBNumEntries[tid] = false; 4002316SN/A 4012316SN/A // Also check if any of the threads has a trap pending 4022316SN/A if (commitStatus[tid] == TrapPending || 4032316SN/A commitStatus[tid] == FetchTrapPending) { 4042316SN/A _nextStatus = Active; 4052316SN/A } 4062292SN/A } 4072292SN/A 4082292SN/A if (_nextStatus == Inactive && _status == Active) { 4092292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4102733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4112292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4122292SN/A DPRINTF(Activity, "Activating stage.\n"); 4132733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4142292SN/A } 4152292SN/A 4162292SN/A _status = _nextStatus; 4172292SN/A} 4182292SN/A 4192292SN/Atemplate <class Impl> 4202292SN/Avoid 4212292SN/ADefaultCommit<Impl>::setNextStatus() 4222292SN/A{ 4232292SN/A int squashes = 0; 4242292SN/A 4256221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4266221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4272292SN/A 4283867Sbinkertn@umich.edu while (threads != end) { 4296221Snate@binkert.org ThreadID tid = *threads++; 4302292SN/A 4312292SN/A if (commitStatus[tid] == ROBSquashing) { 4322292SN/A squashes++; 4332292SN/A } 4342292SN/A } 4352292SN/A 4362702Sktlim@umich.edu squashCounter = squashes; 4372292SN/A 4382292SN/A // If commit is currently squashing, then it will have activity for the 4392292SN/A // next cycle. Set its next status as active. 4402292SN/A if (squashCounter) { 4412292SN/A _nextStatus = Active; 4422292SN/A } 4432292SN/A} 4442292SN/A 4452292SN/Atemplate <class Impl> 4462292SN/Abool 4472292SN/ADefaultCommit<Impl>::changedROBEntries() 4482292SN/A{ 4496221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4506221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4512292SN/A 4523867Sbinkertn@umich.edu while (threads != end) { 4536221Snate@binkert.org ThreadID tid = *threads++; 4542292SN/A 4552292SN/A if (changedROBNumEntries[tid]) { 4562292SN/A return true; 4572292SN/A } 4582292SN/A } 4592292SN/A 4602292SN/A return false; 4612292SN/A} 4622292SN/A 4632292SN/Atemplate <class Impl> 4646221Snate@binkert.orgsize_t 4656221Snate@binkert.orgDefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 4662292SN/A{ 4672292SN/A return rob->numFreeEntries(tid); 4682292SN/A} 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/Avoid 4726221Snate@binkert.orgDefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 4732292SN/A{ 4742292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4752292SN/A 4762292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4772292SN/A 4787823Ssteve.reinhardt@amd.com cpu->schedule(trap, curTick() + trapLatency); 4794035Sktlim@umich.edu trapInFlight[tid] = true; 4802292SN/A} 4812292SN/A 4822292SN/Atemplate <class Impl> 4832292SN/Avoid 4846221Snate@binkert.orgDefaultCommit<Impl>::generateTCEvent(ThreadID tid) 4852292SN/A{ 4864035Sktlim@umich.edu assert(!trapInFlight[tid]); 4872680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4882292SN/A 4892680Sktlim@umich.edu tcSquash[tid] = true; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4946221Snate@binkert.orgDefaultCommit<Impl>::squashAll(ThreadID tid) 4952292SN/A{ 4962292SN/A // If we want to include the squashing instruction in the squash, 4972292SN/A // then use one older sequence number. 4982292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4992292SN/A // all instructions of this thread. 5002292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 5014035Sktlim@umich.edu 0 : rob->readHeadInst(tid)->seqNum - 1; 5022292SN/A 5032292SN/A // All younger instructions will be squashed. Set the sequence 5042292SN/A // number as the youngest instruction in the ROB (0 in this case. 5052292SN/A // Hopefully nothing breaks.) 5062292SN/A youngestSeqNum[tid] = 0; 5072292SN/A 5082292SN/A rob->squash(squashed_inst, tid); 5092292SN/A changedROBNumEntries[tid] = true; 5102292SN/A 5112292SN/A // Send back the sequence number of the squashed instruction. 5122292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5132292SN/A 5142292SN/A // Send back the squash signal to tell stages that they should 5152292SN/A // squash. 5162292SN/A toIEW->commitInfo[tid].squash = true; 5172292SN/A 5182292SN/A // Send back the rob squashing signal so other stages know that 5192292SN/A // the ROB is in the process of squashing. 5202292SN/A toIEW->commitInfo[tid].robSquashing = true; 5212292SN/A 5222292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5232292SN/A toIEW->commitInfo[tid].mispredictInst = NULL; 5247720Sgblack@eecs.umich.edu 5252316SN/A toIEW->commitInfo[tid].pc = pc[tid]; 5262292SN/A} 5272316SN/A 5282316SN/Atemplate <class Impl> 5296221Snate@binkert.orgvoid 5302316SN/ADefaultCommit<Impl>::squashFromTrap(ThreadID tid) 5312316SN/A{ 5322316SN/A squashAll(tid); 5337720Sgblack@eecs.umich.edu 5342316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 5352316SN/A 5362316SN/A thread[tid]->trapPending = false; 5374035Sktlim@umich.edu thread[tid]->inSyscall = false; 5382316SN/A trapInFlight[tid] = false; 5392316SN/A 5402316SN/A trapSquash[tid] = false; 5412316SN/A 5422316SN/A commitStatus[tid] = ROBSquashing; 5432316SN/A cpu->activityThisCycle(); 5442316SN/A} 5452316SN/A 5462316SN/Atemplate <class Impl> 5476221Snate@binkert.orgvoid 5482316SN/ADefaultCommit<Impl>::squashFromTC(ThreadID tid) 5492316SN/A{ 5502292SN/A squashAll(tid); 5517720Sgblack@eecs.umich.edu 5522292SN/A DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 5532292SN/A 5542292SN/A thread[tid]->inSyscall = false; 5552316SN/A assert(!thread[tid]->trapPending); 5562292SN/A 5572292SN/A commitStatus[tid] = ROBSquashing; 5582292SN/A cpu->activityThisCycle(); 5592680Sktlim@umich.edu 5602292SN/A tcSquash[tid] = false; 5612292SN/A} 5622292SN/A 5632292SN/Atemplate <class Impl> 5647784SAli.Saidi@ARM.comvoid 5657784SAli.Saidi@ARM.comDefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) 5667784SAli.Saidi@ARM.com{ 5677784SAli.Saidi@ARM.com youngestSeqNum[tid] = squash_after_seq_num; 5687784SAli.Saidi@ARM.com 5697784SAli.Saidi@ARM.com rob->squash(squash_after_seq_num, tid); 5707784SAli.Saidi@ARM.com changedROBNumEntries[tid] = true; 5717784SAli.Saidi@ARM.com 5727784SAli.Saidi@ARM.com // Send back the sequence number of the squashed instruction. 5737784SAli.Saidi@ARM.com toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 5747784SAli.Saidi@ARM.com 5757784SAli.Saidi@ARM.com // Send back the squash signal to tell stages that they should squash. 5767784SAli.Saidi@ARM.com toIEW->commitInfo[tid].squash = true; 5777784SAli.Saidi@ARM.com 5787784SAli.Saidi@ARM.com // Send back the rob squashing signal so other stages know that 5797784SAli.Saidi@ARM.com // the ROB is in the process of squashing. 5807784SAli.Saidi@ARM.com toIEW->commitInfo[tid].robSquashing = true; 5817784SAli.Saidi@ARM.com 5827784SAli.Saidi@ARM.com toIEW->commitInfo[tid].branchMispredict = false; 5837784SAli.Saidi@ARM.com 5847784SAli.Saidi@ARM.com toIEW->commitInfo[tid].pc = pc[tid]; 5857784SAli.Saidi@ARM.com DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 5867784SAli.Saidi@ARM.com tid, squash_after_seq_num); 5877784SAli.Saidi@ARM.com commitStatus[tid] = ROBSquashing; 5887784SAli.Saidi@ARM.com} 5897784SAli.Saidi@ARM.com 5907784SAli.Saidi@ARM.comtemplate <class Impl> 5912292SN/Avoid 5922292SN/ADefaultCommit<Impl>::tick() 5932292SN/A{ 5942292SN/A wroteToTimeBuffer = false; 5952292SN/A _nextStatus = Inactive; 5962843Sktlim@umich.edu 5972843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5982843Sktlim@umich.edu cpu->signalDrained(); 5992316SN/A drainPending = false; 6002316SN/A return; 6012316SN/A } 6023867Sbinkertn@umich.edu 6032875Sksewell@umich.edu if (activeThreads->empty()) 6042875Sksewell@umich.edu return; 6056221Snate@binkert.org 6066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6072292SN/A list<ThreadID>::iterator end = activeThreads->end(); 6082316SN/A 6092316SN/A // Check if any of the threads are done squashing. Change the 6103867Sbinkertn@umich.edu // status if they are done. 6116221Snate@binkert.org while (threads != end) { 6122292SN/A ThreadID tid = *threads++; 6134035Sktlim@umich.edu 6144035Sktlim@umich.edu // Clear the bit saying if the thread has committed stores 6154035Sktlim@umich.edu // this cycle. 6164035Sktlim@umich.edu committedStores[tid] = false; 6172292SN/A 6182292SN/A if (commitStatus[tid] == ROBSquashing) { 6192292SN/A 6202292SN/A if (rob->isDoneSquashing(tid)) { 6212292SN/A commitStatus[tid] = Running; 6222292SN/A } else { 6232877Sksewell@umich.edu DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 6242702Sktlim@umich.edu " insts this cycle.\n", tid); 6252702Sktlim@umich.edu rob->doSquash(tid); 6262702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 6272292SN/A wroteToTimeBuffer = true; 6282292SN/A } 6292292SN/A } 6302292SN/A } 6312292SN/A 6322292SN/A commit(); 6332292SN/A 6342292SN/A markCompletedInsts(); 6353867Sbinkertn@umich.edu 6362292SN/A threads = activeThreads->begin(); 6373867Sbinkertn@umich.edu 6386221Snate@binkert.org while (threads != end) { 6392292SN/A ThreadID tid = *threads++; 6402292SN/A 6412292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6422292SN/A // The ROB has more instructions it can commit. Its next status 6432292SN/A // will be active. 6442292SN/A _nextStatus = Active; 6452292SN/A 6462292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6477720Sgblack@eecs.umich.edu 6482292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 6497720Sgblack@eecs.umich.edu " ROB and ready to commit\n", 6502292SN/A tid, inst->seqNum, inst->pcState()); 6512292SN/A 6522292SN/A } else if (!rob->isEmpty(tid)) { 6532292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6542292SN/A 6557720Sgblack@eecs.umich.edu DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6567720Sgblack@eecs.umich.edu "%s is head of ROB and not ready\n", 6572292SN/A tid, inst->seqNum, inst->pcState()); 6582292SN/A } 6592292SN/A 6602292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6612292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6622292SN/A } 6632292SN/A 6642292SN/A 6652316SN/A if (wroteToTimeBuffer) { 6662292SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6672292SN/A cpu->activityThisCycle(); 6682292SN/A } 6692292SN/A 6702292SN/A updateStatus(); 6712292SN/A} 6724035Sktlim@umich.edu 6732292SN/A#if FULL_SYSTEM 6742292SN/Atemplate <class Impl> 6754035Sktlim@umich.eduvoid 6762292SN/ADefaultCommit<Impl>::handleInterrupt() 6773640Sktlim@umich.edu{ 6782316SN/A // Verify that we still have an interrupt to handle 6792316SN/A if (!cpu->checkInterrupts(cpu->tcBase(0))) { 6802292SN/A DPRINTF(Commit, "Pending interrupt is cleared by master before " 6813633Sktlim@umich.edu "it got handled. Restart fetching from the orig path.\n"); 6823633Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6833633Sktlim@umich.edu interrupt = NoFault; 6843633Sktlim@umich.edu return; 6854035Sktlim@umich.edu } 6864035Sktlim@umich.edu 6874035Sktlim@umich.edu // Wait until the ROB is empty and all stores have drained in 6882292SN/A // order to enter the interrupt. 6892292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6902292SN/A // Squash or record that I need to squash this cycle if 6913633Sktlim@umich.edu // an interrupt needed to be handled. 6923640Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6932292SN/A 6943633Sktlim@umich.edu // Clear the interrupt now that it's going to be handled 6953633Sktlim@umich.edu toIEW->commitInfo[0].clearInterrupt = true; 6962292SN/A 6972292SN/A assert(!thread[0]->inSyscall); 6982292SN/A thread[0]->inSyscall = true; 6992292SN/A 7002292SN/A // CPU will handle interrupt. 7013640Sktlim@umich.edu cpu->processInterrupts(interrupt); 7022292SN/A 7032292SN/A thread[0]->inSyscall = false; 7042292SN/A 7054035Sktlim@umich.edu commitStatus[0] = TrapPending; 7065704Snate@binkert.org 7074035Sktlim@umich.edu // Generate trap squash event. 7084035Sktlim@umich.edu generateTrapEvent(0); 7093640Sktlim@umich.edu 7103640Sktlim@umich.edu interrupt = NoFault; 7113640Sktlim@umich.edu } else { 7123640Sktlim@umich.edu DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 7133640Sktlim@umich.edu } 7143640Sktlim@umich.edu} 7153640Sktlim@umich.edu 7163640Sktlim@umich.edutemplate <class Impl> 7173640Sktlim@umich.eduvoid 7183640Sktlim@umich.eduDefaultCommit<Impl>::propagateInterrupt() 7193640Sktlim@umich.edu{ 7203640Sktlim@umich.edu if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 7213640Sktlim@umich.edu tcSquash[0]) 7223640Sktlim@umich.edu return; 7231060SN/A 7244035Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 7254035Sktlim@umich.edu // mode, and no other traps or external squashes are currently 7263634Sktlim@umich.edu // pending. 7274035Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 7284035Sktlim@umich.edu 7294035Sktlim@umich.edu // Get any interrupt that happened 7304035Sktlim@umich.edu interrupt = cpu->getInterrupts(); 7314035Sktlim@umich.edu 7324035Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 7334035Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 7344035Sktlim@umich.edu // at which point it stops fetching instructions. 7354035Sktlim@umich.edu if (interrupt != NoFault) 7365704Snate@binkert.org toIEW->commitInfo[0].interruptPending = true; 7374035Sktlim@umich.edu} 7384035Sktlim@umich.edu 7391060SN/A#endif // FULL_SYSTEM 7401060SN/A 7411060SN/Atemplate <class Impl> 7422316SN/Avoid 7431060SN/ADefaultCommit<Impl>::commit() 7446221Snate@binkert.org{ 7456221Snate@binkert.org 7461060SN/A#if FULL_SYSTEM 7473867Sbinkertn@umich.edu // Check for any interrupt that we've already squashed for and start processing it. 7486221Snate@binkert.org if (interrupt != NoFault) 7491060SN/A handleInterrupt(); 7502292SN/A 7512292SN/A // Check if we have a interrupt and get read to handle it 7522292SN/A if (cpu->checkInterrupts(cpu->tcBase(0))) 7532680Sktlim@umich.edu propagateInterrupt(); 7542292SN/A#endif // FULL_SYSTEM 7552680Sktlim@umich.edu 7564035Sktlim@umich.edu //////////////////////////////////// 7572680Sktlim@umich.edu // Check for any possible squashes, handle them first 7582292SN/A //////////////////////////////////// 7591061SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 7602292SN/A list<ThreadID>::iterator end = activeThreads->end(); 7612292SN/A 7622292SN/A while (threads != end) { 7632292SN/A ThreadID tid = *threads++; 7642292SN/A 7652292SN/A // Not sure which one takes priority. I think if we have 7661061SN/A // both, that's a bad sign. 7672292SN/A if (trapSquash[tid] == true) { 7682292SN/A assert(!tcSquash[tid]); 7692292SN/A squashFromTrap(tid); 7702292SN/A } else if (tcSquash[tid] == true) { 7711061SN/A assert(commitStatus[tid] != TrapPending); 7722292SN/A squashFromTC(tid); 7732292SN/A } 7747720Sgblack@eecs.umich.edu 7751061SN/A // Squashed sequence number must be older than youngest valid 7762292SN/A // instruction in the ROB. This prevents squashes from younger 7771061SN/A // instructions overriding squashes from older instructions. 7782292SN/A if (fromIEW->squash[tid] && 7792292SN/A commitStatus[tid] != TrapPending && 7802292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7811062SN/A 7822935Sksewell@umich.edu DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7832292SN/A tid, 7842935Sksewell@umich.edu fromIEW->mispredPC[tid], 7854035Sktlim@umich.edu fromIEW->squashedSeqNum[tid]); 7862292SN/A 7872292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7882292SN/A tid, 7892292SN/A fromIEW->pc[tid].nextInstAddr()); 7903093Sksewell@umich.edu 7912292SN/A commitStatus[tid] = ROBSquashing; 7922292SN/A 7932292SN/A // If we want to include the squashing instruction in the squash, 7942292SN/A // then use one older sequence number. 7952292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7962292SN/A 7972292SN/A if (fromIEW->includeSquashInst[tid] == true) { 7982292SN/A squashed_inst--; 7992292SN/A } 8002292SN/A 8012292SN/A // All younger instructions will be squashed. Set the sequence 8022292SN/A // number as the youngest instruction in the ROB. 8032292SN/A youngestSeqNum[tid] = squashed_inst; 8042292SN/A 8052292SN/A rob->squash(squashed_inst, tid); 8062292SN/A changedROBNumEntries[tid] = true; 8077720Sgblack@eecs.umich.edu 8082292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 8092316SN/A 8102292SN/A toIEW->commitInfo[tid].squash = true; 8112292SN/A 8122292SN/A // Send back the rob squashing signal so other stages know that 8132292SN/A // the ROB is in the process of squashing. 8141062SN/A toIEW->commitInfo[tid].robSquashing = true; 8152292SN/A 8161060SN/A toIEW->commitInfo[tid].branchMispredict = 8171060SN/A fromIEW->branchMispredict[tid]; 8182292SN/A toIEW->commitInfo[tid].mispredictInst = 8192292SN/A fromIEW->mispredictInst[tid]; 8202292SN/A toIEW->commitInfo[tid].branchTaken = 8211061SN/A fromIEW->branchTaken[tid]; 8221060SN/A 8231060SN/A toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 8241061SN/A 8251060SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 8261060SN/A 8271060SN/A if (toIEW->commitInfo[tid].branchMispredict) { 8282292SN/A ++branchMispredicts; 8293867Sbinkertn@umich.edu } 8302292SN/A } 8313867Sbinkertn@umich.edu 8326221Snate@binkert.org } 8332292SN/A 8342292SN/A setNextStatus(); 8352292SN/A 8362292SN/A if (squashCounter != numThreads) { 8372292SN/A // If we're not currently squashing, then get instructions. 8382292SN/A getInsts(); 8392292SN/A 8404035Sktlim@umich.edu // Try to commit any instructions. 8414035Sktlim@umich.edu commitInsts(); 8422292SN/A } 8434035Sktlim@umich.edu 8444035Sktlim@umich.edu //Check for any activity 8454035Sktlim@umich.edu threads = activeThreads->begin(); 8464035Sktlim@umich.edu 8474035Sktlim@umich.edu while (threads != end) { 8484035Sktlim@umich.edu ThreadID tid = *threads++; 8494035Sktlim@umich.edu 8504035Sktlim@umich.edu if (changedROBNumEntries[tid]) { 8514035Sktlim@umich.edu toIEW->commitInfo[tid].usedROB = true; 8524035Sktlim@umich.edu toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8535557Sktlim@umich.edu 8544035Sktlim@umich.edu wroteToTimeBuffer = true; 8554035Sktlim@umich.edu changedROBNumEntries[tid] = false; 8564035Sktlim@umich.edu if (rob->isEmpty(tid)) 8574035Sktlim@umich.edu checkEmptyROB[tid] = true; 8584035Sktlim@umich.edu } 8594035Sktlim@umich.edu 8604035Sktlim@umich.edu // ROB is only considered "empty" for previous stages if: a) 8611060SN/A // ROB is empty, b) there are no outstanding stores, c) IEW 8621060SN/A // stage has received any information regarding stores that 8631060SN/A // committed. 8641061SN/A // c) is checked by making sure to not consider the ROB empty 8651060SN/A // on the same cycle as when stores have been committed. 8662292SN/A // @todo: Make this handle multi-cycle communication between 8671060SN/A // commit and IEW. 8681060SN/A if (checkEmptyROB[tid] && rob->isEmpty(tid) && 8691060SN/A !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 8702316SN/A checkEmptyROB[tid] = false; 8712316SN/A toIEW->commitInfo[tid].usedROB = true; 8722316SN/A toIEW->commitInfo[tid].emptyROB = true; 8732316SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8742316SN/A wroteToTimeBuffer = true; 8751060SN/A } 8761060SN/A 8772292SN/A } 8781060SN/A} 8791060SN/A 8801060SN/Atemplate <class Impl> 8812292SN/Avoid 8822316SN/ADefaultCommit<Impl>::commitInsts() 8831060SN/A{ 8841060SN/A //////////////////////////////////// 8852292SN/A // Handle commit 8862292SN/A // Note that commit will be handled prior to putting new 8871060SN/A // instructions in the ROB so that the ROB only tries to commit 8882292SN/A // instructions it has in this current cycle, and not instructions 8892292SN/A // it is writing in during this cycle. Can't commit and squash 8902292SN/A // things at the same time... 8912292SN/A //////////////////////////////////// 8922292SN/A 8936221Snate@binkert.org DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8942292SN/A 8952292SN/A unsigned num_committed = 0; 8962292SN/A 8972292SN/A DynInstPtr head_inst; 8982292SN/A 8992132SN/A // Commit as many instructions as possible until the commit bandwidth 9002316SN/A // limit is reached, or it becomes impossible to commit any more. 9012316SN/A while (num_committed < commitWidth) { 9021060SN/A int commit_thread = getCommittingThread(); 9031060SN/A 9042292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 9051060SN/A break; 9061060SN/A 9072292SN/A head_inst = rob->readHeadInst(commit_thread); 9081060SN/A 9091062SN/A ThreadID tid = head_inst->threadNumber; 9101062SN/A 9112292SN/A assert(tid == commit_thread); 9122292SN/A 9131060SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 9147720Sgblack@eecs.umich.edu head_inst->seqNum, tid); 9152292SN/A 9161060SN/A // If the head instruction is squashed, it is ready to retire 9171060SN/A // (be removed from the ROB) at any time. 9181060SN/A if (head_inst->isSquashed()) { 9191061SN/A 9201061SN/A DPRINTF(Commit, "Retiring squashed instruction from " 9212292SN/A "ROB.\n"); 9221060SN/A 9231060SN/A rob->retireHead(commit_thread); 9241060SN/A 9251060SN/A ++commitSquashedInsts; 9261062SN/A 9271060SN/A // Record that the number of ROB entries has changed. 9281060SN/A changedROBNumEntries[tid] = true; 9292292SN/A } else { 9302292SN/A pc[tid] = head_inst->pcState(); 9312292SN/A 9322292SN/A // Increment the total number of non-speculative instructions 9331060SN/A // executed. 9341062SN/A // Hack for now: it really shouldn't happen until after the 9351062SN/A // commit is deemed to be successful, but this count is needed 9362292SN/A // for syscalls. 9372292SN/A thread[tid]->funcExeInst++; 9382292SN/A 9392292SN/A // Try to commit the head instruction. 9401062SN/A bool commit_success = commitHead(head_inst, num_committed); 9412292SN/A 9427783SGiacomo.Gabrielli@arm.com if (commit_success) { 9437783SGiacomo.Gabrielli@arm.com ++num_committed; 9447783SGiacomo.Gabrielli@arm.com 9457720Sgblack@eecs.umich.edu changedROBNumEntries[tid] = true; 9462935Sksewell@umich.edu 9477784SAli.Saidi@ARM.com // Set the doneSeqNum to the youngest committed instruction. 9487784SAli.Saidi@ARM.com toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 9497784SAli.Saidi@ARM.com 9507784SAli.Saidi@ARM.com ++commitCommittedInsts; 9517784SAli.Saidi@ARM.com 9522292SN/A // To match the old model, don't count nops and instruction 9532292SN/A // prefetches towards the total commit count. 9545108Sgblack@eecs.umich.edu if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 9555108Sgblack@eecs.umich.edu cpu->instDone(tid); 9565108Sgblack@eecs.umich.edu } 9572292SN/A 9587720Sgblack@eecs.umich.edu // Updates misc. registers. 9595108Sgblack@eecs.umich.edu head_inst->updateMiscRegs(); 9602292SN/A 9617720Sgblack@eecs.umich.edu TheISA::advancePC(pc[tid], head_inst->staticInst); 9622292SN/A 9635108Sgblack@eecs.umich.edu // If this is an instruction that doesn't play nicely with 9645108Sgblack@eecs.umich.edu // others squash everything and restart fetch 9652292SN/A if (head_inst->isSquashAfter()) 9662292SN/A squashAfter(tid, head_inst->seqNum); 9671060SN/A 9687720Sgblack@eecs.umich.edu int count = 0; 9692292SN/A Addr oldpc; 9707720Sgblack@eecs.umich.edu // Debug statement. Checks to make sure we're not 9711060SN/A // currently updating state while handling PC events. 9721060SN/A assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 9731060SN/A do { 9741060SN/A oldpc = pc[tid].instAddr(); 9751062SN/A cpu->system->pcEventQueue.service(thread[tid]->getTC()); 9761063SN/A count++; 9772292SN/A } while (oldpc != pc[tid].instAddr()); 9782307SN/A if (count > 1) { 9792307SN/A DPRINTF(Commit, 9802349SN/A "PC skip function event, stopping commit\n"); 9812307SN/A break; 9821060SN/A } 9831060SN/A } else { 9841061SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%s " 9851060SN/A "[tid:%i] [sn:%i].\n", 9862292SN/A head_inst->pcState(), tid ,head_inst->seqNum); 9871060SN/A break; 9881060SN/A } 9891060SN/A } 9906221Snate@binkert.org } 9912292SN/A 9922316SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9932316SN/A numCommittedDist.sample(num_committed); 9941061SN/A 9951061SN/A if (num_committed == commitWidth) { 9961061SN/A commitEligibleSamples++; 9972292SN/A } 9981062SN/A} 9992292SN/A 10002348SN/Atemplate <class Impl> 10012292SN/Abool 10022292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 10032316SN/A{ 10042316SN/A assert(head_inst); 10057720Sgblack@eecs.umich.edu 10067720Sgblack@eecs.umich.edu ThreadID tid = head_inst->threadNumber; 10072316SN/A 10085557Sktlim@umich.edu // If the instruction is not executed yet, then it will need extra 10092292SN/A // handling. Signal backwards that it should be executed. 10102292SN/A if (!head_inst->isExecuted()) { 10112292SN/A // Keep this number correct. We have not yet actually executed 10122292SN/A // and committed this instruction. 10132292SN/A thread[tid]->funcExeInst--; 10141061SN/A 10151061SN/A if (head_inst->isNonSpeculative() || 10161061SN/A head_inst->isStoreConditional() || 10171061SN/A head_inst->isMemBarrier() || 10181061SN/A head_inst->isWriteBarrier()) { 10191062SN/A 10201062SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 10211061SN/A "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 10222292SN/A head_inst->seqNum, head_inst->pcState()); 10235557Sktlim@umich.edu 10244035Sktlim@umich.edu if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10254035Sktlim@umich.edu DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10264035Sktlim@umich.edu return false; 10274035Sktlim@umich.edu } 10284035Sktlim@umich.edu 10297720Sgblack@eecs.umich.edu toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10307720Sgblack@eecs.umich.edu 10312292SN/A // Change the instruction so it won't try to commit again until 10322292SN/A // it is executed. 10332316SN/A head_inst->clearCanCommit(); 10342292SN/A 10352292SN/A ++commitNonSpecStalls; 10362292SN/A 10372292SN/A return false; 10382292SN/A } else if (head_inst->isLoad()) { 10392292SN/A if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 10402292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 10411061SN/A return false; 10422292SN/A } 10431061SN/A 10441061SN/A assert(head_inst->uncacheable()); 10451060SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 10461060SN/A head_inst->seqNum, head_inst->pcState()); 10472316SN/A 10482292SN/A // Send back the non-speculative instruction's sequence 10492316SN/A // number. Tell the lsq to re-execute the load. 10502132SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10512132SN/A toIEW->commitInfo[tid].uncached = true; 10524035Sktlim@umich.edu toIEW->commitInfo[tid].uncachedLoad = head_inst; 10534035Sktlim@umich.edu 10544035Sktlim@umich.edu head_inst->clearCanCommit(); 10552316SN/A 10564035Sktlim@umich.edu return false; 10572310SN/A } else { 10582310SN/A panic("Trying to commit un-executed instruction " 10592310SN/A "of unknown type!\n"); 10602733Sktlim@umich.edu } 10612316SN/A } 10622316SN/A 10632316SN/A if (head_inst->isThreadSync()) { 10642732Sktlim@umich.edu // Not handled for now. 10651060SN/A panic("Thread sync instructions are not handled yet.\n"); 10662733Sktlim@umich.edu } 10671060SN/A 10682112SN/A // Check if the instruction caused a fault. If so, trap. 10697720Sgblack@eecs.umich.edu Fault inst_fault = head_inst->getFault(); 10707720Sgblack@eecs.umich.edu 10712292SN/A // Stores mark themselves as completed. 10725557Sktlim@umich.edu if (!head_inst->isStore() && inst_fault == NoFault) { 10732316SN/A head_inst->setCompleted(); 10742316SN/A } 10752316SN/A 10762310SN/A#if USE_CHECKER 10774035Sktlim@umich.edu // Use checker prior to updating anything due to traps or PC 10784035Sktlim@umich.edu // based events. 10792733Sktlim@umich.edu if (cpu->checker) { 10802316SN/A cpu->checker->verify(head_inst); 10812732Sktlim@umich.edu } 10822316SN/A#endif 10832733Sktlim@umich.edu 10842292SN/A if (inst_fault != NoFault) { 10852316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 10862292SN/A head_inst->seqNum, head_inst->pcState()); 10872316SN/A 10882316SN/A if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 10892316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10902292SN/A return false; 10912316SN/A } 10922316SN/A 10932316SN/A head_inst->setCompleted(); 10942316SN/A 10952316SN/A#if USE_CHECKER 10962316SN/A if (cpu->checker && head_inst->isStore()) { 10977684Sgblack@eecs.umich.edu cpu->checker->verify(head_inst); 10982292SN/A } 10992316SN/A#endif 11002316SN/A 11012292SN/A assert(!thread[tid]->inSyscall); 11022316SN/A 11032292SN/A // Mark that we're in state update mode so that the trap's 11044035Sktlim@umich.edu // execution doesn't generate extra squashes. 11056667Ssteve.reinhardt@amd.com thread[tid]->inSyscall = true; 11066667Ssteve.reinhardt@amd.com 11076667Ssteve.reinhardt@amd.com // Execute the trap. Although it's slightly unrealistic in 11086667Ssteve.reinhardt@amd.com // terms of timing (as it doesn't wait for the full timing of 11096667Ssteve.reinhardt@amd.com // the trap event to complete before updating state), it's 11104288Sktlim@umich.edu // needed to update the state as soon as possible. This 11114035Sktlim@umich.edu // prevents external agents from changing any specific state 11124035Sktlim@umich.edu // that the trap need. 11134035Sktlim@umich.edu cpu->trap(inst_fault, tid, head_inst->staticInst); 11142316SN/A 11152316SN/A // Exit state update mode to avoid accidental updating. 11162316SN/A thread[tid]->inSyscall = false; 11171060SN/A 11181060SN/A commitStatus[tid] = TrapPending; 11192301SN/A 11202132SN/A if (head_inst->traceData) { 11212362SN/A if (DTRACE(ExecFaulting)) { 11222362SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11237720Sgblack@eecs.umich.edu head_inst->traceData->setCPSeq(thread[tid]->numInst); 11243126Sktlim@umich.edu head_inst->traceData->dump(); 11252362SN/A } 11262362SN/A delete head_inst->traceData; 11272362SN/A head_inst->traceData = NULL; 11282362SN/A } 11292362SN/A 11305953Ssaidi@eecs.umich.edu // Generate trap squash event. 11315953Ssaidi@eecs.umich.edu generateTrapEvent(tid); 11325953Ssaidi@eecs.umich.edu return false; 11337720Sgblack@eecs.umich.edu } 11345953Ssaidi@eecs.umich.edu 11355953Ssaidi@eecs.umich.edu updateComInstStats(head_inst); 11362362SN/A 11372362SN/A#if FULL_SYSTEM 11382132SN/A if (thread[tid]->profile) { 11392292SN/A thread[tid]->profilePC = head_inst->instAddr(); 11402292SN/A ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 11414046Sbinkertn@umich.edu head_inst->staticInst); 11424046Sbinkertn@umich.edu 11432292SN/A if (node) 11441060SN/A thread[tid]->profileNode = node; 11451060SN/A } 11462292SN/A if (CPA::available()) { 11472292SN/A if (head_inst->isControl()) { 11483771Sgblack@eecs.umich.edu ThreadContext *tc = thread[tid]->getTC(); 11492292SN/A CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 11501060SN/A } 11511062SN/A } 11522353SN/A#endif 11532353SN/A 11542353SN/A if (head_inst->traceData) { 11552292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 11562292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 11571060SN/A head_inst->traceData->dump(); 11584035Sktlim@umich.edu delete head_inst->traceData; 11594035Sktlim@umich.edu head_inst->traceData = NULL; 11604035Sktlim@umich.edu } 11614035Sktlim@umich.edu 11621060SN/A // Update the commit rename map 11631060SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11641060SN/A renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11651060SN/A head_inst->renamedDestRegIdx(i)); 11661061SN/A } 11671060SN/A 11682292SN/A if (head_inst->isCopy()) 11691060SN/A panic("Should not commit any copy instructions!"); 11702935Sksewell@umich.edu 11712935Sksewell@umich.edu // Finally clear the head ROB entry. 11723093Sksewell@umich.edu rob->retireHead(tid); 11733093Sksewell@umich.edu 11742965Sksewell@umich.edu // If this was a store, record it for this cycle. 11752965Sksewell@umich.edu if (head_inst->isStore()) 11762965Sksewell@umich.edu committedStores[tid] = true; 11772965Sksewell@umich.edu 11783093Sksewell@umich.edu // Return true to indicate that we have committed an instruction. 11796221Snate@binkert.org return true; 11802292SN/A} 11812292SN/A 11824035Sktlim@umich.edutemplate <class Impl> 11834035Sktlim@umich.eduvoid 11842292SN/ADefaultCommit<Impl>::getInsts() 11852292SN/A{ 11867720Sgblack@eecs.umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11877720Sgblack@eecs.umich.edu 11882292SN/A // Read any renamed instructions and place them into the ROB. 11892292SN/A int insts_to_process = std::min((int)renameWidth, fromRename->size); 11902292SN/A 11912292SN/A for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11922292SN/A DynInstPtr inst; 11932292SN/A 11941061SN/A inst = fromRename->insts[inst_num]; 11957720Sgblack@eecs.umich.edu ThreadID tid = inst->threadNumber; 11961061SN/A 11977720Sgblack@eecs.umich.edu if (!inst->isSquashed() && 11981061SN/A commitStatus[tid] != ROBSquashing && 11991060SN/A commitStatus[tid] != TrapPending) { 12002965Sksewell@umich.edu changedROBNumEntries[tid] = true; 12012965Sksewell@umich.edu 12022965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 12032965Sksewell@umich.edu inst->pcState(), inst->seqNum, tid); 12042965Sksewell@umich.edu 12052965Sksewell@umich.edu rob->insertInst(inst); 12062965Sksewell@umich.edu 12072965Sksewell@umich.edu assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 12082965Sksewell@umich.edu 12092965Sksewell@umich.edu youngestSeqNum[tid] = inst->seqNum; 12102965Sksewell@umich.edu } else { 12112965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12122965Sksewell@umich.edu "squashed, skipping.\n", 12137720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, tid); 12147720Sgblack@eecs.umich.edu } 12153221Sktlim@umich.edu } 12162965Sksewell@umich.edu} 12172965Sksewell@umich.edu 12187720Sgblack@eecs.umich.edutemplate <class Impl> 12192965Sksewell@umich.eduvoid 12207720Sgblack@eecs.umich.eduDefaultCommit<Impl>::skidInsert() 12212965Sksewell@umich.edu{ 12222965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12231060SN/A "skidBuffer.\n"); 12241060SN/A 12251061SN/A for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12261060SN/A DynInstPtr inst = fromRename->insts[inst_num]; 12272292SN/A 12281060SN/A if (!inst->isSquashed()) { 12291060SN/A DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 12301060SN/A "skidBuffer.\n", inst->pcState(), inst->seqNum, 12311060SN/A inst->threadNumber); 12321681SN/A skidBuffer.push(inst); 12331060SN/A } else { 12341060SN/A DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 12352292SN/A "squashed, skipping.\n", 12367720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->threadNumber); 12372316SN/A } 12382292SN/A } 12397720Sgblack@eecs.umich.edu} 12402292SN/A 12411060SN/Atemplate <class Impl> 12422292SN/Avoid 12432292SN/ADefaultCommit<Impl>::markCompletedInsts() 12442292SN/A{ 12451060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12461060SN/A // instructions completed within the ROB. 12471060SN/A for (int inst_num = 0; 12481061SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12492292SN/A ++inst_num) 12502292SN/A { 12511060SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12526221Snate@binkert.org DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 12536221Snate@binkert.org "within ROB.\n", 12542292SN/A fromIEW->insts[inst_num]->threadNumber, 12553867Sbinkertn@umich.edu fromIEW->insts[inst_num]->pcState(), 12566221Snate@binkert.org fromIEW->insts[inst_num]->seqNum); 12572292SN/A 12582292SN/A // Mark the instruction as ready to commit. 12592292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12602292SN/A } 12612292SN/A } 12622292SN/A} 12631060SN/A 12642292SN/Atemplate <class Impl> 12652301SN/Abool 12662301SN/ADefaultCommit<Impl>::robDoneSquashing() 12672301SN/A{ 12682301SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 12696221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12702301SN/A 12712301SN/A while (threads != end) { 12722301SN/A ThreadID tid = *threads++; 12732301SN/A 12742301SN/A if (!rob->isDoneSquashing(tid)) 12752301SN/A return false; 12766221Snate@binkert.org } 12772301SN/A 12786221Snate@binkert.org return true; 12792301SN/A} 12802301SN/A 12816221Snate@binkert.orgtemplate <class Impl> 12822301SN/Avoid 12832301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12842301SN/A{ 12852301SN/A ThreadID tid = inst->threadNumber; 12862301SN/A 12872301SN/A // 12886221Snate@binkert.org // Pick off the software prefetches 12892301SN/A // 12902301SN/A#ifdef TARGET_ALPHA 12912301SN/A if (inst->isDataPrefetch()) { 12922301SN/A statComSwp[tid]++; 12932301SN/A } else { 12946221Snate@binkert.org statComInst[tid]++; 12952301SN/A } 12962301SN/A#else 12976221Snate@binkert.org statComInst[tid]++; 12982301SN/A#endif 12992301SN/A 13002301SN/A // 13012301SN/A // Control Instructions 13026221Snate@binkert.org // 13032301SN/A if (inst->isControl()) 13042301SN/A statComBranches[tid]++; 13052301SN/A 13062292SN/A // 13072292SN/A // Memory references 13082316SN/A // 13092292SN/A if (inst->isMemRef()) { 13102292SN/A statComRefs[tid]++; 13112292SN/A 13126221Snate@binkert.org if (inst->isLoad()) { 13132292SN/A statComLoads[tid]++; 13142292SN/A } 13152292SN/A } 13162292SN/A 13172292SN/A if (inst->isMemBarrier()) { 13182292SN/A statComMembars[tid]++; 13192292SN/A } 13202292SN/A} 13212292SN/A 13222292SN/A//////////////////////////////////////// 13232292SN/A// // 13242292SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13252292SN/A// // 13262292SN/A//////////////////////////////////////// 13272292SN/Atemplate <class Impl> 13282292SN/AThreadID 13292292SN/ADefaultCommit<Impl>::getCommittingThread() 13302292SN/A{ 13316221Snate@binkert.org if (numThreads > 1) { 13322292SN/A switch (commitPolicy) { 13332292SN/A 13343867Sbinkertn@umich.edu case Aggressive: 13356221Snate@binkert.org //If Policy is Aggressive, commit will call 13362292SN/A //this function multiple times per 13372292SN/A //cycle 13382292SN/A return oldestReady(); 13392292SN/A 13402292SN/A case RoundRobin: 13412292SN/A return roundRobin(); 13426221Snate@binkert.org 13432292SN/A case OldestReady: 13442292SN/A return oldestReady(); 13452292SN/A 13462292SN/A default: 13472292SN/A return InvalidThreadID; 13486221Snate@binkert.org } 13492292SN/A } else { 13502292SN/A assert(!activeThreads->empty()); 13516221Snate@binkert.org ThreadID tid = activeThreads->front(); 13526221Snate@binkert.org 13532292SN/A if (commitStatus[tid] == Running || 13542292SN/A commitStatus[tid] == Idle || 13556221Snate@binkert.org commitStatus[tid] == FetchTrapPending) { 13562292SN/A return tid; 13572292SN/A } else { 13582831Sksewell@umich.edu return InvalidThreadID; 13592831Sksewell@umich.edu } 13602292SN/A } 13612292SN/A} 13622292SN/A 13632292SN/Atemplate<class Impl> 13642292SN/AThreadID 13652292SN/ADefaultCommit<Impl>::roundRobin() 13662292SN/A{ 13672292SN/A list<ThreadID>::iterator pri_iter = priority_list.begin(); 13682292SN/A list<ThreadID>::iterator end = priority_list.end(); 13692292SN/A 13702292SN/A while (pri_iter != end) { 13712292SN/A ThreadID tid = *pri_iter; 13726221Snate@binkert.org 13732292SN/A if (commitStatus[tid] == Running || 13742292SN/A commitStatus[tid] == Idle || 13752292SN/A commitStatus[tid] == FetchTrapPending) { 13766221Snate@binkert.org 13772292SN/A if (rob->isHeadReady(tid)) { 13782292SN/A priority_list.erase(pri_iter); 13792292SN/A priority_list.push_back(tid); 13802292SN/A 13812292SN/A return tid; 13826221Snate@binkert.org } 13836221Snate@binkert.org } 13842292SN/A 13853867Sbinkertn@umich.edu pri_iter++; 13866221Snate@binkert.org } 13872292SN/A 13882292SN/A return InvalidThreadID; 13892292SN/A} 13902292SN/A 13912292SN/Atemplate<class Impl> 13922292SN/AThreadID 13932292SN/ADefaultCommit<Impl>::oldestReady() 13942292SN/A{ 13952292SN/A unsigned oldest = 0; 13962292SN/A bool first = true; 13972292SN/A 13982292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 13992292SN/A list<ThreadID>::iterator end = activeThreads->end(); 14002292SN/A 14012292SN/A while (threads != end) { 14022292SN/A ThreadID tid = *threads++; 14032292SN/A 14042292SN/A if (!rob->isEmpty(tid) && 14052292SN/A (commitStatus[tid] == Running || 14062292SN/A commitStatus[tid] == Idle || 14072292SN/A commitStatus[tid] == FetchTrapPending)) { 14082292SN/A 14092292SN/A if (rob->isHeadReady(tid)) { 14106221Snate@binkert.org 14112292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 14122292SN/A 1413 if (first) { 1414 oldest = tid; 1415 first = false; 1416 } else if (head_inst->seqNum < oldest) { 1417 oldest = tid; 1418 } 1419 } 1420 } 1421 } 1422 1423 if (!first) { 1424 return oldest; 1425 } else { 1426 return InvalidThreadID; 1427 } 1428} 1429