commit_impl.hh revision 7851
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/cp_annotate.hh" 49#include "base/loader/symtab.hh" 50#include "cpu/timebuf.hh" 51#include "config/full_system.hh" 52#include "config/the_isa.hh" 53#include "config/use_checker.hh" 54#include "cpu/exetrace.hh" 55#include "cpu/o3/commit.hh" 56#include "cpu/o3/thread_state.hh" 57#include "params/DerivO3CPU.hh" 58 59#if USE_CHECKER 60#include "cpu/checker/cpu.hh" 61#endif 62 63using namespace std; 64 65template <class Impl> 66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 67 ThreadID _tid) 68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid) 69{ 70 this->setFlags(AutoDelete); 71} 72 73template <class Impl> 74void 75DefaultCommit<Impl>::TrapEvent::process() 76{ 77 // This will get reset by commit if it was switched out at the 78 // time of this event processing. 79 commit->trapSquash[tid] = true; 80} 81 82template <class Impl> 83const char * 84DefaultCommit<Impl>::TrapEvent::description() const 85{ 86 return "Trap"; 87} 88 89template <class Impl> 90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) 91 : cpu(_cpu), 92 squashCounter(0), 93 iewToCommitDelay(params->iewToCommitDelay), 94 commitToIEWDelay(params->commitToIEWDelay), 95 renameToROBDelay(params->renameToROBDelay), 96 fetchToCommitDelay(params->commitToFetchDelay), 97 renameWidth(params->renameWidth), 98 commitWidth(params->commitWidth), 99 numThreads(params->numThreads), 100 drainPending(false), 101 switchedOut(false), 102 trapLatency(params->trapLatency) 103{ 104 _status = Active; 105 _nextStatus = Inactive; 106 std::string policy = params->smtCommitPolicy; 107 108 //Convert string to lowercase 109 std::transform(policy.begin(), policy.end(), policy.begin(), 110 (int(*)(int)) tolower); 111 112 //Assign commit policy 113 if (policy == "aggressive"){ 114 commitPolicy = Aggressive; 115 116 DPRINTF(Commit,"Commit Policy set to Aggressive."); 117 } else if (policy == "roundrobin"){ 118 commitPolicy = RoundRobin; 119 120 //Set-Up Priority List 121 for (ThreadID tid = 0; tid < numThreads; tid++) { 122 priority_list.push_back(tid); 123 } 124 125 DPRINTF(Commit,"Commit Policy set to Round Robin."); 126 } else if (policy == "oldestready"){ 127 commitPolicy = OldestReady; 128 129 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 130 } else { 131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 132 "RoundRobin,OldestReady}"); 133 } 134 135 for (ThreadID tid = 0; tid < numThreads; tid++) { 136 commitStatus[tid] = Idle; 137 changedROBNumEntries[tid] = false; 138 checkEmptyROB[tid] = false; 139 trapInFlight[tid] = false; 140 committedStores[tid] = false; 141 trapSquash[tid] = false; 142 tcSquash[tid] = false; 143 pc[tid].set(0); 144 } 145#if FULL_SYSTEM 146 interrupt = NoFault; 147#endif 148} 149 150template <class Impl> 151std::string 152DefaultCommit<Impl>::name() const 153{ 154 return cpu->name() + ".commit"; 155} 156 157template <class Impl> 158void 159DefaultCommit<Impl>::regStats() 160{ 161 using namespace Stats; 162 commitCommittedInsts 163 .name(name() + ".commitCommittedInsts") 164 .desc("The number of committed instructions") 165 .prereq(commitCommittedInsts); 166 commitSquashedInsts 167 .name(name() + ".commitSquashedInsts") 168 .desc("The number of squashed insts skipped by commit") 169 .prereq(commitSquashedInsts); 170 commitSquashEvents 171 .name(name() + ".commitSquashEvents") 172 .desc("The number of times commit is told to squash") 173 .prereq(commitSquashEvents); 174 commitNonSpecStalls 175 .name(name() + ".commitNonSpecStalls") 176 .desc("The number of times commit has been forced to stall to " 177 "communicate backwards") 178 .prereq(commitNonSpecStalls); 179 branchMispredicts 180 .name(name() + ".branchMispredicts") 181 .desc("The number of times a branch was mispredicted") 182 .prereq(branchMispredicts); 183 numCommittedDist 184 .init(0,commitWidth,1) 185 .name(name() + ".COM:committed_per_cycle") 186 .desc("Number of insts commited each cycle") 187 .flags(Stats::pdf) 188 ; 189 190 statComInst 191 .init(cpu->numThreads) 192 .name(name() + ".COM:count") 193 .desc("Number of instructions committed") 194 .flags(total) 195 ; 196 197 statComSwp 198 .init(cpu->numThreads) 199 .name(name() + ".COM:swp_count") 200 .desc("Number of s/w prefetches committed") 201 .flags(total) 202 ; 203 204 statComRefs 205 .init(cpu->numThreads) 206 .name(name() + ".COM:refs") 207 .desc("Number of memory references committed") 208 .flags(total) 209 ; 210 211 statComLoads 212 .init(cpu->numThreads) 213 .name(name() + ".COM:loads") 214 .desc("Number of loads committed") 215 .flags(total) 216 ; 217 218 statComMembars 219 .init(cpu->numThreads) 220 .name(name() + ".COM:membars") 221 .desc("Number of memory barriers committed") 222 .flags(total) 223 ; 224 225 statComBranches 226 .init(cpu->numThreads) 227 .name(name() + ".COM:branches") 228 .desc("Number of branches committed") 229 .flags(total) 230 ; 231 232 commitEligible 233 .init(cpu->numThreads) 234 .name(name() + ".COM:bw_limited") 235 .desc("number of insts not committed due to BW limits") 236 .flags(total) 237 ; 238 239 commitEligibleSamples 240 .name(name() + ".COM:bw_lim_events") 241 .desc("number cycles where commit BW limit reached") 242 ; 243} 244 245template <class Impl> 246void 247DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 248{ 249 thread = threads; 250} 251 252template <class Impl> 253void 254DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 255{ 256 timeBuffer = tb_ptr; 257 258 // Setup wire to send information back to IEW. 259 toIEW = timeBuffer->getWire(0); 260 261 // Setup wire to read data from IEW (for the ROB). 262 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 263} 264 265template <class Impl> 266void 267DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 268{ 269 fetchQueue = fq_ptr; 270 271 // Setup wire to get instructions from rename (for the ROB). 272 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 273} 274 275template <class Impl> 276void 277DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 278{ 279 renameQueue = rq_ptr; 280 281 // Setup wire to get instructions from rename (for the ROB). 282 fromRename = renameQueue->getWire(-renameToROBDelay); 283} 284 285template <class Impl> 286void 287DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 288{ 289 iewQueue = iq_ptr; 290 291 // Setup wire to get instructions from IEW. 292 fromIEW = iewQueue->getWire(-iewToCommitDelay); 293} 294 295template <class Impl> 296void 297DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 298{ 299 iewStage = iew_stage; 300} 301 302template<class Impl> 303void 304DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 305{ 306 activeThreads = at_ptr; 307} 308 309template <class Impl> 310void 311DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 312{ 313 for (ThreadID tid = 0; tid < numThreads; tid++) 314 renameMap[tid] = &rm_ptr[tid]; 315} 316 317template <class Impl> 318void 319DefaultCommit<Impl>::setROB(ROB *rob_ptr) 320{ 321 rob = rob_ptr; 322} 323 324template <class Impl> 325void 326DefaultCommit<Impl>::initStage() 327{ 328 rob->setActiveThreads(activeThreads); 329 rob->resetEntries(); 330 331 // Broadcast the number of free entries. 332 for (ThreadID tid = 0; tid < numThreads; tid++) { 333 toIEW->commitInfo[tid].usedROB = true; 334 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 335 toIEW->commitInfo[tid].emptyROB = true; 336 } 337 338 // Commit must broadcast the number of free entries it has at the 339 // start of the simulation, so it starts as active. 340 cpu->activateStage(O3CPU::CommitIdx); 341 342 cpu->activityThisCycle(); 343 trapLatency = cpu->ticks(trapLatency); 344} 345 346template <class Impl> 347bool 348DefaultCommit<Impl>::drain() 349{ 350 drainPending = true; 351 352 return false; 353} 354 355template <class Impl> 356void 357DefaultCommit<Impl>::switchOut() 358{ 359 switchedOut = true; 360 drainPending = false; 361 rob->switchOut(); 362} 363 364template <class Impl> 365void 366DefaultCommit<Impl>::resume() 367{ 368 drainPending = false; 369} 370 371template <class Impl> 372void 373DefaultCommit<Impl>::takeOverFrom() 374{ 375 switchedOut = false; 376 _status = Active; 377 _nextStatus = Inactive; 378 for (ThreadID tid = 0; tid < numThreads; tid++) { 379 commitStatus[tid] = Idle; 380 changedROBNumEntries[tid] = false; 381 trapSquash[tid] = false; 382 tcSquash[tid] = false; 383 } 384 squashCounter = 0; 385 rob->takeOverFrom(); 386} 387 388template <class Impl> 389void 390DefaultCommit<Impl>::updateStatus() 391{ 392 // reset ROB changed variable 393 list<ThreadID>::iterator threads = activeThreads->begin(); 394 list<ThreadID>::iterator end = activeThreads->end(); 395 396 while (threads != end) { 397 ThreadID tid = *threads++; 398 399 changedROBNumEntries[tid] = false; 400 401 // Also check if any of the threads has a trap pending 402 if (commitStatus[tid] == TrapPending || 403 commitStatus[tid] == FetchTrapPending) { 404 _nextStatus = Active; 405 } 406 } 407 408 if (_nextStatus == Inactive && _status == Active) { 409 DPRINTF(Activity, "Deactivating stage.\n"); 410 cpu->deactivateStage(O3CPU::CommitIdx); 411 } else if (_nextStatus == Active && _status == Inactive) { 412 DPRINTF(Activity, "Activating stage.\n"); 413 cpu->activateStage(O3CPU::CommitIdx); 414 } 415 416 _status = _nextStatus; 417} 418 419template <class Impl> 420void 421DefaultCommit<Impl>::setNextStatus() 422{ 423 int squashes = 0; 424 425 list<ThreadID>::iterator threads = activeThreads->begin(); 426 list<ThreadID>::iterator end = activeThreads->end(); 427 428 while (threads != end) { 429 ThreadID tid = *threads++; 430 431 if (commitStatus[tid] == ROBSquashing) { 432 squashes++; 433 } 434 } 435 436 squashCounter = squashes; 437 438 // If commit is currently squashing, then it will have activity for the 439 // next cycle. Set its next status as active. 440 if (squashCounter) { 441 _nextStatus = Active; 442 } 443} 444 445template <class Impl> 446bool 447DefaultCommit<Impl>::changedROBEntries() 448{ 449 list<ThreadID>::iterator threads = activeThreads->begin(); 450 list<ThreadID>::iterator end = activeThreads->end(); 451 452 while (threads != end) { 453 ThreadID tid = *threads++; 454 455 if (changedROBNumEntries[tid]) { 456 return true; 457 } 458 } 459 460 return false; 461} 462 463template <class Impl> 464size_t 465DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid) 466{ 467 return rob->numFreeEntries(tid); 468} 469 470template <class Impl> 471void 472DefaultCommit<Impl>::generateTrapEvent(ThreadID tid) 473{ 474 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 475 476 TrapEvent *trap = new TrapEvent(this, tid); 477 478 cpu->schedule(trap, curTick() + trapLatency); 479 trapInFlight[tid] = true; 480} 481 482template <class Impl> 483void 484DefaultCommit<Impl>::generateTCEvent(ThreadID tid) 485{ 486 assert(!trapInFlight[tid]); 487 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 488 489 tcSquash[tid] = true; 490} 491 492template <class Impl> 493void 494DefaultCommit<Impl>::squashAll(ThreadID tid) 495{ 496 // If we want to include the squashing instruction in the squash, 497 // then use one older sequence number. 498 // Hopefully this doesn't mess things up. Basically I want to squash 499 // all instructions of this thread. 500 InstSeqNum squashed_inst = rob->isEmpty() ? 501 0 : rob->readHeadInst(tid)->seqNum - 1; 502 503 // All younger instructions will be squashed. Set the sequence 504 // number as the youngest instruction in the ROB (0 in this case. 505 // Hopefully nothing breaks.) 506 youngestSeqNum[tid] = 0; 507 508 rob->squash(squashed_inst, tid); 509 changedROBNumEntries[tid] = true; 510 511 // Send back the sequence number of the squashed instruction. 512 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 513 514 // Send back the squash signal to tell stages that they should 515 // squash. 516 toIEW->commitInfo[tid].squash = true; 517 518 // Send back the rob squashing signal so other stages know that 519 // the ROB is in the process of squashing. 520 toIEW->commitInfo[tid].robSquashing = true; 521 522 toIEW->commitInfo[tid].branchMispredict = false; 523 toIEW->commitInfo[tid].mispredictInst = NULL; 524 525 toIEW->commitInfo[tid].pc = pc[tid]; 526} 527 528template <class Impl> 529void 530DefaultCommit<Impl>::squashFromTrap(ThreadID tid) 531{ 532 squashAll(tid); 533 534 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]); 535 536 thread[tid]->trapPending = false; 537 thread[tid]->inSyscall = false; 538 trapInFlight[tid] = false; 539 540 trapSquash[tid] = false; 541 542 commitStatus[tid] = ROBSquashing; 543 cpu->activityThisCycle(); 544} 545 546template <class Impl> 547void 548DefaultCommit<Impl>::squashFromTC(ThreadID tid) 549{ 550 squashAll(tid); 551 552 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]); 553 554 thread[tid]->inSyscall = false; 555 assert(!thread[tid]->trapPending); 556 557 commitStatus[tid] = ROBSquashing; 558 cpu->activityThisCycle(); 559 560 tcSquash[tid] = false; 561} 562 563template <class Impl> 564void 565DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num) 566{ 567 youngestSeqNum[tid] = squash_after_seq_num; 568 569 rob->squash(squash_after_seq_num, tid); 570 changedROBNumEntries[tid] = true; 571 572 // Send back the sequence number of the squashed instruction. 573 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num; 574 575 // Send back the squash signal to tell stages that they should squash. 576 toIEW->commitInfo[tid].squash = true; 577 578 // Send back the rob squashing signal so other stages know that 579 // the ROB is in the process of squashing. 580 toIEW->commitInfo[tid].robSquashing = true; 581 582 toIEW->commitInfo[tid].branchMispredict = false; 583 584 toIEW->commitInfo[tid].pc = pc[tid]; 585 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n", 586 tid, squash_after_seq_num); 587 commitStatus[tid] = ROBSquashing; 588} 589 590template <class Impl> 591void 592DefaultCommit<Impl>::tick() 593{ 594 wroteToTimeBuffer = false; 595 _nextStatus = Inactive; 596 597 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 598 cpu->signalDrained(); 599 drainPending = false; 600 return; 601 } 602 603 if (activeThreads->empty()) 604 return; 605 606 list<ThreadID>::iterator threads = activeThreads->begin(); 607 list<ThreadID>::iterator end = activeThreads->end(); 608 609 // Check if any of the threads are done squashing. Change the 610 // status if they are done. 611 while (threads != end) { 612 ThreadID tid = *threads++; 613 614 // Clear the bit saying if the thread has committed stores 615 // this cycle. 616 committedStores[tid] = false; 617 618 if (commitStatus[tid] == ROBSquashing) { 619 620 if (rob->isDoneSquashing(tid)) { 621 commitStatus[tid] = Running; 622 } else { 623 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 624 " insts this cycle.\n", tid); 625 rob->doSquash(tid); 626 toIEW->commitInfo[tid].robSquashing = true; 627 wroteToTimeBuffer = true; 628 } 629 } 630 } 631 632 commit(); 633 634 markCompletedInsts(); 635 636 threads = activeThreads->begin(); 637 638 while (threads != end) { 639 ThreadID tid = *threads++; 640 641 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 642 // The ROB has more instructions it can commit. Its next status 643 // will be active. 644 _nextStatus = Active; 645 646 DynInstPtr inst = rob->readHeadInst(tid); 647 648 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of" 649 " ROB and ready to commit\n", 650 tid, inst->seqNum, inst->pcState()); 651 652 } else if (!rob->isEmpty(tid)) { 653 DynInstPtr inst = rob->readHeadInst(tid); 654 655 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 656 "%s is head of ROB and not ready\n", 657 tid, inst->seqNum, inst->pcState()); 658 } 659 660 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 661 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 662 } 663 664 665 if (wroteToTimeBuffer) { 666 DPRINTF(Activity, "Activity This Cycle.\n"); 667 cpu->activityThisCycle(); 668 } 669 670 updateStatus(); 671} 672 673#if FULL_SYSTEM 674template <class Impl> 675void 676DefaultCommit<Impl>::handleInterrupt() 677{ 678 // Verify that we still have an interrupt to handle 679 if (!cpu->checkInterrupts(cpu->tcBase(0))) { 680 DPRINTF(Commit, "Pending interrupt is cleared by master before " 681 "it got handled. Restart fetching from the orig path.\n"); 682 toIEW->commitInfo[0].clearInterrupt = true; 683 interrupt = NoFault; 684 return; 685 } 686 687 // Wait until the ROB is empty and all stores have drained in 688 // order to enter the interrupt. 689 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 690 // Squash or record that I need to squash this cycle if 691 // an interrupt needed to be handled. 692 DPRINTF(Commit, "Interrupt detected.\n"); 693 694 // Clear the interrupt now that it's going to be handled 695 toIEW->commitInfo[0].clearInterrupt = true; 696 697 assert(!thread[0]->inSyscall); 698 thread[0]->inSyscall = true; 699 700 // CPU will handle interrupt. 701 cpu->processInterrupts(interrupt); 702 703 thread[0]->inSyscall = false; 704 705 commitStatus[0] = TrapPending; 706 707 // Generate trap squash event. 708 generateTrapEvent(0); 709 710 interrupt = NoFault; 711 } else { 712 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 713 } 714} 715 716template <class Impl> 717void 718DefaultCommit<Impl>::propagateInterrupt() 719{ 720 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] || 721 tcSquash[0]) 722 return; 723 724 // Process interrupts if interrupts are enabled, not in PAL 725 // mode, and no other traps or external squashes are currently 726 // pending. 727 // @todo: Allow other threads to handle interrupts. 728 729 // Get any interrupt that happened 730 interrupt = cpu->getInterrupts(); 731 732 // Tell fetch that there is an interrupt pending. This 733 // will make fetch wait until it sees a non PAL-mode PC, 734 // at which point it stops fetching instructions. 735 if (interrupt != NoFault) 736 toIEW->commitInfo[0].interruptPending = true; 737} 738 739#endif // FULL_SYSTEM 740 741template <class Impl> 742void 743DefaultCommit<Impl>::commit() 744{ 745 746#if FULL_SYSTEM 747 // Check for any interrupt that we've already squashed for and start processing it. 748 if (interrupt != NoFault) 749 handleInterrupt(); 750 751 // Check if we have a interrupt and get read to handle it 752 if (cpu->checkInterrupts(cpu->tcBase(0))) 753 propagateInterrupt(); 754#endif // FULL_SYSTEM 755 756 //////////////////////////////////// 757 // Check for any possible squashes, handle them first 758 //////////////////////////////////// 759 list<ThreadID>::iterator threads = activeThreads->begin(); 760 list<ThreadID>::iterator end = activeThreads->end(); 761 762 while (threads != end) { 763 ThreadID tid = *threads++; 764 765 // Not sure which one takes priority. I think if we have 766 // both, that's a bad sign. 767 if (trapSquash[tid] == true) { 768 assert(!tcSquash[tid]); 769 squashFromTrap(tid); 770 } else if (tcSquash[tid] == true) { 771 assert(commitStatus[tid] != TrapPending); 772 squashFromTC(tid); 773 } 774 775 // Squashed sequence number must be older than youngest valid 776 // instruction in the ROB. This prevents squashes from younger 777 // instructions overriding squashes from older instructions. 778 if (fromIEW->squash[tid] && 779 commitStatus[tid] != TrapPending && 780 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 781 782 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 783 tid, 784 fromIEW->mispredPC[tid], 785 fromIEW->squashedSeqNum[tid]); 786 787 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 788 tid, 789 fromIEW->pc[tid].nextInstAddr()); 790 791 commitStatus[tid] = ROBSquashing; 792 793 // If we want to include the squashing instruction in the squash, 794 // then use one older sequence number. 795 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 796 797 if (fromIEW->includeSquashInst[tid] == true) { 798 squashed_inst--; 799 } 800 801 // All younger instructions will be squashed. Set the sequence 802 // number as the youngest instruction in the ROB. 803 youngestSeqNum[tid] = squashed_inst; 804 805 rob->squash(squashed_inst, tid); 806 changedROBNumEntries[tid] = true; 807 808 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 809 810 toIEW->commitInfo[tid].squash = true; 811 812 // Send back the rob squashing signal so other stages know that 813 // the ROB is in the process of squashing. 814 toIEW->commitInfo[tid].robSquashing = true; 815 816 toIEW->commitInfo[tid].branchMispredict = 817 fromIEW->branchMispredict[tid]; 818 toIEW->commitInfo[tid].mispredictInst = 819 fromIEW->mispredictInst[tid]; 820 toIEW->commitInfo[tid].branchTaken = 821 fromIEW->branchTaken[tid]; 822 823 toIEW->commitInfo[tid].pc = fromIEW->pc[tid]; 824 825 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 826 827 if (toIEW->commitInfo[tid].branchMispredict) { 828 ++branchMispredicts; 829 } 830 } 831 832 } 833 834 setNextStatus(); 835 836 if (squashCounter != numThreads) { 837 // If we're not currently squashing, then get instructions. 838 getInsts(); 839 840 // Try to commit any instructions. 841 commitInsts(); 842 } 843 844 //Check for any activity 845 threads = activeThreads->begin(); 846 847 while (threads != end) { 848 ThreadID tid = *threads++; 849 850 if (changedROBNumEntries[tid]) { 851 toIEW->commitInfo[tid].usedROB = true; 852 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 853 854 wroteToTimeBuffer = true; 855 changedROBNumEntries[tid] = false; 856 if (rob->isEmpty(tid)) 857 checkEmptyROB[tid] = true; 858 } 859 860 // ROB is only considered "empty" for previous stages if: a) 861 // ROB is empty, b) there are no outstanding stores, c) IEW 862 // stage has received any information regarding stores that 863 // committed. 864 // c) is checked by making sure to not consider the ROB empty 865 // on the same cycle as when stores have been committed. 866 // @todo: Make this handle multi-cycle communication between 867 // commit and IEW. 868 if (checkEmptyROB[tid] && rob->isEmpty(tid) && 869 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) { 870 checkEmptyROB[tid] = false; 871 toIEW->commitInfo[tid].usedROB = true; 872 toIEW->commitInfo[tid].emptyROB = true; 873 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 874 wroteToTimeBuffer = true; 875 } 876 877 } 878} 879 880template <class Impl> 881void 882DefaultCommit<Impl>::commitInsts() 883{ 884 //////////////////////////////////// 885 // Handle commit 886 // Note that commit will be handled prior to putting new 887 // instructions in the ROB so that the ROB only tries to commit 888 // instructions it has in this current cycle, and not instructions 889 // it is writing in during this cycle. Can't commit and squash 890 // things at the same time... 891 //////////////////////////////////// 892 893 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 894 895 unsigned num_committed = 0; 896 897 DynInstPtr head_inst; 898 899 // Commit as many instructions as possible until the commit bandwidth 900 // limit is reached, or it becomes impossible to commit any more. 901 while (num_committed < commitWidth) { 902 int commit_thread = getCommittingThread(); 903 904 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 905 break; 906 907 head_inst = rob->readHeadInst(commit_thread); 908 909 ThreadID tid = head_inst->threadNumber; 910 911 assert(tid == commit_thread); 912 913 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 914 head_inst->seqNum, tid); 915 916 // If the head instruction is squashed, it is ready to retire 917 // (be removed from the ROB) at any time. 918 if (head_inst->isSquashed()) { 919 920 DPRINTF(Commit, "Retiring squashed instruction from " 921 "ROB.\n"); 922 923 rob->retireHead(commit_thread); 924 925 ++commitSquashedInsts; 926 927 // Record that the number of ROB entries has changed. 928 changedROBNumEntries[tid] = true; 929 } else { 930 pc[tid] = head_inst->pcState(); 931 932 // Increment the total number of non-speculative instructions 933 // executed. 934 // Hack for now: it really shouldn't happen until after the 935 // commit is deemed to be successful, but this count is needed 936 // for syscalls. 937 thread[tid]->funcExeInst++; 938 939 // Try to commit the head instruction. 940 bool commit_success = commitHead(head_inst, num_committed); 941 942 if (commit_success) { 943 ++num_committed; 944 945 changedROBNumEntries[tid] = true; 946 947 // Set the doneSeqNum to the youngest committed instruction. 948 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 949 950 ++commitCommittedInsts; 951 952 // To match the old model, don't count nops and instruction 953 // prefetches towards the total commit count. 954 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 955 cpu->instDone(tid); 956 } 957 958 // Updates misc. registers. 959 head_inst->updateMiscRegs(); 960 961 TheISA::advancePC(pc[tid], head_inst->staticInst); 962 963 // If this is an instruction that doesn't play nicely with 964 // others squash everything and restart fetch 965 if (head_inst->isSquashAfter()) 966 squashAfter(tid, head_inst->seqNum); 967 968 int count = 0; 969 Addr oldpc; 970 // Debug statement. Checks to make sure we're not 971 // currently updating state while handling PC events. 972 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); 973 do { 974 oldpc = pc[tid].instAddr(); 975 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 976 count++; 977 } while (oldpc != pc[tid].instAddr()); 978 if (count > 1) { 979 DPRINTF(Commit, 980 "PC skip function event, stopping commit\n"); 981 break; 982 } 983 } else { 984 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 985 "[tid:%i] [sn:%i].\n", 986 head_inst->pcState(), tid ,head_inst->seqNum); 987 break; 988 } 989 } 990 } 991 992 DPRINTF(CommitRate, "%i\n", num_committed); 993 numCommittedDist.sample(num_committed); 994 995 if (num_committed == commitWidth) { 996 commitEligibleSamples++; 997 } 998} 999 1000template <class Impl> 1001bool 1002DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 1003{ 1004 assert(head_inst); 1005 1006 ThreadID tid = head_inst->threadNumber; 1007 1008 // If the instruction is not executed yet, then it will need extra 1009 // handling. Signal backwards that it should be executed. 1010 if (!head_inst->isExecuted()) { 1011 // Keep this number correct. We have not yet actually executed 1012 // and committed this instruction. 1013 thread[tid]->funcExeInst--; 1014 1015 if (head_inst->isNonSpeculative() || 1016 head_inst->isStoreConditional() || 1017 head_inst->isMemBarrier() || 1018 head_inst->isWriteBarrier()) { 1019 1020 DPRINTF(Commit, "Encountered a barrier or non-speculative " 1021 "instruction [sn:%lli] at the head of the ROB, PC %s.\n", 1022 head_inst->seqNum, head_inst->pcState()); 1023 1024 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1025 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1026 return false; 1027 } 1028 1029 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1030 1031 // Change the instruction so it won't try to commit again until 1032 // it is executed. 1033 head_inst->clearCanCommit(); 1034 1035 ++commitNonSpecStalls; 1036 1037 return false; 1038 } else if (head_inst->isLoad()) { 1039 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { 1040 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 1041 return false; 1042 } 1043 1044 assert(head_inst->uncacheable()); 1045 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n", 1046 head_inst->seqNum, head_inst->pcState()); 1047 1048 // Send back the non-speculative instruction's sequence 1049 // number. Tell the lsq to re-execute the load. 1050 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1051 toIEW->commitInfo[tid].uncached = true; 1052 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1053 1054 head_inst->clearCanCommit(); 1055 1056 return false; 1057 } else { 1058 panic("Trying to commit un-executed instruction " 1059 "of unknown type!\n"); 1060 } 1061 } 1062 1063 if (head_inst->isThreadSync()) { 1064 // Not handled for now. 1065 panic("Thread sync instructions are not handled yet.\n"); 1066 } 1067 1068 // Check if the instruction caused a fault. If so, trap. 1069 Fault inst_fault = head_inst->getFault(); 1070 1071 // Stores mark themselves as completed. 1072 if (!head_inst->isStore() && inst_fault == NoFault) { 1073 head_inst->setCompleted(); 1074 } 1075 1076#if USE_CHECKER 1077 // Use checker prior to updating anything due to traps or PC 1078 // based events. 1079 if (cpu->checker) { 1080 cpu->checker->verify(head_inst); 1081 } 1082#endif 1083 1084 if (inst_fault != NoFault) { 1085 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1086 head_inst->seqNum, head_inst->pcState()); 1087 1088 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1089 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1090 return false; 1091 } 1092 1093 head_inst->setCompleted(); 1094 1095#if USE_CHECKER 1096 if (cpu->checker && head_inst->isStore()) { 1097 cpu->checker->verify(head_inst); 1098 } 1099#endif 1100 1101 assert(!thread[tid]->inSyscall); 1102 1103 // Mark that we're in state update mode so that the trap's 1104 // execution doesn't generate extra squashes. 1105 thread[tid]->inSyscall = true; 1106 1107 // Execute the trap. Although it's slightly unrealistic in 1108 // terms of timing (as it doesn't wait for the full timing of 1109 // the trap event to complete before updating state), it's 1110 // needed to update the state as soon as possible. This 1111 // prevents external agents from changing any specific state 1112 // that the trap need. 1113 cpu->trap(inst_fault, tid, head_inst->staticInst); 1114 1115 // Exit state update mode to avoid accidental updating. 1116 thread[tid]->inSyscall = false; 1117 1118 commitStatus[tid] = TrapPending; 1119 1120 if (head_inst->traceData) { 1121 if (DTRACE(ExecFaulting)) { 1122 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1123 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1124 head_inst->traceData->dump(); 1125 } 1126 delete head_inst->traceData; 1127 head_inst->traceData = NULL; 1128 } 1129 1130 // Generate trap squash event. 1131 generateTrapEvent(tid); 1132 return false; 1133 } 1134 1135 updateComInstStats(head_inst); 1136 1137#if FULL_SYSTEM 1138 if (thread[tid]->profile) { 1139 thread[tid]->profilePC = head_inst->instAddr(); 1140 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1141 head_inst->staticInst); 1142 1143 if (node) 1144 thread[tid]->profileNode = node; 1145 } 1146 if (CPA::available()) { 1147 if (head_inst->isControl()) { 1148 ThreadContext *tc = thread[tid]->getTC(); 1149 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr()); 1150 } 1151 } 1152#endif 1153 1154 if (head_inst->traceData) { 1155 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1156 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1157 head_inst->traceData->dump(); 1158 delete head_inst->traceData; 1159 head_inst->traceData = NULL; 1160 } 1161 1162 // Update the commit rename map 1163 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1164 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1165 head_inst->renamedDestRegIdx(i)); 1166 } 1167 1168 if (head_inst->isCopy()) 1169 panic("Should not commit any copy instructions!"); 1170 1171 // Finally clear the head ROB entry. 1172 rob->retireHead(tid); 1173 1174 // If this was a store, record it for this cycle. 1175 if (head_inst->isStore()) 1176 committedStores[tid] = true; 1177 1178 // Return true to indicate that we have committed an instruction. 1179 return true; 1180} 1181 1182template <class Impl> 1183void 1184DefaultCommit<Impl>::getInsts() 1185{ 1186 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1187 1188 // Read any renamed instructions and place them into the ROB. 1189 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1190 1191 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1192 DynInstPtr inst; 1193 1194 inst = fromRename->insts[inst_num]; 1195 ThreadID tid = inst->threadNumber; 1196 1197 if (!inst->isSquashed() && 1198 commitStatus[tid] != ROBSquashing && 1199 commitStatus[tid] != TrapPending) { 1200 changedROBNumEntries[tid] = true; 1201 1202 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n", 1203 inst->pcState(), inst->seqNum, tid); 1204 1205 rob->insertInst(inst); 1206 1207 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1208 1209 youngestSeqNum[tid] = inst->seqNum; 1210 } else { 1211 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1212 "squashed, skipping.\n", 1213 inst->pcState(), inst->seqNum, tid); 1214 } 1215 } 1216} 1217 1218template <class Impl> 1219void 1220DefaultCommit<Impl>::skidInsert() 1221{ 1222 DPRINTF(Commit, "Attempting to any instructions from rename into " 1223 "skidBuffer.\n"); 1224 1225 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1226 DynInstPtr inst = fromRename->insts[inst_num]; 1227 1228 if (!inst->isSquashed()) { 1229 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ", 1230 "skidBuffer.\n", inst->pcState(), inst->seqNum, 1231 inst->threadNumber); 1232 skidBuffer.push(inst); 1233 } else { 1234 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was " 1235 "squashed, skipping.\n", 1236 inst->pcState(), inst->seqNum, inst->threadNumber); 1237 } 1238 } 1239} 1240 1241template <class Impl> 1242void 1243DefaultCommit<Impl>::markCompletedInsts() 1244{ 1245 // Grab completed insts out of the IEW instruction queue, and mark 1246 // instructions completed within the ROB. 1247 for (int inst_num = 0; 1248 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1249 ++inst_num) 1250 { 1251 if (!fromIEW->insts[inst_num]->isSquashed()) { 1252 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready " 1253 "within ROB.\n", 1254 fromIEW->insts[inst_num]->threadNumber, 1255 fromIEW->insts[inst_num]->pcState(), 1256 fromIEW->insts[inst_num]->seqNum); 1257 1258 // Mark the instruction as ready to commit. 1259 fromIEW->insts[inst_num]->setCanCommit(); 1260 } 1261 } 1262} 1263 1264template <class Impl> 1265bool 1266DefaultCommit<Impl>::robDoneSquashing() 1267{ 1268 list<ThreadID>::iterator threads = activeThreads->begin(); 1269 list<ThreadID>::iterator end = activeThreads->end(); 1270 1271 while (threads != end) { 1272 ThreadID tid = *threads++; 1273 1274 if (!rob->isDoneSquashing(tid)) 1275 return false; 1276 } 1277 1278 return true; 1279} 1280 1281template <class Impl> 1282void 1283DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1284{ 1285 ThreadID tid = inst->threadNumber; 1286 1287 // 1288 // Pick off the software prefetches 1289 // 1290#ifdef TARGET_ALPHA 1291 if (inst->isDataPrefetch()) { 1292 statComSwp[tid]++; 1293 } else { 1294 statComInst[tid]++; 1295 } 1296#else 1297 statComInst[tid]++; 1298#endif 1299 1300 // 1301 // Control Instructions 1302 // 1303 if (inst->isControl()) 1304 statComBranches[tid]++; 1305 1306 // 1307 // Memory references 1308 // 1309 if (inst->isMemRef()) { 1310 statComRefs[tid]++; 1311 1312 if (inst->isLoad()) { 1313 statComLoads[tid]++; 1314 } 1315 } 1316 1317 if (inst->isMemBarrier()) { 1318 statComMembars[tid]++; 1319 } 1320} 1321 1322//////////////////////////////////////// 1323// // 1324// SMT COMMIT POLICY MAINTAINED HERE // 1325// // 1326//////////////////////////////////////// 1327template <class Impl> 1328ThreadID 1329DefaultCommit<Impl>::getCommittingThread() 1330{ 1331 if (numThreads > 1) { 1332 switch (commitPolicy) { 1333 1334 case Aggressive: 1335 //If Policy is Aggressive, commit will call 1336 //this function multiple times per 1337 //cycle 1338 return oldestReady(); 1339 1340 case RoundRobin: 1341 return roundRobin(); 1342 1343 case OldestReady: 1344 return oldestReady(); 1345 1346 default: 1347 return InvalidThreadID; 1348 } 1349 } else { 1350 assert(!activeThreads->empty()); 1351 ThreadID tid = activeThreads->front(); 1352 1353 if (commitStatus[tid] == Running || 1354 commitStatus[tid] == Idle || 1355 commitStatus[tid] == FetchTrapPending) { 1356 return tid; 1357 } else { 1358 return InvalidThreadID; 1359 } 1360 } 1361} 1362 1363template<class Impl> 1364ThreadID 1365DefaultCommit<Impl>::roundRobin() 1366{ 1367 list<ThreadID>::iterator pri_iter = priority_list.begin(); 1368 list<ThreadID>::iterator end = priority_list.end(); 1369 1370 while (pri_iter != end) { 1371 ThreadID tid = *pri_iter; 1372 1373 if (commitStatus[tid] == Running || 1374 commitStatus[tid] == Idle || 1375 commitStatus[tid] == FetchTrapPending) { 1376 1377 if (rob->isHeadReady(tid)) { 1378 priority_list.erase(pri_iter); 1379 priority_list.push_back(tid); 1380 1381 return tid; 1382 } 1383 } 1384 1385 pri_iter++; 1386 } 1387 1388 return InvalidThreadID; 1389} 1390 1391template<class Impl> 1392ThreadID 1393DefaultCommit<Impl>::oldestReady() 1394{ 1395 unsigned oldest = 0; 1396 bool first = true; 1397 1398 list<ThreadID>::iterator threads = activeThreads->begin(); 1399 list<ThreadID>::iterator end = activeThreads->end(); 1400 1401 while (threads != end) { 1402 ThreadID tid = *threads++; 1403 1404 if (!rob->isEmpty(tid) && 1405 (commitStatus[tid] == Running || 1406 commitStatus[tid] == Idle || 1407 commitStatus[tid] == FetchTrapPending)) { 1408 1409 if (rob->isHeadReady(tid)) { 1410 1411 DynInstPtr head_inst = rob->readHeadInst(tid); 1412 1413 if (first) { 1414 oldest = tid; 1415 first = false; 1416 } else if (head_inst->seqNum < oldest) { 1417 oldest = tid; 1418 } 1419 } 1420 } 1421 } 1422 1423 if (!first) { 1424 return oldest; 1425 } else { 1426 return InvalidThreadID; 1427 } 1428} 1429