commit_impl.hh revision 3771
11689SN/A/* 22316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292965Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322733Sktlim@umich.edu#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352292SN/A#include <algorithm> 362329SN/A#include <string> 372292SN/A 383577Sgblack@eecs.umich.edu#include "arch/utility.hh" 392292SN/A#include "base/loader/symtab.hh" 401060SN/A#include "base/timebuf.hh" 412292SN/A#include "cpu/exetrace.hh" 421717SN/A#include "cpu/o3/commit.hh" 432292SN/A#include "cpu/o3/thread_state.hh" 442292SN/A 452790Sktlim@umich.edu#if USE_CHECKER 462790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 472790Sktlim@umich.edu#endif 482790Sktlim@umich.edu 491061SN/Atemplate <class Impl> 502292SN/ADefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 512292SN/A unsigned _tid) 522292SN/A : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 531060SN/A{ 542292SN/A this->setFlags(Event::AutoDelete); 551060SN/A} 561060SN/A 571061SN/Atemplate <class Impl> 581060SN/Avoid 592292SN/ADefaultCommit<Impl>::TrapEvent::process() 601062SN/A{ 612316SN/A // This will get reset by commit if it was switched out at the 622316SN/A // time of this event processing. 632292SN/A commit->trapSquash[tid] = true; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Aconst char * 682292SN/ADefaultCommit<Impl>::TrapEvent::description() 692292SN/A{ 702292SN/A return "Trap event"; 712292SN/A} 722292SN/A 732292SN/Atemplate <class Impl> 742292SN/ADefaultCommit<Impl>::DefaultCommit(Params *params) 752669Sktlim@umich.edu : squashCounter(0), 762292SN/A iewToCommitDelay(params->iewToCommitDelay), 772292SN/A commitToIEWDelay(params->commitToIEWDelay), 782292SN/A renameToROBDelay(params->renameToROBDelay), 792292SN/A fetchToCommitDelay(params->commitToFetchDelay), 802292SN/A renameWidth(params->renameWidth), 812292SN/A commitWidth(params->commitWidth), 822307SN/A numThreads(params->numberOfThreads), 832843Sktlim@umich.edu drainPending(false), 842316SN/A switchedOut(false), 852874Sktlim@umich.edu trapLatency(params->trapLatency) 862292SN/A{ 872292SN/A _status = Active; 882292SN/A _nextStatus = Inactive; 892980Sgblack@eecs.umich.edu std::string policy = params->smtCommitPolicy; 902292SN/A 912292SN/A //Convert string to lowercase 922292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 932292SN/A (int(*)(int)) tolower); 942292SN/A 952292SN/A //Assign commit policy 962292SN/A if (policy == "aggressive"){ 972292SN/A commitPolicy = Aggressive; 982292SN/A 992292SN/A DPRINTF(Commit,"Commit Policy set to Aggressive."); 1002292SN/A } else if (policy == "roundrobin"){ 1012292SN/A commitPolicy = RoundRobin; 1022292SN/A 1032292SN/A //Set-Up Priority List 1042292SN/A for (int tid=0; tid < numThreads; tid++) { 1052292SN/A priority_list.push_back(tid); 1062292SN/A } 1072292SN/A 1082292SN/A DPRINTF(Commit,"Commit Policy set to Round Robin."); 1092292SN/A } else if (policy == "oldestready"){ 1102292SN/A commitPolicy = OldestReady; 1112292SN/A 1122292SN/A DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 1132292SN/A } else { 1142292SN/A assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 1152292SN/A "RoundRobin,OldestReady}"); 1162292SN/A } 1172292SN/A 1182292SN/A for (int i=0; i < numThreads; i++) { 1192292SN/A commitStatus[i] = Idle; 1202292SN/A changedROBNumEntries[i] = false; 1212292SN/A trapSquash[i] = false; 1222680Sktlim@umich.edu tcSquash[i] = false; 1232935Sksewell@umich.edu PC[i] = nextPC[i] = nextNPC[i] = 0; 1242292SN/A } 1253640Sktlim@umich.edu#if FULL_SYSTEM 1263640Sktlim@umich.edu interrupt = NoFault; 1273640Sktlim@umich.edu#endif 1282292SN/A} 1292292SN/A 1302292SN/Atemplate <class Impl> 1312292SN/Astd::string 1322292SN/ADefaultCommit<Impl>::name() const 1332292SN/A{ 1342292SN/A return cpu->name() + ".commit"; 1352292SN/A} 1362292SN/A 1372292SN/Atemplate <class Impl> 1382292SN/Avoid 1392292SN/ADefaultCommit<Impl>::regStats() 1402132SN/A{ 1412301SN/A using namespace Stats; 1421062SN/A commitCommittedInsts 1431062SN/A .name(name() + ".commitCommittedInsts") 1441062SN/A .desc("The number of committed instructions") 1451062SN/A .prereq(commitCommittedInsts); 1461062SN/A commitSquashedInsts 1471062SN/A .name(name() + ".commitSquashedInsts") 1481062SN/A .desc("The number of squashed insts skipped by commit") 1491062SN/A .prereq(commitSquashedInsts); 1501062SN/A commitSquashEvents 1511062SN/A .name(name() + ".commitSquashEvents") 1521062SN/A .desc("The number of times commit is told to squash") 1531062SN/A .prereq(commitSquashEvents); 1541062SN/A commitNonSpecStalls 1551062SN/A .name(name() + ".commitNonSpecStalls") 1561062SN/A .desc("The number of times commit has been forced to stall to " 1571062SN/A "communicate backwards") 1581062SN/A .prereq(commitNonSpecStalls); 1591062SN/A branchMispredicts 1601062SN/A .name(name() + ".branchMispredicts") 1611062SN/A .desc("The number of times a branch was mispredicted") 1621062SN/A .prereq(branchMispredicts); 1632292SN/A numCommittedDist 1641062SN/A .init(0,commitWidth,1) 1651062SN/A .name(name() + ".COM:committed_per_cycle") 1661062SN/A .desc("Number of insts commited each cycle") 1671062SN/A .flags(Stats::pdf) 1681062SN/A ; 1692301SN/A 1702316SN/A statComInst 1712301SN/A .init(cpu->number_of_threads) 1722301SN/A .name(name() + ".COM:count") 1732301SN/A .desc("Number of instructions committed") 1742301SN/A .flags(total) 1752301SN/A ; 1762301SN/A 1772316SN/A statComSwp 1782301SN/A .init(cpu->number_of_threads) 1792301SN/A .name(name() + ".COM:swp_count") 1802301SN/A .desc("Number of s/w prefetches committed") 1812301SN/A .flags(total) 1822301SN/A ; 1832301SN/A 1842316SN/A statComRefs 1852301SN/A .init(cpu->number_of_threads) 1862301SN/A .name(name() + ".COM:refs") 1872301SN/A .desc("Number of memory references committed") 1882301SN/A .flags(total) 1892301SN/A ; 1902301SN/A 1912316SN/A statComLoads 1922301SN/A .init(cpu->number_of_threads) 1932301SN/A .name(name() + ".COM:loads") 1942301SN/A .desc("Number of loads committed") 1952301SN/A .flags(total) 1962301SN/A ; 1972301SN/A 1982316SN/A statComMembars 1992301SN/A .init(cpu->number_of_threads) 2002301SN/A .name(name() + ".COM:membars") 2012301SN/A .desc("Number of memory barriers committed") 2022301SN/A .flags(total) 2032301SN/A ; 2042301SN/A 2052316SN/A statComBranches 2062301SN/A .init(cpu->number_of_threads) 2072301SN/A .name(name() + ".COM:branches") 2082301SN/A .desc("Number of branches committed") 2092301SN/A .flags(total) 2102301SN/A ; 2112301SN/A 2122316SN/A commitEligible 2132301SN/A .init(cpu->number_of_threads) 2142301SN/A .name(name() + ".COM:bw_limited") 2152301SN/A .desc("number of insts not committed due to BW limits") 2162301SN/A .flags(total) 2172301SN/A ; 2182301SN/A 2192316SN/A commitEligibleSamples 2202301SN/A .name(name() + ".COM:bw_lim_events") 2212301SN/A .desc("number cycles where commit BW limit reached") 2222301SN/A ; 2231062SN/A} 2241062SN/A 2251062SN/Atemplate <class Impl> 2261062SN/Avoid 2272733Sktlim@umich.eduDefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 2281060SN/A{ 2291060SN/A DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 2301060SN/A cpu = cpu_ptr; 2312292SN/A 2322292SN/A // Commit must broadcast the number of free entries it has at the start of 2332292SN/A // the simulation, so it starts as active. 2342733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 2352307SN/A 2362316SN/A trapLatency = cpu->cycles(trapLatency); 2371060SN/A} 2381060SN/A 2391061SN/Atemplate <class Impl> 2401060SN/Avoid 2412980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 2422292SN/A{ 2432292SN/A thread = threads; 2442292SN/A} 2452292SN/A 2462292SN/Atemplate <class Impl> 2472292SN/Avoid 2482292SN/ADefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2491060SN/A{ 2501060SN/A DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 2511060SN/A timeBuffer = tb_ptr; 2521060SN/A 2531060SN/A // Setup wire to send information back to IEW. 2541060SN/A toIEW = timeBuffer->getWire(0); 2551060SN/A 2561060SN/A // Setup wire to read data from IEW (for the ROB). 2571060SN/A robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 2581060SN/A} 2591060SN/A 2601061SN/Atemplate <class Impl> 2611060SN/Avoid 2622292SN/ADefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 2632292SN/A{ 2642292SN/A DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 2652292SN/A fetchQueue = fq_ptr; 2662292SN/A 2672292SN/A // Setup wire to get instructions from rename (for the ROB). 2682292SN/A fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 2692292SN/A} 2702292SN/A 2712292SN/Atemplate <class Impl> 2722292SN/Avoid 2732292SN/ADefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2741060SN/A{ 2751060SN/A DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 2761060SN/A renameQueue = rq_ptr; 2771060SN/A 2781060SN/A // Setup wire to get instructions from rename (for the ROB). 2791060SN/A fromRename = renameQueue->getWire(-renameToROBDelay); 2801060SN/A} 2811060SN/A 2821061SN/Atemplate <class Impl> 2831060SN/Avoid 2842292SN/ADefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 2851060SN/A{ 2861060SN/A DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 2871060SN/A iewQueue = iq_ptr; 2881060SN/A 2891060SN/A // Setup wire to get instructions from IEW. 2901060SN/A fromIEW = iewQueue->getWire(-iewToCommitDelay); 2911060SN/A} 2921060SN/A 2931061SN/Atemplate <class Impl> 2941060SN/Avoid 2952292SN/ADefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 2962292SN/A{ 2972292SN/A iewStage = iew_stage; 2982292SN/A} 2992292SN/A 3002292SN/Atemplate<class Impl> 3012292SN/Avoid 3022980Sgblack@eecs.umich.eduDefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3032292SN/A{ 3042292SN/A DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 3052292SN/A activeThreads = at_ptr; 3062292SN/A} 3072292SN/A 3082292SN/Atemplate <class Impl> 3092292SN/Avoid 3102292SN/ADefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 3112292SN/A{ 3122292SN/A DPRINTF(Commit, "Setting rename map pointers.\n"); 3132292SN/A 3142292SN/A for (int i=0; i < numThreads; i++) { 3152292SN/A renameMap[i] = &rm_ptr[i]; 3162292SN/A } 3172292SN/A} 3182292SN/A 3192292SN/Atemplate <class Impl> 3202292SN/Avoid 3212292SN/ADefaultCommit<Impl>::setROB(ROB *rob_ptr) 3221060SN/A{ 3231060SN/A DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 3241060SN/A rob = rob_ptr; 3251060SN/A} 3261060SN/A 3271061SN/Atemplate <class Impl> 3281060SN/Avoid 3292292SN/ADefaultCommit<Impl>::initStage() 3301060SN/A{ 3312292SN/A rob->setActiveThreads(activeThreads); 3322292SN/A rob->resetEntries(); 3331060SN/A 3342292SN/A // Broadcast the number of free entries. 3352292SN/A for (int i=0; i < numThreads; i++) { 3362292SN/A toIEW->commitInfo[i].usedROB = true; 3372292SN/A toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 3381060SN/A } 3391060SN/A 3402292SN/A cpu->activityThisCycle(); 3411060SN/A} 3421060SN/A 3431061SN/Atemplate <class Impl> 3442863Sktlim@umich.edubool 3452843Sktlim@umich.eduDefaultCommit<Impl>::drain() 3461060SN/A{ 3472843Sktlim@umich.edu drainPending = true; 3482863Sktlim@umich.edu 3492863Sktlim@umich.edu return false; 3502316SN/A} 3512316SN/A 3522316SN/Atemplate <class Impl> 3532316SN/Avoid 3542843Sktlim@umich.eduDefaultCommit<Impl>::switchOut() 3552316SN/A{ 3562316SN/A switchedOut = true; 3572843Sktlim@umich.edu drainPending = false; 3582307SN/A rob->switchOut(); 3592307SN/A} 3602307SN/A 3612307SN/Atemplate <class Impl> 3622307SN/Avoid 3632843Sktlim@umich.eduDefaultCommit<Impl>::resume() 3642843Sktlim@umich.edu{ 3652864Sktlim@umich.edu drainPending = false; 3662843Sktlim@umich.edu} 3672843Sktlim@umich.edu 3682843Sktlim@umich.edutemplate <class Impl> 3692843Sktlim@umich.eduvoid 3702307SN/ADefaultCommit<Impl>::takeOverFrom() 3712307SN/A{ 3722316SN/A switchedOut = false; 3732307SN/A _status = Active; 3742307SN/A _nextStatus = Inactive; 3752307SN/A for (int i=0; i < numThreads; i++) { 3762307SN/A commitStatus[i] = Idle; 3772307SN/A changedROBNumEntries[i] = false; 3782307SN/A trapSquash[i] = false; 3792680Sktlim@umich.edu tcSquash[i] = false; 3802307SN/A } 3812307SN/A squashCounter = 0; 3822307SN/A rob->takeOverFrom(); 3832307SN/A} 3842307SN/A 3852307SN/Atemplate <class Impl> 3862307SN/Avoid 3872292SN/ADefaultCommit<Impl>::updateStatus() 3882132SN/A{ 3892316SN/A // reset ROB changed variable 3902980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 3912316SN/A while (threads != (*activeThreads).end()) { 3922316SN/A unsigned tid = *threads++; 3932316SN/A changedROBNumEntries[tid] = false; 3942316SN/A 3952316SN/A // Also check if any of the threads has a trap pending 3962316SN/A if (commitStatus[tid] == TrapPending || 3972316SN/A commitStatus[tid] == FetchTrapPending) { 3982316SN/A _nextStatus = Active; 3992316SN/A } 4002292SN/A } 4012292SN/A 4022292SN/A if (_nextStatus == Inactive && _status == Active) { 4032292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4042733Sktlim@umich.edu cpu->deactivateStage(O3CPU::CommitIdx); 4052292SN/A } else if (_nextStatus == Active && _status == Inactive) { 4062292SN/A DPRINTF(Activity, "Activating stage.\n"); 4072733Sktlim@umich.edu cpu->activateStage(O3CPU::CommitIdx); 4082292SN/A } 4092292SN/A 4102292SN/A _status = _nextStatus; 4112292SN/A} 4122292SN/A 4132292SN/Atemplate <class Impl> 4142292SN/Avoid 4152292SN/ADefaultCommit<Impl>::setNextStatus() 4162292SN/A{ 4172292SN/A int squashes = 0; 4182292SN/A 4192980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4202292SN/A 4212292SN/A while (threads != (*activeThreads).end()) { 4222292SN/A unsigned tid = *threads++; 4232292SN/A 4242292SN/A if (commitStatus[tid] == ROBSquashing) { 4252292SN/A squashes++; 4262292SN/A } 4272292SN/A } 4282292SN/A 4292702Sktlim@umich.edu squashCounter = squashes; 4302292SN/A 4312292SN/A // If commit is currently squashing, then it will have activity for the 4322292SN/A // next cycle. Set its next status as active. 4332292SN/A if (squashCounter) { 4342292SN/A _nextStatus = Active; 4352292SN/A } 4362292SN/A} 4372292SN/A 4382292SN/Atemplate <class Impl> 4392292SN/Abool 4402292SN/ADefaultCommit<Impl>::changedROBEntries() 4412292SN/A{ 4422980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4432292SN/A 4442292SN/A while (threads != (*activeThreads).end()) { 4452292SN/A unsigned tid = *threads++; 4462292SN/A 4472292SN/A if (changedROBNumEntries[tid]) { 4482292SN/A return true; 4492292SN/A } 4502292SN/A } 4512292SN/A 4522292SN/A return false; 4532292SN/A} 4542292SN/A 4552292SN/Atemplate <class Impl> 4562292SN/Aunsigned 4572292SN/ADefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 4582292SN/A{ 4592292SN/A return rob->numFreeEntries(tid); 4602292SN/A} 4612292SN/A 4622292SN/Atemplate <class Impl> 4632292SN/Avoid 4642292SN/ADefaultCommit<Impl>::generateTrapEvent(unsigned tid) 4652292SN/A{ 4662292SN/A DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 4672292SN/A 4682292SN/A TrapEvent *trap = new TrapEvent(this, tid); 4692292SN/A 4702292SN/A trap->schedule(curTick + trapLatency); 4712292SN/A 4722292SN/A thread[tid]->trapPending = true; 4732292SN/A} 4742292SN/A 4752292SN/Atemplate <class Impl> 4762292SN/Avoid 4772680Sktlim@umich.eduDefaultCommit<Impl>::generateTCEvent(unsigned tid) 4782292SN/A{ 4792680Sktlim@umich.edu DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 4802292SN/A 4812680Sktlim@umich.edu tcSquash[tid] = true; 4822292SN/A} 4832292SN/A 4842292SN/Atemplate <class Impl> 4852292SN/Avoid 4862316SN/ADefaultCommit<Impl>::squashAll(unsigned tid) 4872292SN/A{ 4882292SN/A // If we want to include the squashing instruction in the squash, 4892292SN/A // then use one older sequence number. 4902292SN/A // Hopefully this doesn't mess things up. Basically I want to squash 4912292SN/A // all instructions of this thread. 4922292SN/A InstSeqNum squashed_inst = rob->isEmpty() ? 4932292SN/A 0 : rob->readHeadInst(tid)->seqNum - 1;; 4942292SN/A 4952292SN/A // All younger instructions will be squashed. Set the sequence 4962292SN/A // number as the youngest instruction in the ROB (0 in this case. 4972292SN/A // Hopefully nothing breaks.) 4982292SN/A youngestSeqNum[tid] = 0; 4992292SN/A 5002292SN/A rob->squash(squashed_inst, tid); 5012292SN/A changedROBNumEntries[tid] = true; 5022292SN/A 5032292SN/A // Send back the sequence number of the squashed instruction. 5042292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 5052292SN/A 5062292SN/A // Send back the squash signal to tell stages that they should 5072292SN/A // squash. 5082292SN/A toIEW->commitInfo[tid].squash = true; 5092292SN/A 5102292SN/A // Send back the rob squashing signal so other stages know that 5112292SN/A // the ROB is in the process of squashing. 5122292SN/A toIEW->commitInfo[tid].robSquashing = true; 5132292SN/A 5142292SN/A toIEW->commitInfo[tid].branchMispredict = false; 5152292SN/A 5162316SN/A toIEW->commitInfo[tid].nextPC = PC[tid]; 5172316SN/A} 5182292SN/A 5192316SN/Atemplate <class Impl> 5202316SN/Avoid 5212316SN/ADefaultCommit<Impl>::squashFromTrap(unsigned tid) 5222316SN/A{ 5232316SN/A squashAll(tid); 5242316SN/A 5252316SN/A DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 5262316SN/A 5272316SN/A thread[tid]->trapPending = false; 5282316SN/A thread[tid]->inSyscall = false; 5292316SN/A 5302316SN/A trapSquash[tid] = false; 5312316SN/A 5322316SN/A commitStatus[tid] = ROBSquashing; 5332316SN/A cpu->activityThisCycle(); 5342316SN/A} 5352316SN/A 5362316SN/Atemplate <class Impl> 5372316SN/Avoid 5382680Sktlim@umich.eduDefaultCommit<Impl>::squashFromTC(unsigned tid) 5392316SN/A{ 5402316SN/A squashAll(tid); 5412292SN/A 5422680Sktlim@umich.edu DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 5432292SN/A 5442292SN/A thread[tid]->inSyscall = false; 5452292SN/A assert(!thread[tid]->trapPending); 5462316SN/A 5472292SN/A commitStatus[tid] = ROBSquashing; 5482292SN/A cpu->activityThisCycle(); 5492292SN/A 5502680Sktlim@umich.edu tcSquash[tid] = false; 5512292SN/A} 5522292SN/A 5532292SN/Atemplate <class Impl> 5542292SN/Avoid 5552292SN/ADefaultCommit<Impl>::tick() 5562292SN/A{ 5572292SN/A wroteToTimeBuffer = false; 5582292SN/A _nextStatus = Inactive; 5592292SN/A 5602843Sktlim@umich.edu if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 5612843Sktlim@umich.edu cpu->signalDrained(); 5622843Sktlim@umich.edu drainPending = false; 5632316SN/A return; 5642316SN/A } 5652316SN/A 5662875Sksewell@umich.edu if ((*activeThreads).size() <= 0) 5672875Sksewell@umich.edu return; 5682875Sksewell@umich.edu 5692980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 5702292SN/A 5712316SN/A // Check if any of the threads are done squashing. Change the 5722316SN/A // status if they are done. 5732292SN/A while (threads != (*activeThreads).end()) { 5742292SN/A unsigned tid = *threads++; 5752292SN/A 5762292SN/A if (commitStatus[tid] == ROBSquashing) { 5772292SN/A 5782292SN/A if (rob->isDoneSquashing(tid)) { 5792292SN/A commitStatus[tid] = Running; 5802292SN/A } else { 5812292SN/A DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 5822877Sksewell@umich.edu " insts this cycle.\n", tid); 5832702Sktlim@umich.edu rob->doSquash(tid); 5842702Sktlim@umich.edu toIEW->commitInfo[tid].robSquashing = true; 5852702Sktlim@umich.edu wroteToTimeBuffer = true; 5862292SN/A } 5872292SN/A } 5882292SN/A } 5892292SN/A 5902292SN/A commit(); 5912292SN/A 5922292SN/A markCompletedInsts(); 5932292SN/A 5942292SN/A threads = (*activeThreads).begin(); 5952292SN/A 5962292SN/A while (threads != (*activeThreads).end()) { 5972292SN/A unsigned tid = *threads++; 5982292SN/A 5992292SN/A if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 6002292SN/A // The ROB has more instructions it can commit. Its next status 6012292SN/A // will be active. 6022292SN/A _nextStatus = Active; 6032292SN/A 6042292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6052292SN/A 6062292SN/A DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 6072292SN/A " ROB and ready to commit\n", 6082292SN/A tid, inst->seqNum, inst->readPC()); 6092292SN/A 6102292SN/A } else if (!rob->isEmpty(tid)) { 6112292SN/A DynInstPtr inst = rob->readHeadInst(tid); 6122292SN/A 6132292SN/A DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 6142292SN/A "%#x is head of ROB and not ready\n", 6152292SN/A tid, inst->seqNum, inst->readPC()); 6162292SN/A } 6172292SN/A 6182292SN/A DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 6192292SN/A tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 6202292SN/A } 6212292SN/A 6222292SN/A 6232292SN/A if (wroteToTimeBuffer) { 6242316SN/A DPRINTF(Activity, "Activity This Cycle.\n"); 6252292SN/A cpu->activityThisCycle(); 6262292SN/A } 6272292SN/A 6282292SN/A updateStatus(); 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Avoid 6332292SN/ADefaultCommit<Impl>::commit() 6342292SN/A{ 6352292SN/A 6361060SN/A ////////////////////////////////////// 6371060SN/A // Check for interrupts 6381060SN/A ////////////////////////////////////// 6391060SN/A 6401858SN/A#if FULL_SYSTEM 6413640Sktlim@umich.edu if (interrupt != NoFault) { 6422316SN/A // Wait until the ROB is empty and all stores have drained in 6432316SN/A // order to enter the interrupt. 6442292SN/A if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 6453633Sktlim@umich.edu // Squash or record that I need to squash this cycle if 6463633Sktlim@umich.edu // an interrupt needed to be handled. 6473633Sktlim@umich.edu DPRINTF(Commit, "Interrupt detected.\n"); 6483633Sktlim@umich.edu 6492292SN/A assert(!thread[0]->inSyscall); 6502292SN/A thread[0]->inSyscall = true; 6512292SN/A 6523633Sktlim@umich.edu // CPU will handle interrupt. 6533640Sktlim@umich.edu cpu->processInterrupts(interrupt); 6542292SN/A 6553633Sktlim@umich.edu thread[0]->inSyscall = false; 6563633Sktlim@umich.edu 6572292SN/A commitStatus[0] = TrapPending; 6582292SN/A 6592292SN/A // Generate trap squash event. 6602292SN/A generateTrapEvent(0); 6612292SN/A 6623640Sktlim@umich.edu // Clear the interrupt now that it's been handled 6632292SN/A toIEW->commitInfo[0].clearInterrupt = true; 6643640Sktlim@umich.edu interrupt = NoFault; 6652292SN/A } else { 6662292SN/A DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 6672292SN/A } 6683640Sktlim@umich.edu } else if (cpu->checkInterrupts && 6693640Sktlim@umich.edu cpu->check_interrupts(cpu->tcBase(0)) && 6703640Sktlim@umich.edu commitStatus[0] != TrapPending && 6713640Sktlim@umich.edu !trapSquash[0] && 6723640Sktlim@umich.edu !tcSquash[0]) { 6733640Sktlim@umich.edu // Process interrupts if interrupts are enabled, not in PAL 6743640Sktlim@umich.edu // mode, and no other traps or external squashes are currently 6753640Sktlim@umich.edu // pending. 6763640Sktlim@umich.edu // @todo: Allow other threads to handle interrupts. 6773640Sktlim@umich.edu 6783640Sktlim@umich.edu // Get any interrupt that happened 6793640Sktlim@umich.edu interrupt = cpu->getInterrupts(); 6803640Sktlim@umich.edu 6813640Sktlim@umich.edu if (interrupt != NoFault) { 6823640Sktlim@umich.edu // Tell fetch that there is an interrupt pending. This 6833640Sktlim@umich.edu // will make fetch wait until it sees a non PAL-mode PC, 6843640Sktlim@umich.edu // at which point it stops fetching instructions. 6853640Sktlim@umich.edu toIEW->commitInfo[0].interruptPending = true; 6863640Sktlim@umich.edu } 6871060SN/A } 6883634Sktlim@umich.edu 6891060SN/A#endif // FULL_SYSTEM 6901060SN/A 6911060SN/A //////////////////////////////////// 6922316SN/A // Check for any possible squashes, handle them first 6931060SN/A //////////////////////////////////// 6942980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 6951060SN/A 6962292SN/A while (threads != (*activeThreads).end()) { 6972292SN/A unsigned tid = *threads++; 6981060SN/A 6992292SN/A // Not sure which one takes priority. I think if we have 7002292SN/A // both, that's a bad sign. 7012292SN/A if (trapSquash[tid] == true) { 7022680Sktlim@umich.edu assert(!tcSquash[tid]); 7032292SN/A squashFromTrap(tid); 7042680Sktlim@umich.edu } else if (tcSquash[tid] == true) { 7052680Sktlim@umich.edu squashFromTC(tid); 7062292SN/A } 7071061SN/A 7082292SN/A // Squashed sequence number must be older than youngest valid 7092292SN/A // instruction in the ROB. This prevents squashes from younger 7102292SN/A // instructions overriding squashes from older instructions. 7112292SN/A if (fromIEW->squash[tid] && 7122292SN/A commitStatus[tid] != TrapPending && 7132292SN/A fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 7141061SN/A 7152292SN/A DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 7162292SN/A tid, 7172292SN/A fromIEW->mispredPC[tid], 7182292SN/A fromIEW->squashedSeqNum[tid]); 7191061SN/A 7202292SN/A DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 7212292SN/A tid, 7222292SN/A fromIEW->nextPC[tid]); 7231061SN/A 7242292SN/A commitStatus[tid] = ROBSquashing; 7251061SN/A 7262292SN/A // If we want to include the squashing instruction in the squash, 7272292SN/A // then use one older sequence number. 7282292SN/A InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 7291062SN/A 7303093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7313771Sgblack@eecs.umich.edu InstSeqNum bdelay_done_seq_num = squashed_inst; 7323771Sgblack@eecs.umich.edu bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 7332935Sksewell@umich.edu 7343771Sgblack@eecs.umich.edu if (!squash_bdelay_slot) 7353771Sgblack@eecs.umich.edu bdelay_done_seq_num++; 7363771Sgblack@eecs.umich.edu 7372935Sksewell@umich.edu#endif 7382935Sksewell@umich.edu 7392935Sksewell@umich.edu if (fromIEW->includeSquashInst[tid] == true) { 7402292SN/A squashed_inst--; 7413093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7422935Sksewell@umich.edu bdelay_done_seq_num--; 7432935Sksewell@umich.edu#endif 7442935Sksewell@umich.edu } 7452292SN/A // All younger instructions will be squashed. Set the sequence 7462292SN/A // number as the youngest instruction in the ROB. 7472292SN/A youngestSeqNum[tid] = squashed_inst; 7482292SN/A 7493093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7502935Sksewell@umich.edu rob->squash(bdelay_done_seq_num, tid); 7512935Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 7522935Sksewell@umich.edu toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 7533093Sksewell@umich.edu#else 7543093Sksewell@umich.edu rob->squash(squashed_inst, tid); 7553093Sksewell@umich.edu toIEW->commitInfo[tid].squashDelaySlot = true; 7562935Sksewell@umich.edu#endif 7572292SN/A changedROBNumEntries[tid] = true; 7582292SN/A 7592292SN/A toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 7602292SN/A 7612292SN/A toIEW->commitInfo[tid].squash = true; 7622292SN/A 7632292SN/A // Send back the rob squashing signal so other stages know that 7642292SN/A // the ROB is in the process of squashing. 7652292SN/A toIEW->commitInfo[tid].robSquashing = true; 7662292SN/A 7672292SN/A toIEW->commitInfo[tid].branchMispredict = 7682292SN/A fromIEW->branchMispredict[tid]; 7692292SN/A 7702292SN/A toIEW->commitInfo[tid].branchTaken = 7712292SN/A fromIEW->branchTaken[tid]; 7722292SN/A 7732292SN/A toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 7742292SN/A 7752316SN/A toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 7762292SN/A 7772292SN/A if (toIEW->commitInfo[tid].branchMispredict) { 7782292SN/A ++branchMispredicts; 7792292SN/A } 7801062SN/A } 7812292SN/A 7821060SN/A } 7831060SN/A 7842292SN/A setNextStatus(); 7852292SN/A 7862292SN/A if (squashCounter != numThreads) { 7871061SN/A // If we're not currently squashing, then get instructions. 7881060SN/A getInsts(); 7891060SN/A 7901061SN/A // Try to commit any instructions. 7911060SN/A commitInsts(); 7922965Sksewell@umich.edu } else { 7933093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7942965Sksewell@umich.edu skidInsert(); 7952965Sksewell@umich.edu#endif 7961060SN/A } 7971060SN/A 7982292SN/A //Check for any activity 7992292SN/A threads = (*activeThreads).begin(); 8002292SN/A 8012292SN/A while (threads != (*activeThreads).end()) { 8022292SN/A unsigned tid = *threads++; 8032292SN/A 8042292SN/A if (changedROBNumEntries[tid]) { 8052292SN/A toIEW->commitInfo[tid].usedROB = true; 8062292SN/A toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 8072292SN/A 8082292SN/A if (rob->isEmpty(tid)) { 8092292SN/A toIEW->commitInfo[tid].emptyROB = true; 8102292SN/A } 8112292SN/A 8122292SN/A wroteToTimeBuffer = true; 8132292SN/A changedROBNumEntries[tid] = false; 8142292SN/A } 8151060SN/A } 8161060SN/A} 8171060SN/A 8181061SN/Atemplate <class Impl> 8191060SN/Avoid 8202292SN/ADefaultCommit<Impl>::commitInsts() 8211060SN/A{ 8221060SN/A //////////////////////////////////// 8231060SN/A // Handle commit 8242316SN/A // Note that commit will be handled prior to putting new 8252316SN/A // instructions in the ROB so that the ROB only tries to commit 8262316SN/A // instructions it has in this current cycle, and not instructions 8272316SN/A // it is writing in during this cycle. Can't commit and squash 8282316SN/A // things at the same time... 8291060SN/A //////////////////////////////////// 8301060SN/A 8312292SN/A DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 8321060SN/A 8331060SN/A unsigned num_committed = 0; 8341060SN/A 8352292SN/A DynInstPtr head_inst; 8362316SN/A 8371060SN/A // Commit as many instructions as possible until the commit bandwidth 8381060SN/A // limit is reached, or it becomes impossible to commit any more. 8392292SN/A while (num_committed < commitWidth) { 8402292SN/A int commit_thread = getCommittingThread(); 8411060SN/A 8422292SN/A if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 8432292SN/A break; 8442292SN/A 8452292SN/A head_inst = rob->readHeadInst(commit_thread); 8462292SN/A 8472292SN/A int tid = head_inst->threadNumber; 8482292SN/A 8492292SN/A assert(tid == commit_thread); 8502292SN/A 8512292SN/A DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 8522292SN/A head_inst->seqNum, tid); 8532132SN/A 8542316SN/A // If the head instruction is squashed, it is ready to retire 8552316SN/A // (be removed from the ROB) at any time. 8561060SN/A if (head_inst->isSquashed()) { 8571060SN/A 8582292SN/A DPRINTF(Commit, "Retiring squashed instruction from " 8591060SN/A "ROB.\n"); 8601060SN/A 8612292SN/A rob->retireHead(commit_thread); 8621060SN/A 8631062SN/A ++commitSquashedInsts; 8641062SN/A 8652292SN/A // Record that the number of ROB entries has changed. 8662292SN/A changedROBNumEntries[tid] = true; 8671060SN/A } else { 8682292SN/A PC[tid] = head_inst->readPC(); 8692292SN/A nextPC[tid] = head_inst->readNextPC(); 8702935Sksewell@umich.edu nextNPC[tid] = head_inst->readNextNPC(); 8712292SN/A 8721060SN/A // Increment the total number of non-speculative instructions 8731060SN/A // executed. 8741060SN/A // Hack for now: it really shouldn't happen until after the 8751061SN/A // commit is deemed to be successful, but this count is needed 8761061SN/A // for syscalls. 8772292SN/A thread[tid]->funcExeInst++; 8781060SN/A 8791060SN/A // Try to commit the head instruction. 8801060SN/A bool commit_success = commitHead(head_inst, num_committed); 8811060SN/A 8821062SN/A if (commit_success) { 8831060SN/A ++num_committed; 8841060SN/A 8852292SN/A changedROBNumEntries[tid] = true; 8862292SN/A 8872292SN/A // Set the doneSeqNum to the youngest committed instruction. 8882292SN/A toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 8891060SN/A 8901062SN/A ++commitCommittedInsts; 8911062SN/A 8922292SN/A // To match the old model, don't count nops and instruction 8932292SN/A // prefetches towards the total commit count. 8942292SN/A if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 8952292SN/A cpu->instDone(tid); 8961062SN/A } 8972292SN/A 8982292SN/A PC[tid] = nextPC[tid]; 8993093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9002935Sksewell@umich.edu nextPC[tid] = nextNPC[tid]; 9012935Sksewell@umich.edu nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 9023093Sksewell@umich.edu#else 9033093Sksewell@umich.edu nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 9042935Sksewell@umich.edu#endif 9052935Sksewell@umich.edu 9062292SN/A#if FULL_SYSTEM 9072292SN/A int count = 0; 9082292SN/A Addr oldpc; 9092292SN/A do { 9102316SN/A // Debug statement. Checks to make sure we're not 9112316SN/A // currently updating state while handling PC events. 9122292SN/A if (count == 0) 9132316SN/A assert(!thread[tid]->inSyscall && 9142316SN/A !thread[tid]->trapPending); 9152292SN/A oldpc = PC[tid]; 9162292SN/A cpu->system->pcEventQueue.service( 9172690Sktlim@umich.edu thread[tid]->getTC()); 9182292SN/A count++; 9192292SN/A } while (oldpc != PC[tid]); 9202292SN/A if (count > 1) { 9212292SN/A DPRINTF(Commit, "PC skip function event, stopping commit\n"); 9222292SN/A break; 9232292SN/A } 9242292SN/A#endif 9251060SN/A } else { 9262292SN/A DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 9272292SN/A "[tid:%i] [sn:%i].\n", 9282292SN/A head_inst->readPC(), tid ,head_inst->seqNum); 9291060SN/A break; 9301060SN/A } 9311060SN/A } 9321060SN/A } 9331062SN/A 9341063SN/A DPRINTF(CommitRate, "%i\n", num_committed); 9352292SN/A numCommittedDist.sample(num_committed); 9362307SN/A 9372307SN/A if (num_committed == commitWidth) { 9382349SN/A commitEligibleSamples++; 9392307SN/A } 9401060SN/A} 9411060SN/A 9421061SN/Atemplate <class Impl> 9431060SN/Abool 9442292SN/ADefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 9451060SN/A{ 9461060SN/A assert(head_inst); 9471060SN/A 9482292SN/A int tid = head_inst->threadNumber; 9492292SN/A 9502316SN/A // If the instruction is not executed yet, then it will need extra 9512316SN/A // handling. Signal backwards that it should be executed. 9521061SN/A if (!head_inst->isExecuted()) { 9531061SN/A // Keep this number correct. We have not yet actually executed 9541061SN/A // and committed this instruction. 9552292SN/A thread[tid]->funcExeInst--; 9561062SN/A 9572731Sktlim@umich.edu head_inst->setAtCommit(); 9581060SN/A 9592292SN/A if (head_inst->isNonSpeculative() || 9602348SN/A head_inst->isStoreConditional() || 9612292SN/A head_inst->isMemBarrier() || 9622292SN/A head_inst->isWriteBarrier()) { 9632316SN/A 9642316SN/A DPRINTF(Commit, "Encountered a barrier or non-speculative " 9652316SN/A "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 9662316SN/A head_inst->seqNum, head_inst->readPC()); 9672316SN/A 9682292SN/A#if !FULL_SYSTEM 9692316SN/A // Hack to make sure syscalls/memory barriers/quiesces 9702316SN/A // aren't executed until all stores write back their data. 9712316SN/A // This direct communication shouldn't be used for 9722316SN/A // anything other than this. 9732292SN/A if (inst_num > 0 || iewStage->hasStoresToWB()) 9742292SN/A#else 9752292SN/A if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 9762292SN/A head_inst->isQuiesce()) && 9772292SN/A iewStage->hasStoresToWB()) 9782292SN/A#endif 9792292SN/A { 9802292SN/A DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 9812292SN/A return false; 9822292SN/A } 9832292SN/A 9842292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 9851061SN/A 9861061SN/A // Change the instruction so it won't try to commit again until 9871061SN/A // it is executed. 9881061SN/A head_inst->clearCanCommit(); 9891061SN/A 9901062SN/A ++commitNonSpecStalls; 9911062SN/A 9921061SN/A return false; 9932292SN/A } else if (head_inst->isLoad()) { 9942292SN/A DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 9952292SN/A head_inst->seqNum, head_inst->readPC()); 9962292SN/A 9972292SN/A // Send back the non-speculative instruction's sequence 9982316SN/A // number. Tell the lsq to re-execute the load. 9992292SN/A toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 10002292SN/A toIEW->commitInfo[tid].uncached = true; 10012292SN/A toIEW->commitInfo[tid].uncachedLoad = head_inst; 10022292SN/A 10032292SN/A head_inst->clearCanCommit(); 10042292SN/A 10052292SN/A return false; 10061061SN/A } else { 10072292SN/A panic("Trying to commit un-executed instruction " 10081061SN/A "of unknown type!\n"); 10091061SN/A } 10101060SN/A } 10111060SN/A 10122316SN/A if (head_inst->isThreadSync()) { 10132292SN/A // Not handled for now. 10142316SN/A panic("Thread sync instructions are not handled yet.\n"); 10152132SN/A } 10162132SN/A 10172316SN/A // Stores mark themselves as completed. 10182310SN/A if (!head_inst->isStore()) { 10192310SN/A head_inst->setCompleted(); 10202310SN/A } 10212310SN/A 10222733Sktlim@umich.edu#if USE_CHECKER 10232316SN/A // Use checker prior to updating anything due to traps or PC 10242316SN/A // based events. 10252316SN/A if (cpu->checker) { 10262732Sktlim@umich.edu cpu->checker->verify(head_inst); 10271060SN/A } 10282733Sktlim@umich.edu#endif 10291060SN/A 10301060SN/A // Check if the instruction caused a fault. If so, trap. 10312132SN/A Fault inst_fault = head_inst->getFault(); 10321681SN/A 10332918Sktlim@umich.edu // DTB will sometimes need the machine instruction for when 10342918Sktlim@umich.edu // faults happen. So we will set it here, prior to the DTB 10352918Sktlim@umich.edu // possibly needing it for its fault. 10362918Sktlim@umich.edu thread[tid]->setInst( 10372918Sktlim@umich.edu static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 10382918Sktlim@umich.edu 10392112SN/A if (inst_fault != NoFault) { 10402316SN/A head_inst->setCompleted(); 10412316SN/A DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 10422316SN/A head_inst->seqNum, head_inst->readPC()); 10432292SN/A 10442316SN/A if (iewStage->hasStoresToWB() || inst_num > 0) { 10452316SN/A DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 10462316SN/A return false; 10472316SN/A } 10482310SN/A 10492733Sktlim@umich.edu#if USE_CHECKER 10502316SN/A if (cpu->checker && head_inst->isStore()) { 10512732Sktlim@umich.edu cpu->checker->verify(head_inst); 10522316SN/A } 10532733Sktlim@umich.edu#endif 10542292SN/A 10552316SN/A assert(!thread[tid]->inSyscall); 10562292SN/A 10572316SN/A // Mark that we're in state update mode so that the trap's 10582316SN/A // execution doesn't generate extra squashes. 10592316SN/A thread[tid]->inSyscall = true; 10602292SN/A 10612316SN/A // Execute the trap. Although it's slightly unrealistic in 10622316SN/A // terms of timing (as it doesn't wait for the full timing of 10632316SN/A // the trap event to complete before updating state), it's 10642316SN/A // needed to update the state as soon as possible. This 10652316SN/A // prevents external agents from changing any specific state 10662316SN/A // that the trap need. 10672316SN/A cpu->trap(inst_fault, tid); 10682292SN/A 10692316SN/A // Exit state update mode to avoid accidental updating. 10702316SN/A thread[tid]->inSyscall = false; 10712292SN/A 10722316SN/A commitStatus[tid] = TrapPending; 10732292SN/A 10742316SN/A // Generate trap squash event. 10752316SN/A generateTrapEvent(tid); 10762353SN/A// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 10772316SN/A return false; 10781060SN/A } 10791060SN/A 10802301SN/A updateComInstStats(head_inst); 10812132SN/A 10822362SN/A#if FULL_SYSTEM 10832362SN/A if (thread[tid]->profile) { 10843577Sgblack@eecs.umich.edu// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 10852362SN/A// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 10862362SN/A thread[tid]->profilePC = head_inst->readPC(); 10873126Sktlim@umich.edu ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 10882362SN/A head_inst->staticInst); 10892362SN/A 10902362SN/A if (node) 10912362SN/A thread[tid]->profileNode = node; 10922362SN/A } 10932362SN/A#endif 10942362SN/A 10952132SN/A if (head_inst->traceData) { 10962292SN/A head_inst->traceData->setFetchSeq(head_inst->seqNum); 10972292SN/A head_inst->traceData->setCPSeq(thread[tid]->numInst); 10982132SN/A head_inst->traceData->finalize(); 10992292SN/A head_inst->traceData = NULL; 11001060SN/A } 11011060SN/A 11022292SN/A // Update the commit rename map 11032292SN/A for (int i = 0; i < head_inst->numDestRegs(); i++) { 11043771Sgblack@eecs.umich.edu renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 11052292SN/A head_inst->renamedDestRegIdx(i)); 11061060SN/A } 11071062SN/A 11082353SN/A if (head_inst->isCopy()) 11092353SN/A panic("Should not commit any copy instructions!"); 11102353SN/A 11112292SN/A // Finally clear the head ROB entry. 11122292SN/A rob->retireHead(tid); 11131060SN/A 11141060SN/A // Return true to indicate that we have committed an instruction. 11151060SN/A return true; 11161060SN/A} 11171060SN/A 11181061SN/Atemplate <class Impl> 11191060SN/Avoid 11202292SN/ADefaultCommit<Impl>::getInsts() 11211060SN/A{ 11222935Sksewell@umich.edu DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 11232935Sksewell@umich.edu 11243093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11252965Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11262980Sgblack@eecs.umich.edu int insts_to_process = std::min((int)renameWidth, 11272965Sksewell@umich.edu (int)(fromRename->size + skidBuffer.size())); 11282965Sksewell@umich.edu int rename_idx = 0; 11291061SN/A 11302965Sksewell@umich.edu DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 11312965Sksewell@umich.edu "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 11322965Sksewell@umich.edu skidBuffer.size()); 11333093Sksewell@umich.edu#else 11343093Sksewell@umich.edu // Read any renamed instructions and place them into the ROB. 11353093Sksewell@umich.edu int insts_to_process = std::min((int)renameWidth, fromRename->size); 11362965Sksewell@umich.edu#endif 11372965Sksewell@umich.edu 11382965Sksewell@umich.edu 11392965Sksewell@umich.edu for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 11402965Sksewell@umich.edu DynInstPtr inst; 11412965Sksewell@umich.edu 11423093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11432965Sksewell@umich.edu // Get insts from skidBuffer or from Rename 11442965Sksewell@umich.edu if (skidBuffer.size() > 0) { 11452965Sksewell@umich.edu DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 11462965Sksewell@umich.edu inst = skidBuffer.front(); 11472965Sksewell@umich.edu skidBuffer.pop(); 11482965Sksewell@umich.edu } else { 11492965Sksewell@umich.edu DPRINTF(Commit, "Grabbing rename inst.\n"); 11502965Sksewell@umich.edu inst = fromRename->insts[rename_idx++]; 11512965Sksewell@umich.edu } 11523093Sksewell@umich.edu#else 11533093Sksewell@umich.edu inst = fromRename->insts[inst_num]; 11542965Sksewell@umich.edu#endif 11552292SN/A int tid = inst->threadNumber; 11562292SN/A 11572292SN/A if (!inst->isSquashed() && 11582292SN/A commitStatus[tid] != ROBSquashing) { 11592292SN/A changedROBNumEntries[tid] = true; 11602292SN/A 11612292SN/A DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 11622292SN/A inst->readPC(), inst->seqNum, tid); 11632292SN/A 11642292SN/A rob->insertInst(inst); 11652292SN/A 11662292SN/A assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 11672292SN/A 11682292SN/A youngestSeqNum[tid] = inst->seqNum; 11691061SN/A } else { 11702292SN/A DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11711061SN/A "squashed, skipping.\n", 11722292SN/A inst->readPC(), inst->seqNum, tid); 11731061SN/A } 11741060SN/A } 11752965Sksewell@umich.edu 11763093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 11772965Sksewell@umich.edu if (rename_idx < fromRename->size) { 11782965Sksewell@umich.edu DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 11792965Sksewell@umich.edu 11802965Sksewell@umich.edu for (; 11812965Sksewell@umich.edu rename_idx < fromRename->size; 11822965Sksewell@umich.edu rename_idx++) { 11832965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[rename_idx]; 11842965Sksewell@umich.edu int tid = inst->threadNumber; 11852965Sksewell@umich.edu 11862965Sksewell@umich.edu if (!inst->isSquashed()) { 11872965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 11882965Sksewell@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); 11892965Sksewell@umich.edu skidBuffer.push(inst); 11902965Sksewell@umich.edu } else { 11912965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 11922965Sksewell@umich.edu "squashed, skipping.\n", 11932965Sksewell@umich.edu inst->readPC(), inst->seqNum, tid); 11942965Sksewell@umich.edu } 11952965Sksewell@umich.edu } 11962965Sksewell@umich.edu } 11972965Sksewell@umich.edu#endif 11982965Sksewell@umich.edu 11992965Sksewell@umich.edu} 12002965Sksewell@umich.edu 12012965Sksewell@umich.edutemplate <class Impl> 12022965Sksewell@umich.eduvoid 12032965Sksewell@umich.eduDefaultCommit<Impl>::skidInsert() 12042965Sksewell@umich.edu{ 12052965Sksewell@umich.edu DPRINTF(Commit, "Attempting to any instructions from rename into " 12062965Sksewell@umich.edu "skidBuffer.\n"); 12072965Sksewell@umich.edu 12082965Sksewell@umich.edu for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 12092965Sksewell@umich.edu DynInstPtr inst = fromRename->insts[inst_num]; 12102965Sksewell@umich.edu 12112965Sksewell@umich.edu if (!inst->isSquashed()) { 12122965Sksewell@umich.edu DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 12133221Sktlim@umich.edu "skidBuffer.\n", inst->readPC(), inst->seqNum, 12143221Sktlim@umich.edu inst->threadNumber); 12152965Sksewell@umich.edu skidBuffer.push(inst); 12162965Sksewell@umich.edu } else { 12172965Sksewell@umich.edu DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 12182965Sksewell@umich.edu "squashed, skipping.\n", 12193221Sktlim@umich.edu inst->readPC(), inst->seqNum, inst->threadNumber); 12202965Sksewell@umich.edu } 12212965Sksewell@umich.edu } 12221060SN/A} 12231060SN/A 12241061SN/Atemplate <class Impl> 12251060SN/Avoid 12262292SN/ADefaultCommit<Impl>::markCompletedInsts() 12271060SN/A{ 12281060SN/A // Grab completed insts out of the IEW instruction queue, and mark 12291060SN/A // instructions completed within the ROB. 12301060SN/A for (int inst_num = 0; 12311681SN/A inst_num < fromIEW->size && fromIEW->insts[inst_num]; 12321060SN/A ++inst_num) 12331060SN/A { 12342292SN/A if (!fromIEW->insts[inst_num]->isSquashed()) { 12352316SN/A DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 12362316SN/A "within ROB.\n", 12372292SN/A fromIEW->insts[inst_num]->threadNumber, 12382292SN/A fromIEW->insts[inst_num]->readPC(), 12392292SN/A fromIEW->insts[inst_num]->seqNum); 12401060SN/A 12412292SN/A // Mark the instruction as ready to commit. 12422292SN/A fromIEW->insts[inst_num]->setCanCommit(); 12432292SN/A } 12441060SN/A } 12451060SN/A} 12461060SN/A 12471061SN/Atemplate <class Impl> 12482292SN/Abool 12492292SN/ADefaultCommit<Impl>::robDoneSquashing() 12501060SN/A{ 12512980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 12522292SN/A 12532292SN/A while (threads != (*activeThreads).end()) { 12542292SN/A unsigned tid = *threads++; 12552292SN/A 12562292SN/A if (!rob->isDoneSquashing(tid)) 12572292SN/A return false; 12582292SN/A } 12592292SN/A 12602292SN/A return true; 12611060SN/A} 12622292SN/A 12632301SN/Atemplate <class Impl> 12642301SN/Avoid 12652301SN/ADefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 12662301SN/A{ 12672301SN/A unsigned thread = inst->threadNumber; 12682301SN/A 12692301SN/A // 12702301SN/A // Pick off the software prefetches 12712301SN/A // 12722301SN/A#ifdef TARGET_ALPHA 12732301SN/A if (inst->isDataPrefetch()) { 12742316SN/A statComSwp[thread]++; 12752301SN/A } else { 12762316SN/A statComInst[thread]++; 12772301SN/A } 12782301SN/A#else 12792316SN/A statComInst[thread]++; 12802301SN/A#endif 12812301SN/A 12822301SN/A // 12832301SN/A // Control Instructions 12842301SN/A // 12852301SN/A if (inst->isControl()) 12862316SN/A statComBranches[thread]++; 12872301SN/A 12882301SN/A // 12892301SN/A // Memory references 12902301SN/A // 12912301SN/A if (inst->isMemRef()) { 12922316SN/A statComRefs[thread]++; 12932301SN/A 12942301SN/A if (inst->isLoad()) { 12952316SN/A statComLoads[thread]++; 12962301SN/A } 12972301SN/A } 12982301SN/A 12992301SN/A if (inst->isMemBarrier()) { 13002316SN/A statComMembars[thread]++; 13012301SN/A } 13022301SN/A} 13032301SN/A 13042292SN/A//////////////////////////////////////// 13052292SN/A// // 13062316SN/A// SMT COMMIT POLICY MAINTAINED HERE // 13072292SN/A// // 13082292SN/A//////////////////////////////////////// 13092292SN/Atemplate <class Impl> 13102292SN/Aint 13112292SN/ADefaultCommit<Impl>::getCommittingThread() 13122292SN/A{ 13132292SN/A if (numThreads > 1) { 13142292SN/A switch (commitPolicy) { 13152292SN/A 13162292SN/A case Aggressive: 13172292SN/A //If Policy is Aggressive, commit will call 13182292SN/A //this function multiple times per 13192292SN/A //cycle 13202292SN/A return oldestReady(); 13212292SN/A 13222292SN/A case RoundRobin: 13232292SN/A return roundRobin(); 13242292SN/A 13252292SN/A case OldestReady: 13262292SN/A return oldestReady(); 13272292SN/A 13282292SN/A default: 13292292SN/A return -1; 13302292SN/A } 13312292SN/A } else { 13322292SN/A int tid = (*activeThreads).front(); 13332292SN/A 13342292SN/A if (commitStatus[tid] == Running || 13352292SN/A commitStatus[tid] == Idle || 13362292SN/A commitStatus[tid] == FetchTrapPending) { 13372292SN/A return tid; 13382292SN/A } else { 13392292SN/A return -1; 13402292SN/A } 13412292SN/A } 13422292SN/A} 13432292SN/A 13442292SN/Atemplate<class Impl> 13452292SN/Aint 13462292SN/ADefaultCommit<Impl>::roundRobin() 13472292SN/A{ 13482980Sgblack@eecs.umich.edu std::list<unsigned>::iterator pri_iter = priority_list.begin(); 13492980Sgblack@eecs.umich.edu std::list<unsigned>::iterator end = priority_list.end(); 13502292SN/A 13512292SN/A while (pri_iter != end) { 13522292SN/A unsigned tid = *pri_iter; 13532292SN/A 13542292SN/A if (commitStatus[tid] == Running || 13552831Sksewell@umich.edu commitStatus[tid] == Idle || 13562831Sksewell@umich.edu commitStatus[tid] == FetchTrapPending) { 13572292SN/A 13582292SN/A if (rob->isHeadReady(tid)) { 13592292SN/A priority_list.erase(pri_iter); 13602292SN/A priority_list.push_back(tid); 13612292SN/A 13622292SN/A return tid; 13632292SN/A } 13642292SN/A } 13652292SN/A 13662292SN/A pri_iter++; 13672292SN/A } 13682292SN/A 13692292SN/A return -1; 13702292SN/A} 13712292SN/A 13722292SN/Atemplate<class Impl> 13732292SN/Aint 13742292SN/ADefaultCommit<Impl>::oldestReady() 13752292SN/A{ 13762292SN/A unsigned oldest = 0; 13772292SN/A bool first = true; 13782292SN/A 13792980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 13802292SN/A 13812292SN/A while (threads != (*activeThreads).end()) { 13822292SN/A unsigned tid = *threads++; 13832292SN/A 13842292SN/A if (!rob->isEmpty(tid) && 13852292SN/A (commitStatus[tid] == Running || 13862292SN/A commitStatus[tid] == Idle || 13872292SN/A commitStatus[tid] == FetchTrapPending)) { 13882292SN/A 13892292SN/A if (rob->isHeadReady(tid)) { 13902292SN/A 13912292SN/A DynInstPtr head_inst = rob->readHeadInst(tid); 13922292SN/A 13932292SN/A if (first) { 13942292SN/A oldest = tid; 13952292SN/A first = false; 13962292SN/A } else if (head_inst->seqNum < oldest) { 13972292SN/A oldest = tid; 13982292SN/A } 13992292SN/A } 14002292SN/A } 14012292SN/A } 14022292SN/A 14032292SN/A if (!first) { 14042292SN/A return oldest; 14052292SN/A } else { 14062292SN/A return -1; 14072292SN/A } 14082292SN/A} 1409