commit_impl.hh revision 3771
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#include <algorithm> 36#include <string> 37 38#include "arch/utility.hh" 39#include "base/loader/symtab.hh" 40#include "base/timebuf.hh" 41#include "cpu/exetrace.hh" 42#include "cpu/o3/commit.hh" 43#include "cpu/o3/thread_state.hh" 44 45#if USE_CHECKER 46#include "cpu/checker/cpu.hh" 47#endif 48 49template <class Impl> 50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 51 unsigned _tid) 52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid) 53{ 54 this->setFlags(Event::AutoDelete); 55} 56 57template <class Impl> 58void 59DefaultCommit<Impl>::TrapEvent::process() 60{ 61 // This will get reset by commit if it was switched out at the 62 // time of this event processing. 63 commit->trapSquash[tid] = true; 64} 65 66template <class Impl> 67const char * 68DefaultCommit<Impl>::TrapEvent::description() 69{ 70 return "Trap event"; 71} 72 73template <class Impl> 74DefaultCommit<Impl>::DefaultCommit(Params *params) 75 : squashCounter(0), 76 iewToCommitDelay(params->iewToCommitDelay), 77 commitToIEWDelay(params->commitToIEWDelay), 78 renameToROBDelay(params->renameToROBDelay), 79 fetchToCommitDelay(params->commitToFetchDelay), 80 renameWidth(params->renameWidth), 81 commitWidth(params->commitWidth), 82 numThreads(params->numberOfThreads), 83 drainPending(false), 84 switchedOut(false), 85 trapLatency(params->trapLatency) 86{ 87 _status = Active; 88 _nextStatus = Inactive; 89 std::string policy = params->smtCommitPolicy; 90 91 //Convert string to lowercase 92 std::transform(policy.begin(), policy.end(), policy.begin(), 93 (int(*)(int)) tolower); 94 95 //Assign commit policy 96 if (policy == "aggressive"){ 97 commitPolicy = Aggressive; 98 99 DPRINTF(Commit,"Commit Policy set to Aggressive."); 100 } else if (policy == "roundrobin"){ 101 commitPolicy = RoundRobin; 102 103 //Set-Up Priority List 104 for (int tid=0; tid < numThreads; tid++) { 105 priority_list.push_back(tid); 106 } 107 108 DPRINTF(Commit,"Commit Policy set to Round Robin."); 109 } else if (policy == "oldestready"){ 110 commitPolicy = OldestReady; 111 112 DPRINTF(Commit,"Commit Policy set to Oldest Ready."); 113 } else { 114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive," 115 "RoundRobin,OldestReady}"); 116 } 117 118 for (int i=0; i < numThreads; i++) { 119 commitStatus[i] = Idle; 120 changedROBNumEntries[i] = false; 121 trapSquash[i] = false; 122 tcSquash[i] = false; 123 PC[i] = nextPC[i] = nextNPC[i] = 0; 124 } 125#if FULL_SYSTEM 126 interrupt = NoFault; 127#endif 128} 129 130template <class Impl> 131std::string 132DefaultCommit<Impl>::name() const 133{ 134 return cpu->name() + ".commit"; 135} 136 137template <class Impl> 138void 139DefaultCommit<Impl>::regStats() 140{ 141 using namespace Stats; 142 commitCommittedInsts 143 .name(name() + ".commitCommittedInsts") 144 .desc("The number of committed instructions") 145 .prereq(commitCommittedInsts); 146 commitSquashedInsts 147 .name(name() + ".commitSquashedInsts") 148 .desc("The number of squashed insts skipped by commit") 149 .prereq(commitSquashedInsts); 150 commitSquashEvents 151 .name(name() + ".commitSquashEvents") 152 .desc("The number of times commit is told to squash") 153 .prereq(commitSquashEvents); 154 commitNonSpecStalls 155 .name(name() + ".commitNonSpecStalls") 156 .desc("The number of times commit has been forced to stall to " 157 "communicate backwards") 158 .prereq(commitNonSpecStalls); 159 branchMispredicts 160 .name(name() + ".branchMispredicts") 161 .desc("The number of times a branch was mispredicted") 162 .prereq(branchMispredicts); 163 numCommittedDist 164 .init(0,commitWidth,1) 165 .name(name() + ".COM:committed_per_cycle") 166 .desc("Number of insts commited each cycle") 167 .flags(Stats::pdf) 168 ; 169 170 statComInst 171 .init(cpu->number_of_threads) 172 .name(name() + ".COM:count") 173 .desc("Number of instructions committed") 174 .flags(total) 175 ; 176 177 statComSwp 178 .init(cpu->number_of_threads) 179 .name(name() + ".COM:swp_count") 180 .desc("Number of s/w prefetches committed") 181 .flags(total) 182 ; 183 184 statComRefs 185 .init(cpu->number_of_threads) 186 .name(name() + ".COM:refs") 187 .desc("Number of memory references committed") 188 .flags(total) 189 ; 190 191 statComLoads 192 .init(cpu->number_of_threads) 193 .name(name() + ".COM:loads") 194 .desc("Number of loads committed") 195 .flags(total) 196 ; 197 198 statComMembars 199 .init(cpu->number_of_threads) 200 .name(name() + ".COM:membars") 201 .desc("Number of memory barriers committed") 202 .flags(total) 203 ; 204 205 statComBranches 206 .init(cpu->number_of_threads) 207 .name(name() + ".COM:branches") 208 .desc("Number of branches committed") 209 .flags(total) 210 ; 211 212 commitEligible 213 .init(cpu->number_of_threads) 214 .name(name() + ".COM:bw_limited") 215 .desc("number of insts not committed due to BW limits") 216 .flags(total) 217 ; 218 219 commitEligibleSamples 220 .name(name() + ".COM:bw_lim_events") 221 .desc("number cycles where commit BW limit reached") 222 ; 223} 224 225template <class Impl> 226void 227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) 228{ 229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); 230 cpu = cpu_ptr; 231 232 // Commit must broadcast the number of free entries it has at the start of 233 // the simulation, so it starts as active. 234 cpu->activateStage(O3CPU::CommitIdx); 235 236 trapLatency = cpu->cycles(trapLatency); 237} 238 239template <class Impl> 240void 241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) 242{ 243 thread = threads; 244} 245 246template <class Impl> 247void 248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 249{ 250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n"); 251 timeBuffer = tb_ptr; 252 253 // Setup wire to send information back to IEW. 254 toIEW = timeBuffer->getWire(0); 255 256 // Setup wire to read data from IEW (for the ROB). 257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay); 258} 259 260template <class Impl> 261void 262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 263{ 264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n"); 265 fetchQueue = fq_ptr; 266 267 // Setup wire to get instructions from rename (for the ROB). 268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay); 269} 270 271template <class Impl> 272void 273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 274{ 275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n"); 276 renameQueue = rq_ptr; 277 278 // Setup wire to get instructions from rename (for the ROB). 279 fromRename = renameQueue->getWire(-renameToROBDelay); 280} 281 282template <class Impl> 283void 284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 285{ 286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n"); 287 iewQueue = iq_ptr; 288 289 // Setup wire to get instructions from IEW. 290 fromIEW = iewQueue->getWire(-iewToCommitDelay); 291} 292 293template <class Impl> 294void 295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) 296{ 297 iewStage = iew_stage; 298} 299 300template<class Impl> 301void 302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 303{ 304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); 305 activeThreads = at_ptr; 306} 307 308template <class Impl> 309void 310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[]) 311{ 312 DPRINTF(Commit, "Setting rename map pointers.\n"); 313 314 for (int i=0; i < numThreads; i++) { 315 renameMap[i] = &rm_ptr[i]; 316 } 317} 318 319template <class Impl> 320void 321DefaultCommit<Impl>::setROB(ROB *rob_ptr) 322{ 323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n"); 324 rob = rob_ptr; 325} 326 327template <class Impl> 328void 329DefaultCommit<Impl>::initStage() 330{ 331 rob->setActiveThreads(activeThreads); 332 rob->resetEntries(); 333 334 // Broadcast the number of free entries. 335 for (int i=0; i < numThreads; i++) { 336 toIEW->commitInfo[i].usedROB = true; 337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i); 338 } 339 340 cpu->activityThisCycle(); 341} 342 343template <class Impl> 344bool 345DefaultCommit<Impl>::drain() 346{ 347 drainPending = true; 348 349 return false; 350} 351 352template <class Impl> 353void 354DefaultCommit<Impl>::switchOut() 355{ 356 switchedOut = true; 357 drainPending = false; 358 rob->switchOut(); 359} 360 361template <class Impl> 362void 363DefaultCommit<Impl>::resume() 364{ 365 drainPending = false; 366} 367 368template <class Impl> 369void 370DefaultCommit<Impl>::takeOverFrom() 371{ 372 switchedOut = false; 373 _status = Active; 374 _nextStatus = Inactive; 375 for (int i=0; i < numThreads; i++) { 376 commitStatus[i] = Idle; 377 changedROBNumEntries[i] = false; 378 trapSquash[i] = false; 379 tcSquash[i] = false; 380 } 381 squashCounter = 0; 382 rob->takeOverFrom(); 383} 384 385template <class Impl> 386void 387DefaultCommit<Impl>::updateStatus() 388{ 389 // reset ROB changed variable 390 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 391 while (threads != (*activeThreads).end()) { 392 unsigned tid = *threads++; 393 changedROBNumEntries[tid] = false; 394 395 // Also check if any of the threads has a trap pending 396 if (commitStatus[tid] == TrapPending || 397 commitStatus[tid] == FetchTrapPending) { 398 _nextStatus = Active; 399 } 400 } 401 402 if (_nextStatus == Inactive && _status == Active) { 403 DPRINTF(Activity, "Deactivating stage.\n"); 404 cpu->deactivateStage(O3CPU::CommitIdx); 405 } else if (_nextStatus == Active && _status == Inactive) { 406 DPRINTF(Activity, "Activating stage.\n"); 407 cpu->activateStage(O3CPU::CommitIdx); 408 } 409 410 _status = _nextStatus; 411} 412 413template <class Impl> 414void 415DefaultCommit<Impl>::setNextStatus() 416{ 417 int squashes = 0; 418 419 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 420 421 while (threads != (*activeThreads).end()) { 422 unsigned tid = *threads++; 423 424 if (commitStatus[tid] == ROBSquashing) { 425 squashes++; 426 } 427 } 428 429 squashCounter = squashes; 430 431 // If commit is currently squashing, then it will have activity for the 432 // next cycle. Set its next status as active. 433 if (squashCounter) { 434 _nextStatus = Active; 435 } 436} 437 438template <class Impl> 439bool 440DefaultCommit<Impl>::changedROBEntries() 441{ 442 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 443 444 while (threads != (*activeThreads).end()) { 445 unsigned tid = *threads++; 446 447 if (changedROBNumEntries[tid]) { 448 return true; 449 } 450 } 451 452 return false; 453} 454 455template <class Impl> 456unsigned 457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid) 458{ 459 return rob->numFreeEntries(tid); 460} 461 462template <class Impl> 463void 464DefaultCommit<Impl>::generateTrapEvent(unsigned tid) 465{ 466 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid); 467 468 TrapEvent *trap = new TrapEvent(this, tid); 469 470 trap->schedule(curTick + trapLatency); 471 472 thread[tid]->trapPending = true; 473} 474 475template <class Impl> 476void 477DefaultCommit<Impl>::generateTCEvent(unsigned tid) 478{ 479 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 480 481 tcSquash[tid] = true; 482} 483 484template <class Impl> 485void 486DefaultCommit<Impl>::squashAll(unsigned tid) 487{ 488 // If we want to include the squashing instruction in the squash, 489 // then use one older sequence number. 490 // Hopefully this doesn't mess things up. Basically I want to squash 491 // all instructions of this thread. 492 InstSeqNum squashed_inst = rob->isEmpty() ? 493 0 : rob->readHeadInst(tid)->seqNum - 1;; 494 495 // All younger instructions will be squashed. Set the sequence 496 // number as the youngest instruction in the ROB (0 in this case. 497 // Hopefully nothing breaks.) 498 youngestSeqNum[tid] = 0; 499 500 rob->squash(squashed_inst, tid); 501 changedROBNumEntries[tid] = true; 502 503 // Send back the sequence number of the squashed instruction. 504 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 505 506 // Send back the squash signal to tell stages that they should 507 // squash. 508 toIEW->commitInfo[tid].squash = true; 509 510 // Send back the rob squashing signal so other stages know that 511 // the ROB is in the process of squashing. 512 toIEW->commitInfo[tid].robSquashing = true; 513 514 toIEW->commitInfo[tid].branchMispredict = false; 515 516 toIEW->commitInfo[tid].nextPC = PC[tid]; 517} 518 519template <class Impl> 520void 521DefaultCommit<Impl>::squashFromTrap(unsigned tid) 522{ 523 squashAll(tid); 524 525 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]); 526 527 thread[tid]->trapPending = false; 528 thread[tid]->inSyscall = false; 529 530 trapSquash[tid] = false; 531 532 commitStatus[tid] = ROBSquashing; 533 cpu->activityThisCycle(); 534} 535 536template <class Impl> 537void 538DefaultCommit<Impl>::squashFromTC(unsigned tid) 539{ 540 squashAll(tid); 541 542 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); 543 544 thread[tid]->inSyscall = false; 545 assert(!thread[tid]->trapPending); 546 547 commitStatus[tid] = ROBSquashing; 548 cpu->activityThisCycle(); 549 550 tcSquash[tid] = false; 551} 552 553template <class Impl> 554void 555DefaultCommit<Impl>::tick() 556{ 557 wroteToTimeBuffer = false; 558 _nextStatus = Inactive; 559 560 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) { 561 cpu->signalDrained(); 562 drainPending = false; 563 return; 564 } 565 566 if ((*activeThreads).size() <= 0) 567 return; 568 569 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 570 571 // Check if any of the threads are done squashing. Change the 572 // status if they are done. 573 while (threads != (*activeThreads).end()) { 574 unsigned tid = *threads++; 575 576 if (commitStatus[tid] == ROBSquashing) { 577 578 if (rob->isDoneSquashing(tid)) { 579 commitStatus[tid] = Running; 580 } else { 581 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" 582 " insts this cycle.\n", tid); 583 rob->doSquash(tid); 584 toIEW->commitInfo[tid].robSquashing = true; 585 wroteToTimeBuffer = true; 586 } 587 } 588 } 589 590 commit(); 591 592 markCompletedInsts(); 593 594 threads = (*activeThreads).begin(); 595 596 while (threads != (*activeThreads).end()) { 597 unsigned tid = *threads++; 598 599 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) { 600 // The ROB has more instructions it can commit. Its next status 601 // will be active. 602 _nextStatus = Active; 603 604 DynInstPtr inst = rob->readHeadInst(tid); 605 606 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of" 607 " ROB and ready to commit\n", 608 tid, inst->seqNum, inst->readPC()); 609 610 } else if (!rob->isEmpty(tid)) { 611 DynInstPtr inst = rob->readHeadInst(tid); 612 613 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC " 614 "%#x is head of ROB and not ready\n", 615 tid, inst->seqNum, inst->readPC()); 616 } 617 618 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n", 619 tid, rob->countInsts(tid), rob->numFreeEntries(tid)); 620 } 621 622 623 if (wroteToTimeBuffer) { 624 DPRINTF(Activity, "Activity This Cycle.\n"); 625 cpu->activityThisCycle(); 626 } 627 628 updateStatus(); 629} 630 631template <class Impl> 632void 633DefaultCommit<Impl>::commit() 634{ 635 636 ////////////////////////////////////// 637 // Check for interrupts 638 ////////////////////////////////////// 639 640#if FULL_SYSTEM 641 if (interrupt != NoFault) { 642 // Wait until the ROB is empty and all stores have drained in 643 // order to enter the interrupt. 644 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 645 // Squash or record that I need to squash this cycle if 646 // an interrupt needed to be handled. 647 DPRINTF(Commit, "Interrupt detected.\n"); 648 649 assert(!thread[0]->inSyscall); 650 thread[0]->inSyscall = true; 651 652 // CPU will handle interrupt. 653 cpu->processInterrupts(interrupt); 654 655 thread[0]->inSyscall = false; 656 657 commitStatus[0] = TrapPending; 658 659 // Generate trap squash event. 660 generateTrapEvent(0); 661 662 // Clear the interrupt now that it's been handled 663 toIEW->commitInfo[0].clearInterrupt = true; 664 interrupt = NoFault; 665 } else { 666 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 667 } 668 } else if (cpu->checkInterrupts && 669 cpu->check_interrupts(cpu->tcBase(0)) && 670 commitStatus[0] != TrapPending && 671 !trapSquash[0] && 672 !tcSquash[0]) { 673 // Process interrupts if interrupts are enabled, not in PAL 674 // mode, and no other traps or external squashes are currently 675 // pending. 676 // @todo: Allow other threads to handle interrupts. 677 678 // Get any interrupt that happened 679 interrupt = cpu->getInterrupts(); 680 681 if (interrupt != NoFault) { 682 // Tell fetch that there is an interrupt pending. This 683 // will make fetch wait until it sees a non PAL-mode PC, 684 // at which point it stops fetching instructions. 685 toIEW->commitInfo[0].interruptPending = true; 686 } 687 } 688 689#endif // FULL_SYSTEM 690 691 //////////////////////////////////// 692 // Check for any possible squashes, handle them first 693 //////////////////////////////////// 694 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 695 696 while (threads != (*activeThreads).end()) { 697 unsigned tid = *threads++; 698 699 // Not sure which one takes priority. I think if we have 700 // both, that's a bad sign. 701 if (trapSquash[tid] == true) { 702 assert(!tcSquash[tid]); 703 squashFromTrap(tid); 704 } else if (tcSquash[tid] == true) { 705 squashFromTC(tid); 706 } 707 708 // Squashed sequence number must be older than youngest valid 709 // instruction in the ROB. This prevents squashes from younger 710 // instructions overriding squashes from older instructions. 711 if (fromIEW->squash[tid] && 712 commitStatus[tid] != TrapPending && 713 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) { 714 715 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n", 716 tid, 717 fromIEW->mispredPC[tid], 718 fromIEW->squashedSeqNum[tid]); 719 720 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n", 721 tid, 722 fromIEW->nextPC[tid]); 723 724 commitStatus[tid] = ROBSquashing; 725 726 // If we want to include the squashing instruction in the squash, 727 // then use one older sequence number. 728 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 729 730#if ISA_HAS_DELAY_SLOT 731 InstSeqNum bdelay_done_seq_num = squashed_inst; 732 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 733 734 if (!squash_bdelay_slot) 735 bdelay_done_seq_num++; 736 737#endif 738 739 if (fromIEW->includeSquashInst[tid] == true) { 740 squashed_inst--; 741#if ISA_HAS_DELAY_SLOT 742 bdelay_done_seq_num--; 743#endif 744 } 745 // All younger instructions will be squashed. Set the sequence 746 // number as the youngest instruction in the ROB. 747 youngestSeqNum[tid] = squashed_inst; 748 749#if ISA_HAS_DELAY_SLOT 750 rob->squash(bdelay_done_seq_num, tid); 751 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 752 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 753#else 754 rob->squash(squashed_inst, tid); 755 toIEW->commitInfo[tid].squashDelaySlot = true; 756#endif 757 changedROBNumEntries[tid] = true; 758 759 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 760 761 toIEW->commitInfo[tid].squash = true; 762 763 // Send back the rob squashing signal so other stages know that 764 // the ROB is in the process of squashing. 765 toIEW->commitInfo[tid].robSquashing = true; 766 767 toIEW->commitInfo[tid].branchMispredict = 768 fromIEW->branchMispredict[tid]; 769 770 toIEW->commitInfo[tid].branchTaken = 771 fromIEW->branchTaken[tid]; 772 773 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid]; 774 775 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid]; 776 777 if (toIEW->commitInfo[tid].branchMispredict) { 778 ++branchMispredicts; 779 } 780 } 781 782 } 783 784 setNextStatus(); 785 786 if (squashCounter != numThreads) { 787 // If we're not currently squashing, then get instructions. 788 getInsts(); 789 790 // Try to commit any instructions. 791 commitInsts(); 792 } else { 793#if ISA_HAS_DELAY_SLOT 794 skidInsert(); 795#endif 796 } 797 798 //Check for any activity 799 threads = (*activeThreads).begin(); 800 801 while (threads != (*activeThreads).end()) { 802 unsigned tid = *threads++; 803 804 if (changedROBNumEntries[tid]) { 805 toIEW->commitInfo[tid].usedROB = true; 806 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid); 807 808 if (rob->isEmpty(tid)) { 809 toIEW->commitInfo[tid].emptyROB = true; 810 } 811 812 wroteToTimeBuffer = true; 813 changedROBNumEntries[tid] = false; 814 } 815 } 816} 817 818template <class Impl> 819void 820DefaultCommit<Impl>::commitInsts() 821{ 822 //////////////////////////////////// 823 // Handle commit 824 // Note that commit will be handled prior to putting new 825 // instructions in the ROB so that the ROB only tries to commit 826 // instructions it has in this current cycle, and not instructions 827 // it is writing in during this cycle. Can't commit and squash 828 // things at the same time... 829 //////////////////////////////////// 830 831 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n"); 832 833 unsigned num_committed = 0; 834 835 DynInstPtr head_inst; 836 837 // Commit as many instructions as possible until the commit bandwidth 838 // limit is reached, or it becomes impossible to commit any more. 839 while (num_committed < commitWidth) { 840 int commit_thread = getCommittingThread(); 841 842 if (commit_thread == -1 || !rob->isHeadReady(commit_thread)) 843 break; 844 845 head_inst = rob->readHeadInst(commit_thread); 846 847 int tid = head_inst->threadNumber; 848 849 assert(tid == commit_thread); 850 851 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n", 852 head_inst->seqNum, tid); 853 854 // If the head instruction is squashed, it is ready to retire 855 // (be removed from the ROB) at any time. 856 if (head_inst->isSquashed()) { 857 858 DPRINTF(Commit, "Retiring squashed instruction from " 859 "ROB.\n"); 860 861 rob->retireHead(commit_thread); 862 863 ++commitSquashedInsts; 864 865 // Record that the number of ROB entries has changed. 866 changedROBNumEntries[tid] = true; 867 } else { 868 PC[tid] = head_inst->readPC(); 869 nextPC[tid] = head_inst->readNextPC(); 870 nextNPC[tid] = head_inst->readNextNPC(); 871 872 // Increment the total number of non-speculative instructions 873 // executed. 874 // Hack for now: it really shouldn't happen until after the 875 // commit is deemed to be successful, but this count is needed 876 // for syscalls. 877 thread[tid]->funcExeInst++; 878 879 // Try to commit the head instruction. 880 bool commit_success = commitHead(head_inst, num_committed); 881 882 if (commit_success) { 883 ++num_committed; 884 885 changedROBNumEntries[tid] = true; 886 887 // Set the doneSeqNum to the youngest committed instruction. 888 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; 889 890 ++commitCommittedInsts; 891 892 // To match the old model, don't count nops and instruction 893 // prefetches towards the total commit count. 894 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) { 895 cpu->instDone(tid); 896 } 897 898 PC[tid] = nextPC[tid]; 899#if ISA_HAS_DELAY_SLOT 900 nextPC[tid] = nextNPC[tid]; 901 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); 902#else 903 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); 904#endif 905 906#if FULL_SYSTEM 907 int count = 0; 908 Addr oldpc; 909 do { 910 // Debug statement. Checks to make sure we're not 911 // currently updating state while handling PC events. 912 if (count == 0) 913 assert(!thread[tid]->inSyscall && 914 !thread[tid]->trapPending); 915 oldpc = PC[tid]; 916 cpu->system->pcEventQueue.service( 917 thread[tid]->getTC()); 918 count++; 919 } while (oldpc != PC[tid]); 920 if (count > 1) { 921 DPRINTF(Commit, "PC skip function event, stopping commit\n"); 922 break; 923 } 924#endif 925 } else { 926 DPRINTF(Commit, "Unable to commit head instruction PC:%#x " 927 "[tid:%i] [sn:%i].\n", 928 head_inst->readPC(), tid ,head_inst->seqNum); 929 break; 930 } 931 } 932 } 933 934 DPRINTF(CommitRate, "%i\n", num_committed); 935 numCommittedDist.sample(num_committed); 936 937 if (num_committed == commitWidth) { 938 commitEligibleSamples++; 939 } 940} 941 942template <class Impl> 943bool 944DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) 945{ 946 assert(head_inst); 947 948 int tid = head_inst->threadNumber; 949 950 // If the instruction is not executed yet, then it will need extra 951 // handling. Signal backwards that it should be executed. 952 if (!head_inst->isExecuted()) { 953 // Keep this number correct. We have not yet actually executed 954 // and committed this instruction. 955 thread[tid]->funcExeInst--; 956 957 head_inst->setAtCommit(); 958 959 if (head_inst->isNonSpeculative() || 960 head_inst->isStoreConditional() || 961 head_inst->isMemBarrier() || 962 head_inst->isWriteBarrier()) { 963 964 DPRINTF(Commit, "Encountered a barrier or non-speculative " 965 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n", 966 head_inst->seqNum, head_inst->readPC()); 967 968#if !FULL_SYSTEM 969 // Hack to make sure syscalls/memory barriers/quiesces 970 // aren't executed until all stores write back their data. 971 // This direct communication shouldn't be used for 972 // anything other than this. 973 if (inst_num > 0 || iewStage->hasStoresToWB()) 974#else 975 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() || 976 head_inst->isQuiesce()) && 977 iewStage->hasStoresToWB()) 978#endif 979 { 980 DPRINTF(Commit, "Waiting for all stores to writeback.\n"); 981 return false; 982 } 983 984 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 985 986 // Change the instruction so it won't try to commit again until 987 // it is executed. 988 head_inst->clearCanCommit(); 989 990 ++commitNonSpecStalls; 991 992 return false; 993 } else if (head_inst->isLoad()) { 994 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n", 995 head_inst->seqNum, head_inst->readPC()); 996 997 // Send back the non-speculative instruction's sequence 998 // number. Tell the lsq to re-execute the load. 999 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum; 1000 toIEW->commitInfo[tid].uncached = true; 1001 toIEW->commitInfo[tid].uncachedLoad = head_inst; 1002 1003 head_inst->clearCanCommit(); 1004 1005 return false; 1006 } else { 1007 panic("Trying to commit un-executed instruction " 1008 "of unknown type!\n"); 1009 } 1010 } 1011 1012 if (head_inst->isThreadSync()) { 1013 // Not handled for now. 1014 panic("Thread sync instructions are not handled yet.\n"); 1015 } 1016 1017 // Stores mark themselves as completed. 1018 if (!head_inst->isStore()) { 1019 head_inst->setCompleted(); 1020 } 1021 1022#if USE_CHECKER 1023 // Use checker prior to updating anything due to traps or PC 1024 // based events. 1025 if (cpu->checker) { 1026 cpu->checker->verify(head_inst); 1027 } 1028#endif 1029 1030 // Check if the instruction caused a fault. If so, trap. 1031 Fault inst_fault = head_inst->getFault(); 1032 1033 // DTB will sometimes need the machine instruction for when 1034 // faults happen. So we will set it here, prior to the DTB 1035 // possibly needing it for its fault. 1036 thread[tid]->setInst( 1037 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); 1038 1039 if (inst_fault != NoFault) { 1040 head_inst->setCompleted(); 1041 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", 1042 head_inst->seqNum, head_inst->readPC()); 1043 1044 if (iewStage->hasStoresToWB() || inst_num > 0) { 1045 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1046 return false; 1047 } 1048 1049#if USE_CHECKER 1050 if (cpu->checker && head_inst->isStore()) { 1051 cpu->checker->verify(head_inst); 1052 } 1053#endif 1054 1055 assert(!thread[tid]->inSyscall); 1056 1057 // Mark that we're in state update mode so that the trap's 1058 // execution doesn't generate extra squashes. 1059 thread[tid]->inSyscall = true; 1060 1061 // Execute the trap. Although it's slightly unrealistic in 1062 // terms of timing (as it doesn't wait for the full timing of 1063 // the trap event to complete before updating state), it's 1064 // needed to update the state as soon as possible. This 1065 // prevents external agents from changing any specific state 1066 // that the trap need. 1067 cpu->trap(inst_fault, tid); 1068 1069 // Exit state update mode to avoid accidental updating. 1070 thread[tid]->inSyscall = false; 1071 1072 commitStatus[tid] = TrapPending; 1073 1074 // Generate trap squash event. 1075 generateTrapEvent(tid); 1076// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); 1077 return false; 1078 } 1079 1080 updateComInstStats(head_inst); 1081 1082#if FULL_SYSTEM 1083 if (thread[tid]->profile) { 1084// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); 1085// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); 1086 thread[tid]->profilePC = head_inst->readPC(); 1087 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), 1088 head_inst->staticInst); 1089 1090 if (node) 1091 thread[tid]->profileNode = node; 1092 } 1093#endif 1094 1095 if (head_inst->traceData) { 1096 head_inst->traceData->setFetchSeq(head_inst->seqNum); 1097 head_inst->traceData->setCPSeq(thread[tid]->numInst); 1098 head_inst->traceData->finalize(); 1099 head_inst->traceData = NULL; 1100 } 1101 1102 // Update the commit rename map 1103 for (int i = 0; i < head_inst->numDestRegs(); i++) { 1104 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i), 1105 head_inst->renamedDestRegIdx(i)); 1106 } 1107 1108 if (head_inst->isCopy()) 1109 panic("Should not commit any copy instructions!"); 1110 1111 // Finally clear the head ROB entry. 1112 rob->retireHead(tid); 1113 1114 // Return true to indicate that we have committed an instruction. 1115 return true; 1116} 1117 1118template <class Impl> 1119void 1120DefaultCommit<Impl>::getInsts() 1121{ 1122 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1123 1124#if ISA_HAS_DELAY_SLOT 1125 // Read any renamed instructions and place them into the ROB. 1126 int insts_to_process = std::min((int)renameWidth, 1127 (int)(fromRename->size + skidBuffer.size())); 1128 int rename_idx = 0; 1129 1130 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1131 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1132 skidBuffer.size()); 1133#else 1134 // Read any renamed instructions and place them into the ROB. 1135 int insts_to_process = std::min((int)renameWidth, fromRename->size); 1136#endif 1137 1138 1139 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1140 DynInstPtr inst; 1141 1142#if ISA_HAS_DELAY_SLOT 1143 // Get insts from skidBuffer or from Rename 1144 if (skidBuffer.size() > 0) { 1145 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1146 inst = skidBuffer.front(); 1147 skidBuffer.pop(); 1148 } else { 1149 DPRINTF(Commit, "Grabbing rename inst.\n"); 1150 inst = fromRename->insts[rename_idx++]; 1151 } 1152#else 1153 inst = fromRename->insts[inst_num]; 1154#endif 1155 int tid = inst->threadNumber; 1156 1157 if (!inst->isSquashed() && 1158 commitStatus[tid] != ROBSquashing) { 1159 changedROBNumEntries[tid] = true; 1160 1161 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", 1162 inst->readPC(), inst->seqNum, tid); 1163 1164 rob->insertInst(inst); 1165 1166 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid)); 1167 1168 youngestSeqNum[tid] = inst->seqNum; 1169 } else { 1170 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1171 "squashed, skipping.\n", 1172 inst->readPC(), inst->seqNum, tid); 1173 } 1174 } 1175 1176#if ISA_HAS_DELAY_SLOT 1177 if (rename_idx < fromRename->size) { 1178 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1179 1180 for (; 1181 rename_idx < fromRename->size; 1182 rename_idx++) { 1183 DynInstPtr inst = fromRename->insts[rename_idx]; 1184 int tid = inst->threadNumber; 1185 1186 if (!inst->isSquashed()) { 1187 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1188 "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); 1189 skidBuffer.push(inst); 1190 } else { 1191 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1192 "squashed, skipping.\n", 1193 inst->readPC(), inst->seqNum, tid); 1194 } 1195 } 1196 } 1197#endif 1198 1199} 1200 1201template <class Impl> 1202void 1203DefaultCommit<Impl>::skidInsert() 1204{ 1205 DPRINTF(Commit, "Attempting to any instructions from rename into " 1206 "skidBuffer.\n"); 1207 1208 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) { 1209 DynInstPtr inst = fromRename->insts[inst_num]; 1210 1211 if (!inst->isSquashed()) { 1212 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1213 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1214 inst->threadNumber); 1215 skidBuffer.push(inst); 1216 } else { 1217 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1218 "squashed, skipping.\n", 1219 inst->readPC(), inst->seqNum, inst->threadNumber); 1220 } 1221 } 1222} 1223 1224template <class Impl> 1225void 1226DefaultCommit<Impl>::markCompletedInsts() 1227{ 1228 // Grab completed insts out of the IEW instruction queue, and mark 1229 // instructions completed within the ROB. 1230 for (int inst_num = 0; 1231 inst_num < fromIEW->size && fromIEW->insts[inst_num]; 1232 ++inst_num) 1233 { 1234 if (!fromIEW->insts[inst_num]->isSquashed()) { 1235 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready " 1236 "within ROB.\n", 1237 fromIEW->insts[inst_num]->threadNumber, 1238 fromIEW->insts[inst_num]->readPC(), 1239 fromIEW->insts[inst_num]->seqNum); 1240 1241 // Mark the instruction as ready to commit. 1242 fromIEW->insts[inst_num]->setCanCommit(); 1243 } 1244 } 1245} 1246 1247template <class Impl> 1248bool 1249DefaultCommit<Impl>::robDoneSquashing() 1250{ 1251 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1252 1253 while (threads != (*activeThreads).end()) { 1254 unsigned tid = *threads++; 1255 1256 if (!rob->isDoneSquashing(tid)) 1257 return false; 1258 } 1259 1260 return true; 1261} 1262 1263template <class Impl> 1264void 1265DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst) 1266{ 1267 unsigned thread = inst->threadNumber; 1268 1269 // 1270 // Pick off the software prefetches 1271 // 1272#ifdef TARGET_ALPHA 1273 if (inst->isDataPrefetch()) { 1274 statComSwp[thread]++; 1275 } else { 1276 statComInst[thread]++; 1277 } 1278#else 1279 statComInst[thread]++; 1280#endif 1281 1282 // 1283 // Control Instructions 1284 // 1285 if (inst->isControl()) 1286 statComBranches[thread]++; 1287 1288 // 1289 // Memory references 1290 // 1291 if (inst->isMemRef()) { 1292 statComRefs[thread]++; 1293 1294 if (inst->isLoad()) { 1295 statComLoads[thread]++; 1296 } 1297 } 1298 1299 if (inst->isMemBarrier()) { 1300 statComMembars[thread]++; 1301 } 1302} 1303 1304//////////////////////////////////////// 1305// // 1306// SMT COMMIT POLICY MAINTAINED HERE // 1307// // 1308//////////////////////////////////////// 1309template <class Impl> 1310int 1311DefaultCommit<Impl>::getCommittingThread() 1312{ 1313 if (numThreads > 1) { 1314 switch (commitPolicy) { 1315 1316 case Aggressive: 1317 //If Policy is Aggressive, commit will call 1318 //this function multiple times per 1319 //cycle 1320 return oldestReady(); 1321 1322 case RoundRobin: 1323 return roundRobin(); 1324 1325 case OldestReady: 1326 return oldestReady(); 1327 1328 default: 1329 return -1; 1330 } 1331 } else { 1332 int tid = (*activeThreads).front(); 1333 1334 if (commitStatus[tid] == Running || 1335 commitStatus[tid] == Idle || 1336 commitStatus[tid] == FetchTrapPending) { 1337 return tid; 1338 } else { 1339 return -1; 1340 } 1341 } 1342} 1343 1344template<class Impl> 1345int 1346DefaultCommit<Impl>::roundRobin() 1347{ 1348 std::list<unsigned>::iterator pri_iter = priority_list.begin(); 1349 std::list<unsigned>::iterator end = priority_list.end(); 1350 1351 while (pri_iter != end) { 1352 unsigned tid = *pri_iter; 1353 1354 if (commitStatus[tid] == Running || 1355 commitStatus[tid] == Idle || 1356 commitStatus[tid] == FetchTrapPending) { 1357 1358 if (rob->isHeadReady(tid)) { 1359 priority_list.erase(pri_iter); 1360 priority_list.push_back(tid); 1361 1362 return tid; 1363 } 1364 } 1365 1366 pri_iter++; 1367 } 1368 1369 return -1; 1370} 1371 1372template<class Impl> 1373int 1374DefaultCommit<Impl>::oldestReady() 1375{ 1376 unsigned oldest = 0; 1377 bool first = true; 1378 1379 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1380 1381 while (threads != (*activeThreads).end()) { 1382 unsigned tid = *threads++; 1383 1384 if (!rob->isEmpty(tid) && 1385 (commitStatus[tid] == Running || 1386 commitStatus[tid] == Idle || 1387 commitStatus[tid] == FetchTrapPending)) { 1388 1389 if (rob->isHeadReady(tid)) { 1390 1391 DynInstPtr head_inst = rob->readHeadInst(tid); 1392 1393 if (first) { 1394 oldest = tid; 1395 first = false; 1396 } else if (head_inst->seqNum < oldest) { 1397 oldest = tid; 1398 } 1399 } 1400 } 1401 } 1402 1403 if (!first) { 1404 return oldest; 1405 } else { 1406 return -1; 1407 } 1408} 1409