FuncUnitConfig.py revision 11683:f1e198a028be 
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39# Authors: Kevin Lim
40
41from m5.SimObject import SimObject
42from m5.defines import buildEnv
43from m5.params import *
44from FuncUnit import *
45
46class IntALU(FUDesc):
47    opList = [ OpDesc(opClass='IntAlu') ]
48    count = 6
49
50class IntMultDiv(FUDesc):
51    opList = [ OpDesc(opClass='IntMult', opLat=3),
52               OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
53
54    # DIV and IDIV instructions in x86 are implemented using a loop which
55    # issues division microops.  The latency of these microops should really be
56    # one (or a small number) cycle each since each of these computes one bit
57    # of the quotient.
58    if buildEnv['TARGET_ISA'] in ('x86'):
59        opList[1].opLat=1
60
61    count=2
62
63class FP_ALU(FUDesc):
64    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
65               OpDesc(opClass='FloatCmp', opLat=2),
66               OpDesc(opClass='FloatCvt', opLat=2) ]
67    count = 4
68
69class FP_MultDiv(FUDesc):
70    opList = [ OpDesc(opClass='FloatMult', opLat=4),
71               OpDesc(opClass='FloatMultAcc', opLat=5),
72               OpDesc(opClass='FloatMisc', opLat=3),
73               OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
74               OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
75    count = 2
76
77class SIMD_Unit(FUDesc):
78    opList = [ OpDesc(opClass='SimdAdd'),
79               OpDesc(opClass='SimdAddAcc'),
80               OpDesc(opClass='SimdAlu'),
81               OpDesc(opClass='SimdCmp'),
82               OpDesc(opClass='SimdCvt'),
83               OpDesc(opClass='SimdMisc'),
84               OpDesc(opClass='SimdMult'),
85               OpDesc(opClass='SimdMultAcc'),
86               OpDesc(opClass='SimdShift'),
87               OpDesc(opClass='SimdShiftAcc'),
88               OpDesc(opClass='SimdSqrt'),
89               OpDesc(opClass='SimdFloatAdd'),
90               OpDesc(opClass='SimdFloatAlu'),
91               OpDesc(opClass='SimdFloatCmp'),
92               OpDesc(opClass='SimdFloatCvt'),
93               OpDesc(opClass='SimdFloatDiv'),
94               OpDesc(opClass='SimdFloatMisc'),
95               OpDesc(opClass='SimdFloatMult'),
96               OpDesc(opClass='SimdFloatMultAcc'),
97               OpDesc(opClass='SimdFloatSqrt') ]
98    count = 4
99
100class ReadPort(FUDesc):
101    opList = [ OpDesc(opClass='MemRead'),
102               OpDesc(opClass='FloatMemRead') ]
103    count = 0
104
105class WritePort(FUDesc):
106    opList = [ OpDesc(opClass='MemWrite'),
107               OpDesc(opClass='FloatMemWrite') ]
108    count = 0
109
110class RdWrPort(FUDesc):
111    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
112               OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
113    count = 4
114
115class IprPort(FUDesc):
116    opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ]
117    count = 1
118
119