FuncUnitConfig.py revision 10806:b9410e821c41
112598Snikos.nikoleris@arm.com# Copyright (c) 2010 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Kevin Lim 407584SAli.Saidi@arm.com 417754SWilliam.Wang@arm.comfrom m5.SimObject import SimObject 4212472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 434486SN/Afrom m5.params import * 4412472Sglenn.bergmans@arm.comfrom FuncUnit import * 453630SN/A 463630SN/Aclass IntALU(FUDesc): 4712472Sglenn.bergmans@arm.com opList = [ OpDesc(opClass='IntAlu') ] 4811011SAndreas.Sandberg@ARM.com count = 6 4911011SAndreas.Sandberg@ARM.com 507587SAli.Saidi@arm.comclass IntMultDiv(FUDesc): 5111244Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntMult', opLat=3), 5210353SGeoffrey.Blake@arm.com OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] 538212SAli.Saidi@ARM.com 545478SN/A # DIV and IDIV instructions in x86 are implemented using a loop which 555478SN/A # issues division microops. The latency of these microops should really be 567584SAli.Saidi@arm.com # one (or a small number) cycle each since each of these computes one bit 578931Sandreas.hansson@arm.com # of the quotient. 589525SAndreas.Sandberg@ARM.com if buildEnv['TARGET_ISA'] in ('x86'): 5910397Sstephan.diestelhorst@arm.com opList[1].opLat=1 6012467SCurtis.Dunham@arm.com opList[1].issueLat=1 6111090Sandreas.sandberg@arm.com 6211236Sandreas.sandberg@arm.com count=2 6312232Sgiacomo.travaglini@arm.com 6412472Sglenn.bergmans@arm.comclass FP_ALU(FUDesc): 6512659Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='FloatAdd', opLat=2), 6612741Sandreas.sandberg@arm.com OpDesc(opClass='FloatCmp', opLat=2), 673630SN/A OpDesc(opClass='FloatCvt', opLat=2) ] 6811841Sandreas.sandberg@arm.com count = 4 6911841Sandreas.sandberg@arm.com 7011841Sandreas.sandberg@arm.comclass FP_MultDiv(FUDesc): 7111841Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='FloatMult', opLat=4), 7211841Sandreas.sandberg@arm.com OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), 7311841Sandreas.sandberg@arm.com OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] 7411841Sandreas.sandberg@arm.com count = 2 7511841Sandreas.sandberg@arm.com 7611841Sandreas.sandberg@arm.comclass SIMD_Unit(FUDesc): 7713014Sciro.santilli@arm.com opList = [ OpDesc(opClass='SimdAdd'), 7811841Sandreas.sandberg@arm.com OpDesc(opClass='SimdAddAcc'), 7911841Sandreas.sandberg@arm.com OpDesc(opClass='SimdAlu'), 809806Sstever@gmail.com OpDesc(opClass='SimdCmp'), 819806Sstever@gmail.com OpDesc(opClass='SimdCvt'), 827584SAli.Saidi@arm.com OpDesc(opClass='SimdMisc'), 839338SAndreas.Sandberg@arm.com OpDesc(opClass='SimdMult'), 847584SAli.Saidi@arm.com OpDesc(opClass='SimdMultAcc'), 853898SN/A OpDesc(opClass='SimdShift'), 869806Sstever@gmail.com OpDesc(opClass='SimdShiftAcc'), 877950SAli.Saidi@ARM.com OpDesc(opClass='SimdSqrt'), 887950SAli.Saidi@ARM.com OpDesc(opClass='SimdFloatAdd'), 899338SAndreas.Sandberg@arm.com OpDesc(opClass='SimdFloatAlu'), 909525SAndreas.Sandberg@ARM.com OpDesc(opClass='SimdFloatCmp'), 917950SAli.Saidi@ARM.com OpDesc(opClass='SimdFloatCvt'), 927950SAli.Saidi@ARM.com OpDesc(opClass='SimdFloatDiv'), 937950SAli.Saidi@ARM.com OpDesc(opClass='SimdFloatMisc'), 947950SAli.Saidi@ARM.com OpDesc(opClass='SimdFloatMult'), 957587SAli.Saidi@arm.com OpDesc(opClass='SimdFloatMultAcc'), 967587SAli.Saidi@arm.com OpDesc(opClass='SimdFloatSqrt') ] 977587SAli.Saidi@arm.com count = 4 989338SAndreas.Sandberg@arm.com 997753SWilliam.Wang@arm.comclass ReadPort(FUDesc): 1007753SWilliam.Wang@arm.com opList = [ OpDesc(opClass='MemRead') ] 1019525SAndreas.Sandberg@ARM.com count = 0 1027753SWilliam.Wang@arm.com 1037587SAli.Saidi@arm.comclass WritePort(FUDesc): 1047587SAli.Saidi@arm.com opList = [ OpDesc(opClass='MemWrite') ] 1058282SAli.Saidi@ARM.com count = 0 1068282SAli.Saidi@ARM.com 1079338SAndreas.Sandberg@arm.comclass RdWrPort(FUDesc): 1088282SAli.Saidi@ARM.com opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] 10911296Sandreas.sandberg@arm.com count = 4 11011296Sandreas.sandberg@arm.com 11111296Sandreas.sandberg@arm.comclass IprPort(FUDesc): 11211296Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] 11311296Sandreas.sandberg@arm.com count = 1 11411296Sandreas.sandberg@arm.com 11511296Sandreas.sandberg@arm.com