FuncUnitConfig.py revision 13665
12SN/A# Copyright (c) 2010 ARM Limited 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 48733Sgeoffrey.blake@arm.com# The license below extends only to copyright in the software and shall 58733Sgeoffrey.blake@arm.com# not be construed as granting a license to any other intellectual 68733Sgeoffrey.blake@arm.com# property including but not limited to intellectual property relating 78733Sgeoffrey.blake@arm.com# to a hardware implementation of the functionality of the software 88733Sgeoffrey.blake@arm.com# licensed hereunder. You may use the software subject to the license 98733Sgeoffrey.blake@arm.com# terms below provided that you ensure that this notice is replicated 108733Sgeoffrey.blake@arm.com# unmodified and in its entirety in all distributions of the software, 118733Sgeoffrey.blake@arm.com# modified or unmodified, in source code or in binary form. 128733Sgeoffrey.blake@arm.com# 138733Sgeoffrey.blake@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 148733Sgeoffrey.blake@arm.com# All rights reserved. 152190SN/A# 162SN/A# Redistribution and use in source and binary forms, with or without 172SN/A# modification, are permitted provided that the following conditions are 182SN/A# met: redistributions of source code must retain the above copyright 192SN/A# notice, this list of conditions and the following disclaimer; 202SN/A# redistributions in binary form must reproduce the above copyright 212SN/A# notice, this list of conditions and the following disclaimer in the 222SN/A# documentation and/or other materials provided with the distribution; 232SN/A# neither the name of the copyright holders nor the names of its 242SN/A# contributors may be used to endorse or promote products derived from 252SN/A# this software without specific prior written permission. 262SN/A# 272SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382SN/A# 392SN/A# Authors: Kevin Lim 402665SN/A 412665SN/Afrom m5.SimObject import SimObject 422SN/Afrom m5.defines import buildEnv 432SN/Afrom m5.params import * 442680Sktlim@umich.edu 452680Sktlim@umich.edufrom m5.objects.FuncUnit import * 462SN/A 478229Snate@binkert.orgclass IntALU(FUDesc): 487680Sgblack@eecs.umich.edu opList = [ OpDesc(opClass='IntAlu') ] 497680Sgblack@eecs.umich.edu count = 6 506329Sgblack@eecs.umich.edu 513453Sgblack@eecs.umich.educlass IntMultDiv(FUDesc): 526216Snate@binkert.org opList = [ OpDesc(opClass='IntMult', opLat=3), 536658Snate@binkert.org OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ] 5412104Snathanael.premillieu@arm.com 552SN/A # DIV and IDIV instructions in x86 are implemented using a loop which 562190SN/A # issues division microops. The latency of these microops should really be 572190SN/A # one (or a small number) cycle each since each of these computes one bit 583453Sgblack@eecs.umich.edu # of the quotient. 593453Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ('x86'): 609020Sgblack@eecs.umich.edu opList[1].opLat=1 613453Sgblack@eecs.umich.edu 622190SN/A count=2 6312406Sgabeblack@google.com 648887Sgeoffrey.blake@arm.comclass FP_ALU(FUDesc): 657680Sgblack@eecs.umich.edu opList = [ OpDesc(opClass='FloatAdd', opLat=2), 662313SN/A OpDesc(opClass='FloatCmp', opLat=2), 678706Sandreas.hansson@arm.com OpDesc(opClass='FloatCvt', opLat=2) ] 688706Sandreas.hansson@arm.com count = 4 698706Sandreas.hansson@arm.com 702190SN/Aclass FP_MultDiv(FUDesc): 712190SN/A opList = [ OpDesc(opClass='FloatMult', opLat=4), 723548Sgblack@eecs.umich.edu OpDesc(opClass='FloatMultAcc', opLat=5), 733548Sgblack@eecs.umich.edu OpDesc(opClass='FloatMisc', opLat=3), 743548Sgblack@eecs.umich.edu OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 758902Sandreas.hansson@arm.com OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] 768902Sandreas.hansson@arm.com count = 2 772SN/A 782680Sktlim@umich.educlass SIMD_Unit(FUDesc): 792680Sktlim@umich.edu opList = [ OpDesc(opClass='SimdAdd'), 802680Sktlim@umich.edu OpDesc(opClass='SimdAddAcc'), 812680Sktlim@umich.edu OpDesc(opClass='SimdAlu'), 822680Sktlim@umich.edu OpDesc(opClass='SimdCmp'), 832680Sktlim@umich.edu OpDesc(opClass='SimdCvt'), 842680Sktlim@umich.edu OpDesc(opClass='SimdMisc'), 852680Sktlim@umich.edu OpDesc(opClass='SimdMult'), 862680Sktlim@umich.edu OpDesc(opClass='SimdMultAcc'), 872680Sktlim@umich.edu OpDesc(opClass='SimdShift'), 882680Sktlim@umich.edu OpDesc(opClass='SimdShiftAcc'), 892682Sktlim@umich.edu OpDesc(opClass='SimdSqrt'), 902680Sktlim@umich.edu OpDesc(opClass='SimdFloatAdd'), 912680Sktlim@umich.edu OpDesc(opClass='SimdFloatAlu'), 922680Sktlim@umich.edu OpDesc(opClass='SimdFloatCmp'), 932680Sktlim@umich.edu OpDesc(opClass='SimdFloatCvt'), 942680Sktlim@umich.edu OpDesc(opClass='SimdFloatDiv'), 952SN/A OpDesc(opClass='SimdFloatMisc'), 962107SN/A OpDesc(opClass='SimdFloatMult'), 972107SN/A OpDesc(opClass='SimdFloatMultAcc'), 989920Syasuko.eckert@amd.com OpDesc(opClass='SimdFloatSqrt') ] 9912109SRekai.GonzalezAlberquilla@arm.com count = 4 10012109SRekai.GonzalezAlberquilla@arm.com 1012SN/Aclass ReadPort(FUDesc): 1026029Ssteve.reinhardt@amd.com opList = [ OpDesc(opClass='MemRead'), 103246SN/A OpDesc(opClass='FloatMemRead') ] 104246SN/A count = 0 105246SN/A 106246SN/Aclass WritePort(FUDesc): 107246SN/A opList = [ OpDesc(opClass='MemWrite'), 108246SN/A OpDesc(opClass='FloatMemWrite') ] 109246SN/A count = 0 1102190SN/A 111246SN/Aclass RdWrPort(FUDesc): 112246SN/A opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'), 113246SN/A OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')] 114246SN/A count = 4 115246SN/A 116246SN/Aclass IprPort(FUDesc): 117246SN/A opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] 1182SN/A count = 1 1192680Sktlim@umich.edu 1202423SN/A