intr_control.hh revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302SN/A */ 312SN/A 322SN/A#ifndef __INTR_CONTROL_HH__ 332SN/A#define __INTR_CONTROL_HH__ 342SN/A 35295SN/A#include <vector> 3656SN/A#include "base/misc.hh" 371717SN/A#include "cpu/base.hh" 3856SN/A#include "sim/sim_object.hh" 39295SN/A#include "sim/system.hh" 40295SN/A 412SN/A 422SN/Aclass IntrControl : public SimObject 432SN/A{ 442SN/A public: 452SN/A BaseCPU *cpu; 462SN/A IntrControl(const std::string &name, BaseCPU *c); 472SN/A 482SN/A void clear(int int_num, int index = 0); 492SN/A void post(int int_num, int index = 0); 50295SN/A void clear(int cpu_id, int int_num, int index); 51295SN/A void post(int cpu_id, int int_num, int index); 522SN/A}; 532SN/A 542SN/A#endif // __INTR_CONTROL_HH__ 552SN/A 562SN/A 572SN/A 582SN/A 592SN/A 602SN/A 612SN/A 62