intr_control.cc revision 295
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30#include <vector> 31 32#include "cpu/base_cpu.hh" 33#include "cpu/intr_control.hh" 34#include "sim/builder.hh" 35#include "sim/sim_object.hh" 36 37using namespace std; 38 39IntrControl::IntrControl(const string &name, BaseCPU *c) 40 : SimObject(name), cpu(c) 41{} 42 43/* @todo 44 *Fix the cpu sim object parameter to be a system pointer 45 *instead, to avoid some extra dereferencing 46 */ 47void 48IntrControl::post(int int_num, int index) 49{ 50 std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 51 BaseCPU *temp = xcvec[0]->cpu; 52 temp->post_interrupt(int_num, index); 53} 54 55void 56IntrControl::post(int cpu_id, int int_num, int index) 57{ 58 std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 59 BaseCPU *temp = xcvec[cpu_id]->cpu; 60 temp->post_interrupt(int_num, index); 61} 62 63void 64IntrControl::clear(int int_num, int index) 65{ 66 std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 67 BaseCPU *temp = xcvec[0]->cpu; 68 temp->clear_interrupt(int_num, index); 69} 70 71void 72IntrControl::clear(int cpu_id, int int_num, int index) 73{ 74 std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 75 BaseCPU *temp = xcvec[cpu_id]->cpu; 76 temp->clear_interrupt(int_num, index); 77} 78 79BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 80 81 SimObjectParam<BaseCPU *> cpu; 82 83END_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 84 85BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 86 87 INIT_PARAM(cpu, "the cpu") 88 89END_INIT_SIM_OBJECT_PARAMS(IntrControl) 90 91CREATE_SIM_OBJECT(IntrControl) 92{ 93 return new IntrControl(getInstanceName(), cpu); 94} 95 96REGISTER_SIM_OBJECT("IntrControl", IntrControl) 97